ATMEL AT83C5136 User Manual

BDTIC www.BDTIC.com/ATMEL

Features

• 80C52X2 Core (6 Clocks per Instruction)

– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART), TxD and Rxd are 5 Volt Tolerant – Three 16-bit Timer/Counters: T0, T1 and T2 – 256 Bytes of Scratchpad RAM

• 8/16/32-Kbyte On-chip ROM

• 512 byte or 32-Kbyte EEPROM

• On-chip Expanded RAM (ERAM): 1024 Bytes

• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

• USB 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion (12Mbps)

– Endpoint 0 for Control Transfers: 32-byte FIFO – 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

• Endpoint 1, 2, 3: 32-byte FIFO

• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode) – Suspend/Resume Interrupts – Power-on Reset and USB Bus Reset – 48 MHz DPLL for Full-speed Bus Operation – USB Bus Disconnection on Microcontroller Request

• 5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed

Output, Compare/Capture, PWM and Watchdog Timer Capabilities

• Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to

6s at 4 MHz

• Keyboard Interrupt Interface on Port P1 (8 Bits)

• TWI (Two Wire Interface) 400Kbit/s

• SPI Interface (Master/Slave Mode) MISO,MOSI,SCK and SS are 5 Volt Tolerant

• 34 I/O Pins

• 4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical

• 4-level Priority Interrupt System (11 sources)

• Idle and Power-down Modes

• 0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis

• Industrial Temperature Range

• Low Voltage Range Supply: 2.7V to 3.6V

• Packages: Die SO28, QFN32, MLF48, TQFP64

(1)

8-bit Microcontroller with Full Speed USB Device

AT83C5134 AT83C5135 AT83C5136

Notes: 1. EEPROM only available on MLF48

1. Description

AT83C5134/35/36 are high performance ROM versions of the 80C51 single-chip 8-bit microcontrollers with full speed USB functions.

AT83C5134/35 is pin compatible with AT89C5130A 16Kbytes In-System Programmable Flash microcontrollers.

AT83C5134/35/36

This allows to use AT89C5130A for development, pre-production and flexibility, while using AT83C5134/35 for cost reduction in mass production. Similarly AT83C5136 is pin compatible with AT89C5131A 32-Kbytes Flash microcontroller.

AT83C5134/35/36 features a full-speed USB module compatible with the USB specifications Version 2.0. This module integrates the USB transceivers and the Serial Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recovery. USB Event detection logic (Reset and Suspend/Resume) and FIFO buffers supporting the mandatory control Endpoint (EP0) and 5 versatile Endpoints (EP1/EP2/EP3/EP4/EP5) with minimum software overhead are also part of the USB module.

AT83C5134/35/36 retains the features of the Atmel 80C52 with extended ROM cpacity (8/16/32 Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator.

In addition, AT83C5134/35/36 has an on-chip expanded RAM of 1024 bytes (ERAM), a dualdata pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 programmable LED current sources, a programmable hardware watchdog and a power-on reset.

AT83C5134/35/36 has two software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial ports and the interrupt system are still operating. In the power-down mode the RAM is saved, the peripheral clock is frozen, but the device has full wake-up capability through USB events or external interrupts.

7683C–USB–11/07

3. Block Diagram

Timer 0

INT

RAM

256x8

RxD

TxD

PSEN

ALE

XTAL2

XTAL1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

(2)

C51

CORE

(2) (2) (2) (2)

Port 0P0Port 1

Port 2

Port 3

Parallel I/O Ports & Ext. Bus

ERAM

1Kx8

PCA

RST

Watch

Dog

CEX

ECI

VSS

VDD

(2)(2)

(1)(1)

Timer2

T2EX

(1) (1)

Port 4

32Kx8 ROM

BRG

USB

D -

D +

Key

Board

KIN

EEPROM*

1Kx8

SPI

MISO

MOSI

SCK

(1) (1) (1)

(1)

TWI

SCL

SDA

TWI interface

AT83C5134/35/36

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

3. Alternate function of Port 4

* EEPROM only available in MLF48

7683C–USB–11/07

AT83C5134/35/36

4. Pinout Description

P3.4/T0

P3.5/T1/LED1

ALE

PSEN

PLLF

VREF

D-

D+

17 18 22212019 252423 26 27

62 61 60 59 58 63

57 56 55 54 53

1 2

48 47

41 40

VQFP64

12 13

51 50

15 16

31 32

P1.1/T2EX/KIN1/SS

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

P2.7/A15

P2.6/A14

P4.1/SDA

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P1.0/T2/KIN0

XTAL2

RST

P3.7/RD/LED3

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P3.0/RxD

P0.0/AD0

AVSS

P3.2/INT0

P3.6/WR/LED2

P3.1/TxD

P3.3/INT1/LED0

VSS

P0.6/AD6 P0.7/AD7

P2.5/A13

P0.3/AD3

P0.5/AD5

P0.4/AD4

P0.2/AD2

P0.1/AD1

P4.0/SCL

XTAL1

AVDD

VDD

4.1 Pinout

Figure 4-1. AT83C5134/35/36 64-pin VQFP Pinout

7683C–USB–11/07

Figure 4-2. AT83C5134/35/36 48-pin MLF Pinout

46 45 44 43 42 41 40 39 38

MLF48

P1.1/T2EX/KIN1/SS

P1.0/T2/KIN0

P0.6/AD6

ALE

P0.7/AD7

PSEN

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

PLLF

P3.0/RxD

AVSS

P2.6/A14

XTAL1

P2.5/A13

P0.3/AD3

P0.5/AD5

P0.4/AD4

VREF

P0.2/AD2

P0.0/AD0

P0.1/AD1

AVDD

P3.2/INT0

P3.6/WR/LED2

XTAL2

RST

P3.1/TxD

P3.3/INT1/LED0

P3.7/RD/LED3

D-

P2.1/A9

P2.2/A10

P2.3/A11

VSS

P2.4/A12

P4.1/SDA

D+

P4.0/SCL

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P3.4/T0

P3.5/T1/LED1

VDD

P2.7/A15

29 28

23 22 21

P2.0/A8

P1.1/T2EX/KIN1/SS

PLLF

P3.0/RxD

P1.0/T2/KIN0

AVSS

VDD

XTAL1

XTAL2

P3.2/INT0

P3.5/T1/LED1

P3.6/WR/LED2

P3.7/RD/LED3

D-

P1.4/CEX1/KIN4

VSS

D+

P1.2/ECI/KIN2

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

RST

P1.6/CEX3/KIN6/SCK

P1.7/CEX4/KIN7/MOSI

P4.0/SCL

VREF P3.1/TxD

P3.4/T0

3 4

7 8

27 26

24 23

19 18

SO28

P4.1/SDA

P3.3/INT1/LED0

AT83C5134/35/36

7683C–USB–11/07

Figure 4-3. AT83C5134/35/36 28-pin SO Pinout

AT83C5134/35/36

Figure 4-4. AT83C5134/35/36 32-pin QFN Pinout

QFN32

P1.1/T2EX/KIN1/SS

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

P3.0/RxD

AVSS

XTAL1

VREF

AVDD

P3.2/INT0

P3.5/T1/LED1

XTAL2

RST

P3.1/TxD

P3.3/INT1/LED0

P3.7/RD/LED3

D-

VSS

P4.1/SDA

D+

P4.0/SCL

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P3.4/T0

P1.0/T2/KIN0

VDD

PLLF

P3.6/WR/LED2

UVSS

VSS

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

Note : The metal plate can be connected to Vss

4.2 Signals

All the AT83C5134/35/36 signals are detailed by functionality on Table 4-1 through Table 4-12.

Table 4-1. Keypad Interface Signal Description

Signal

Name Type Description

KIN[7:0) I

Table 4-2. Programmable Counter Array Signal Description

Signal

CEX[4:0] I/O

Name Type Description

ECI I External Clock Input P1.2

Keypad Input Lines

Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt if enabled. Held line is reported in the KBCON register.

Capture External Input

Compare External Output

Alternate Function

P1[7:0]

Alternate Function

P1.3

P1.4

P1.5

P1.6

P1.7

7683C–USB–11/07

Table 4-3. Serial I/O Signal Description

AT83C5134/35/36

Signal

Name Type Description

RxD I

TxD O

Serial Input

The serial input for Extended UART. This I/O is 5 Volt Tolerant.

Serial Output

The serial output for Extended UART. This I/O is 5 Volt Tolerant.

Table 4-4. Timer 0, Timer 1 and Timer 2 Signal Description

Signal

Name Type Description

Timer 0 Gate Input

INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register.

INT0 I

INT1 I

External Interrupt 0

INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low level on INT0.

Timer 1 Gate Input

INT1 serves as external run control for Timer 1, when selected by GATE1 bit in TCON register.

External Interrupt 1

INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by a low level on INT1.

Alternate Function

P3.0

P3.1

Alternate Function

P3.2

P3.3

T0 I

T1 I

T2EX I Timer/Counter 2 Reload/Capture/Direction Control Input P1.1

Timer Counter 0 External Clock Input

When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count.

Timer/Counter 1 External Clock Input

When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count.

IOTimer/Counter 2 External Clock Input

Timer/Counter 2 Clock Output

Table 4-5. LED Signal Description

Signal

Name Type Description

Direct Drive LED Output

These pins can be directly connected to the Cathode of standard LEDs without

LED[3:0] O

external current limiting resistors. The typical current of each output can be programmed by software to 2, 6 or 10 mA. Several outputs can be connected together to get higher drive capabilities.

P3.4

P3.5

P1.0

Alternate Function

P3.3

P3.5

P3.6

P3.7

7683C–USB–11/07

AT83C5134/35/36

Table 4-6. TWI Signal Description

Signal

Name Type Description

SCL I/O

SDA I/O

SCL: TWI Serial Clock

SCL output the serial clock to slave peripherals. SCL input the serial clock from master.

SDA: TWI Serial Data

SCL is the bidirectional TWI data line.

Table 4-7. SPI Signal Description

Signal

Name Type Description

SS I/O SS: SPI Slave Select . This I/O is 5 Volt tolerant P1.1

MISO: SPI Master Input Slave Output line

MISO I/O

SCK I/O

MOSI

When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. This I/O is 5 Volt tolerant

SCK: SPI Serial Clock

SCK outputs clock to the slave peripheral or receive clock from the master.

This I/O is 5 Volt tolerant.

MOSI: SPI Master Output Slave Input line

I/O

When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller.

This I/O is 5 Volt tolerant.

Alternate Function

P4.0

P4.1

Alternate Function

P1.5

P1.6

P1.7

Table 4-8. Ports Signal Description

Signal

Name Type Description Alternate Function

Port 0

P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

P0[7:0] I/O

P1[7:0] I/O

P2[7:0] I/O

have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, Floating P0 inputs must be pulled to V

Port 1

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 2

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

or VSS.

AD[7:0]

KIN[7:0]

T2EX

ECI

CEX[4:0]

A[15:8]

7683C–USB–11/07

AT83C5134/35/36

Signal

Name Type Description Alternate Function

LED[3:0]

RxD

TxD

P3[7:0] I/O

Port 3

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

INT0 INT1

T0 T1

P4[1:0] I/O

Port 4

P4 is an 2-bit open port.

Table 4-9. Clock Signal Description

Signal

Name Type Description

XTAL1 I

XTAL2 O

PLLF I

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin.

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.

PLL Low Pass Filter input

Receives the RC network of the PLL low pass filter (See Figure 5-1 on page 11 ).

Table 4-10. USB Signal Description

Signal

Name Type Description

D+ I/O

USB Data + signal

Set to high level under reset.

SCL

SDA

Alternate Function

7683C–USB–11/07

D- I/O

VREF O

USB Data - signal

Set to low level under reset.

USB Reference Voltage

Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.

Table 4-11. System Signal Description

Signal

Name Type Description

AD[7:0] I/O

A[15:8] I/O

Multiplexed Address/Data LSB for external access

Data LSB for Slave port access (used for 8-bit and 16-bit modes)

Address Bus MSB for external access

Data MSB for Slave port access (used for 16-bit mode only)

Alternate Function

P0[7:0]

P2[7:0]

AT83C5134/35/36

Signal

Name Type Description

Read Signal

RD I/O

WR I/O

RST I/O

ALE O

Read signal asserted during external data memory read operation.

Control input for slave port read access cycles.

Write Signal

Write signal asserted during external data memory write operation.

Control input for slave write access cycles.

Reset

Holding this pin low for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS. Asserting RST when the chip is in Idle mode or Power-down mode returns the chip to normal operation. This pin is set to 0 for at least 12 oscillator periods when an internal reset occurs (hardware watchdog or Power monitor).

Address Latch Enable Output

The falling edge of ALE strobes the address into external latch. This signal is active only when reading or writing external memory using MOVX instructions.

Alternate Function

P3.7

P3.6

PSEN O

EA I

Program Strobe Enable / Hardware conditions Input for ISP

Used as input under reset to detect external hardware conditions of ISP mode

External Access Enable

This pin must be held low to force the device to fetch code from external program memory starting at address 0000h. It is latched during reset and cannot be dynamically changed during operation.

Table 4-12. Power Signal Description

Signal

Name Type Description

AVSS GND

AVDD PWR

VSS GND

VDD PWR

VREF O

Alternate Ground

AVSS is used to supply the on-chip PLL and the USB PAD.

Alternate Supply Voltage

AVDD is used to supply the on-chip PLL and the USB PAD.

Digital Ground

VSS is used to supply the buffer ring and the digital core.

Digital Supply Voltage

VDD is used to supply the buffer ring on all versions of the device.

It is also used to power the on-chip voltage regulator of the Standard versions or the digital core of the Low Power versions.

USB pull-up Controlled Output

VREF is used to control the USB D+ 1.5 kΩ pull up.

The Vref output is in high impedance when the bit DETACH is set in the USBCON register.

Alternate Function

7683C–USB–11/07

5. Typical Application

VSS

XTAL1

XTAL2

22pF

VSS

PLLF

560

820pF

150pF

VSS

AVSS

VSS

D-

D+

27R

VRef

1.5K

USB

D+

D-

VBUS

GND

VSS

VDD

AVDD

VDD

4.7µF

VSS

100nF

VSS

100nF

VSS

AT83C5134/35/3

5.1 Recommended External components

All the external components described in the figure below must be implemented as close as possible from the microcontroller package.

The following figure represents the typical wiring schematic.

Figure 5-1. Typical Application

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

5.2 PCB Recommandations

D+

VRef

D-

USB Connector

Wires must be routed in Parallel and

Components must be

If possible, isolate D+ and D- signals from other signals with ground wires

must be as short as possible

close to the microcontroller

PLLFAVss

Components must be

Isolate filter components

with a ground wire

microcontroller

close to the

Figure 5-2. USB Pads

Note: No sharp angle in above drawing.

Figure 5-3. USB PLL

7683C–USB–11/07

6. Clock Controller

PCON.1

IDL

PCON.0

Peripheral

CPU Core

CKCON.0

Clock

EXT48

PLLCON.2

PLL

USB Clock

6.1 Introduction

The AT83C5134/35/36 clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller.

The AT83C5134/35/36 X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 6-1) that can be configured with off-chip components as a Pierce oscillator (see Figure 6-2). Value of capacitors and crystal characteristics are detailed in the section “DC Characteristics”.

The X1 pin can also be used as input for an external 48 MHz clock.

The clock controller outputs three different clocks as shown in Figure 6-1:

• a clock for the CPU core

• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port

• a clock for the USB controller

These clocks are enabled or disabled depending on the power reduction mode as detailed in Section “Power Management”, page 135.

AT83C5134/35/36

sampling clocks

Figure 6-1. Oscillator Block Diagram

6.2 Oscillator

Two clock sources are available for CPU:

• Crystal oscillator on X1 and X2 pins: Up to 32 MHz

• External 48 MHz clock on X1 pin

7683C–USB–11/07

AT83C5134/35/36

6.3 PLL

VSS

PLLEN

PLLCON.1

N3:0

N divider

R divider

VCO USB Clock

US Bclk

OSCclk R 1+( )×

N 1+

-----------------------------------------------=

PFLD

PLOCK

PLLCON.0

PLLF

CHP

Vref

Down

R3:0

USB

CLOCK

USB Clock Symbol

6.3.1 PLL Description

In order to optimize the power consumption, the oscillator inverter is inactive when the PLL output is not selected for the USB device.

Figure 6-2. Crystal Connection

The AT83C5134/35/36 PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 6-3 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 6-3) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin (see Figure 6-4). Value of the filter components are detailed in the Section “DC Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V the charge pump. It generates a square wave signal: the PLL clock.

Figure 6-3. PLL Block Diagram and Symbol

produced by

REF

7683C–USB–11/07

Figure 6-4. PLL Filter Connection

VSS

PLLF

VSS

PLL

Programming

Configure Dividers

N3:0 = xxxxb R3:0 = xxxxb

Enable PLL

PLLEN = 1

PLL Locked?

LOCK = 1?

The typical values are: R = 560 Ω, C1 = 820 pf, C2 = 150 pF.

6.3.2 PLL Programming

The PLL is programmed using the flow shown in Figure 6-5. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable.

Figure 6-5. PLL Programming Flow

AT83C5134/35/36

6.3.3 Divider Values

7683C–USB–11/07

To generate a 48 MHz clock using the PLL, the divider values have to be configured following the oscillator frequency. The typical divider values are shown in Table 6-1.

Table 6-1. Typical Divider Values

Oscillator Frequency R+1 N+1 PLLDIV

3 MHz 16 1 F0h

6 MHz 8 1 70h

8 MHz 6 1 50h

12 MHz 4 1 30h

16 MHz 3 1 20h

18 MHz 8 3 72h

20 MHz 12 5 B4h

24 MHz 2 1 10h

AT83C5134/35/36

6.4 Registers

Oscillator Frequency R+1 N+1 PLLDIV

32 MHz 3 2 21h

40 MHz 12 10 B9h

Table 6-2. CKCON0 (S:8Fh)

Clock Control Register 0

7 6 5 4 3 2 1 0

TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit Number

7 TWIX2

6 WDX2

5 PCAX2

4 SIX2

3 T2X2

Bit

Mnemonic Description

TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Watchdog Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART Clock (Mode 0 and 2) This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer2 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer1 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

2 T1X2

1 T0X2

0 X2

has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer0 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

System Clock Control bit

Clear to select 12 clock periods per machine cycle (STD mode, F Set to select 6 clock periods per machine cycle (X2 mode, F

Reset Value = 0000 0000b

= F

CPU

CPU = FPER = FOSC

PER = FOSC

7683C–USB–11/07

2).

AT83C5134/35/36

Table 6-3. CKCON1 (S:AFh)

Clock Control Register 1

7 6 5 4 3 2 1 0

- - - - - - - SPIX2

Bit Number

7-1 -

0 SPIX2

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Reset Value = 0000 0000b

Table 6-4. PLLCON (S:A3h)

PLL Control Register

7 6 5 4 3 2 1 0

- - - - - EXT48 PLLEN PLOCK

Bit Number

7-3 -

2 EXT48

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

External 48 MHz Enable Bit

Set this bit to bypass the PLL and disable the crystal oscillator. Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator.

7683C–USB–11/07

PLL Enable Bit

1 PLLEN

0 PLOCK

Set to enable the PLL. Clear to disable the PLL.

PLL Lock Indicator

Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked.

Reset Value = 0000 0000b

Table 6-5. PLLDIV (S:A4h)

PLL Divider Register

7 6 5 4 3 2 1 0

R3 R2 R1 R0 N3 N2 N1 N0

Bit Number

7-4 R3:0 PLL R Divider Bits

3-0 N3:0 PLL N Divider Bits

Bit

Mnemonic Description

Reset Value = 0000 0000

AT83C5134/35/36

7. SFR Mapping

The Special Function Registers (SFRs) of the AT83C5134/35/36 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3, P4

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4)

• Power and clock control registers: PCON

• Hardware Watchdog Timer registers: WDTRST, WDTPRG

• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1

• Keyboard Interface registers: KBE, KBF, KBLS

• LED register: LEDCON

• Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR

• Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT

• USB registers: Uxxx (17 registers)

• PLL registers: PLLCON, PLLDIV

• BRG (Baud Rate Generator) registers: BRL, BDRCON

• Others: AUXR, AUXR1, CKCON0, CKCON1

7683C–USB–11/07

The table below shows all SFRs with their address and their reset value.

Reserved

Table 7-1. SFR Descriptions

Bit

Addressable Non-Bit Addressable

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

AT83C5134/35/36

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

UEPINT

0000 0000

ACC

0000 0000

CCON

00X0 0000

PSW

0000 0000

T2CON

0000 0000

XXXX 1111

IPL0

X000 000

1111 1111

0000 0000

LEDCON

0000 0000

CMOD

00XX X000

T2MOD

XXXX XX00

SADEN

0000 0000

IEN1

X0XX X000

CCAP0H

XXXX XXXX

CCAP0L

XXXX XXXX

UBYCTLX

0000 0000

CCAPM0

X000 0000

RCAP2L

0000 0000

UEPIEN

0000 0000

UFNUML

0000 0000

IPL1

X0XX X000

CCAP1H

XXXX XXXX

CCAP1L

XXXX XXXX

UBYCTHX 0000 0000

CCAPM1

X000 0000

RCAP2H

0000 0000

SPCON

0001 0100

UFNUMH

0000 0000

IPH1

X0XX X000

CCAP2H

XXXX XXXX

CCAP2L

XXXX XXXX

CCAPM2

X000 0000

UEPCONX 1000 0000

TL2

0000 0000

SPSTA

0000 0000

USBCON

0000 0000

CCAP3H

XXXX XXXX

CCAP3L

XXXX XXXX

CCAPM3

X000 0000

UEPRST

0000 0000

TH2

0000 0000

SPDAT

XXXX XXXX

USBINT

0000 0000

CCAP4H

XXXX XXXX

CCAP4L

XXXX XXXX

CCAPM4

X000 0000

UEPSTAX

0000 0000

USBADDR 1000 0000

USBIEN

0000 0000

UEPDATX 0000 0000

UEPNUM

0000 0000

IPH0

X000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

A8h

A0h

98h

90h

88h

80h

IEN0

0000 0000

1111 1111

SCON

0000 0000

1111 1111

TCON

0000 0000

1111 1111

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

SADDR

0000 0000

SBUF

XXXX XXXX

TMOD

0000 0000

0000 0111

AUXR1

XXXX X0X0

BRL

0000 0000

TL0

0000 0000

DPL

0000 0000

PLLCON

XXXX XX00

BDRCON

XXX0 0000

SSCON

0000 0000

TL1

0000 0000

DPH

0000 0000

PLLDIV

0000 0000

1111 1000

0000 0000

Note: 1. FCON access is reserved for the Flash API and ISP software.

The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories:

KBLS

SSCS

TH0

KBE

0000 0000

SSDAT

1111 1111

TH1

0000 0000

WDTRST

XXXX XXXX

KBF

0000 0000

SSADR

1111 1110

AUXR

XX0X 0000

CKCON1

0000 0000

WDTPRG

XXXX X000

CKCON0

0000 0000

PCON

00X1 0000

AFh

A7h

9Fh

97h

8Fh

87h

7683C–USB–11/07

AT83C5134/35/36

Table 7-2. C51 Core SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC E0h Accumulator

B F0h B Register

PSW D0h

SP 81h

DPL 82h

DPH 83h

Program Status Word

Stack Pointer

LSB of SPX

Data Pointer Low byte

LSB of DPTR

Data Pointer High byte

MSB of DPTR

Table 7-3. I/O Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

P0 80h Port 0

P1 90h Port 1

P2 A0h Port 2

P3 B0h Port 3

P4 C0h Port 4 (2bits)

Table 7-4. Timer SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

TH0 8Ch Timer/Counter 0 High byte

TL0 8Ah Timer/Counter 0 Low byte

TH1 8Dh Timer/Counter 1 High byte

TL1 8Bh Timer/Counter 1 Low byte

TH2 CDh Timer/Counter 2 High byte

TL2 CCh Timer/Counter 2 Low byte

TCON 88h

TMOD 89h

T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/Counter 2 Mode T2OE DCEN

Timer/Counter 0 and 1 control

Timer/Counter 0 and 1 Modes

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

7683C–USB–11/07

AT83C5134/35/36

Table 7-4. Timer SFR’s (Continued)

Mnemonic Add Name 7 6 5 4 3 2 1 0

RCAP2H CBh

RCAP2L CAh

WDTRST A6h WatchDog Timer Reset

WDTPRG A7h WatchDog Timer Program S2 S1 S0

Timer/Counter 2 Reload/Capture High byte

Timer/Counter 2 Reload/Capture Low byte

Table 7-5. Serial I/O Port SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer

SADEN B9h Slave Address Mask

SADDR A9h Slave Address

Table 7-6. Baud Rate Generator SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

BRL 9Ah Baud Rate Reload

BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC

Table 7-7. PCA SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter Mode CIDL WDTE CPS1 CPS0 ECF

CL E9h PCA Timer/Counter Low byte

CH F9h PCA Timer/Counter High byte

CCAPM 0

CCAPM 1

CCAPM 2

CCAPM 3

CCAPM 4

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

DCh

PCA Timer/Counter Mode 2

DDh

PCA Timer/Counter Mode 3

DEh

PCA Timer/Counter Mode 4

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

7683C–USB–11/07

AT83C5134/35/36

Table 7-7. PCA SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

CCAP0 H

CCAP1 H

CCAP2 H

CCAP3 H

CCAP4 H

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

PCA Compare Capture Module 0 H

PCA Compare Capture Module 1

FAh

FBh

PCA Compare Capture Module 2

FCh

FDh

PCA Compare Capture Module 3

FEh

PCA Compare Capture Module 4 H

PCA Compare Capture Module 0 L

PCA Compare Capture Module 1

EAh

EBh

PCA Compare Capture Module 2

ECh

EDh

PCA Compare Capture Module 3

EEh

PCA Compare Capture Module 4 L

CCAP0H7

CCAP1H7

CCAP2H7

CCAP3H7

CCAP4H7

CCAP0L7

CCAP1L7

CCAP2L7

CCAP3L7

CCAP4L7

CCAP0H6

CCAP1H6

CCAP2H6

CCAP3H6

CCAP4H6

CCAP0L6

CCAP1L6

CCAP2L6

CCAP3L6

CCAP4L6

CCAP0H5

CCAP1H5

CCAP2H5

CCAP3H5

CCAP4H5

CCAP0L5

CCAP1L5

CCAP2L5

CCAP3L5

CCAP4L5

CCAP0H4

CCAP1H4

CCAP2H4

CCAP3H4

CCAP4H4

CCAP0L4

CCAP1L4

CCAP2L4

CCAP3L4

CCAP4L4

CCAP0H3

CCAP1H3

CCAP2H3

CCAP3H3

CCAP4H3

CCAP0L3

CCAP1L3

CCAP2L3

CCAP3L3

CCAP4L3

CCAP0H2

CCAP1H2

CCAP2H2

CCAP3H2

CCAP4H2

CCAP0L2

CCAP1L2

CCAP2L2

CCAP3L2

CCAP4L2

CCAP0H1

CCAP1H1

CCAP2H1

CCAP3H1

CCAP4H1

CCAP0L1

CCAP1L1

CCAP2L1

CCAP3L1

CCAP4L1

CCAP0H0

CCAP1H0

CCAP2H0

CCAP3H0

CCAP4H0

CCAP0L0

CCAP1L0

CCAP2L0

CCAP3L0

CCAP4L0

Table 7-8. Interrupt SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 B1h Interrupt Enable Control 1 EUSB ESPI ETWI EKB

IPL0 B8h Interrupt Priority Control Low 0 PPCL PT2L PSL PT1L PX1L PT0L PX0L

IPH0 B7h Interrupt Priority Control High 0 PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL1 B2h Interrupt Priority Control Low 1 PUSBL PSPIL PTWIL PKBL

IPH1 B3h Interrupt Priority Control High 1 PUSBH PSPIH PTWIH PKBH

Table 7-9. PLL SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

PLLCON A3h PLL Control EXT48 PLLEN PLOCK

PLLDIV A4h PLL Divider R3 R2 R1 R0 N3 N2 N1 N0

Table 7-10. Keyboard SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

KBF 9Eh

KBE 9Dh

Keyboard Flag Register

Keyboard Input Enable Register

KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0

KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0

7683C–USB–11/07

AT83C5134/35/36

Table 7-10. Keyboard SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

KBLS 9Ch

Keyboard Level Selector Register

KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0

Table 7-11. TWI SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SSCON 93h

SSCS 94h

SSDAT 95h

SSADR 96h

Synchronous Serial Control

Synchronous Serial Control-Status

Synchronous Serial Data

Synchronous Serial Address

CR2 SSIE STA STO SI AA CR1 CR0

SC4 SC3 SC2 SC1 SC0 - - -

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

A7 A6 A5 A4 A3 A2 A1 A0

Table 7-12. SPI SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SPCON C3h

SPSTA C4h

Serial Peripheral Control

Serial Peripheral Status-Control

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPIF WCOL SSERR MODF - - - -

SPDAT C5h Serial Peripheral Data R7 R6 R5 R4 R3 R2 R1 R0

Table 7-13. USB SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

USBCON BCh USB Global Control USBE SUSPCLK

USBADDR C6h USB Address FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0

USBINT BDh USB Global Interrupt - - WUPCPU EORINT SOFINT - - SPINT

USBIEN BEh

UEPNUM C7h USB Endpoint Number - - - - EPNUM3 EPNUM2 EPNUM1 EPNUM0

UEPCONX D4h USB Endpoint X Control EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0

UEPSTAX CEh USB Endpoint X Status DIR RXOUTB1 STALLRQ TXRDY STLCRC RXSETUP RXOUTB0 TXCMP

UEPRST D5h USB Endpoint Reset - - EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST

UEPINT F8h USB Endpoint Interrupt - - EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

UEPIEN C2h

UEPDATX CFh

USB Global Interrupt Enable

USB Endpoint Interrupt Enable

USB Endpoint X FIFO Data

- -

- - EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE

FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0

SDRMWU

EWUPCP

DETACH UPRSM RMWUPE CONFG FADDEN

EEORINT ESOFINT - - ESPINT

7683C–USB–11/07

AT83C5134/35/36

Table 7-13. USB SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

UBYCTLX E2h

UBYCTHX E3h

UFNUML BAh

UFNUMH BBh

USB Byte Counter Low (EP X)

USB Byte Counter High (EP X)

USB Frame Number Low

USB Frame Number High

BYCT7 BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0

- - - - - BYCT10 BYCT9 BYCT8

FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0

- - CRCOK CRCERR - FNUM10 FNUM9 FNUM8

Table 7-14. Other SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL

AUXR 8Eh Auxiliary Register 0 DPU - M0 - XRS1 XRS2 EXTRAM A0

AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 - - DPS

CKCON0 8Fh Clock Control 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

CKCON1 AFh Clock Control 1 - - - - - - - SPIX2

LEDCON F1h LED Control LED3 LED2 LED1 LED0

7683C–USB–11/07

8. Program/Code Memory

0000h

32 Kbytes

7FFFh

ROM

32 Kbytes

External Code

FFFFh

8000h

0000h

16 Kbytes

3FFFh

ROM

48 Kbytes

External Code

FFFFh

4000h

AT83C5135 AT83C5136

Flash

EPROM

AT89C5131

AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

Latch

OEPSEN

The AT83C5134/35/36 implement 16 or 32 Kbytes of on-chip program/code memory. Figure 8-1 shows the split of internal and external program/code memory spaces depending on the product.

Figure 8-1. Program/Code Memory Organization

AT83C5134/35/36

Note: If the program executes exclusively from on-chip code memory (not from external memory),

beware of executing code from the upper byte of on-chip memory and thereby disrupting I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2.

8.1 External Code Memory Access

8.1.1 Memory Interface

The external memory interface comprises the external bus (Port 0 and Port 2) as well as the bus control signals (PSEN, and ALE).

Figure 8-2 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 8-1 describes the external memory interface signals.

Figure 8-2. External Code Memory Interface Structure

7683C–USB–11/07

AT83C5134/35/36

Table 8-1. External Data Memory Interface Signals

ALE

PSEN

PCL

PCHPCH

PCLD7:0 D7:0

PCH

D7:0

CPU Clock

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

PSEN O

8.1.2 External Bus Cycles

This section describes the bus cycles the AT83C5134/35/36 executes to fetch code (see Figure 8-3) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode (see the clock Section).

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information.

Figure 8-3. External Code Fetch Waveforms

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

Address Latch Enable

ALE signals indicates that valid address information are available on lines AD7:0.

Program Store Enable Output

This signal is active low during external code fetch or external code read (MOVC instruction).

Alternate Function

P2.7:0

P0.7:0

7683C–USB–11/07

9. AT89C5131 ROM

9.1 ROM Structure

The AT89C5131 ROM memory is divided in two different arrays:

• the code array: 16-32 Kbytes.

• the configuration byte:1 byte.

9.1.1 Hardware Configuration Byte

The configuration byte sets the starting microcontroller options and the security levels.

The starting default options are X1 mode, Oscillator A.

Table 9-1. Hardware Security Byte (HSB)

7 6 5 4 3 2 1 0

- - OSCON1 OSCON0 - - LB1 LB0

AT83C5134/35/36

HSB (S:EFh) Power configuration Register

Number

HSB = xxxx xx11b

9.2 ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

Bit

7 - Reserved

6 - Reserved

5-4 OSCON1-0

3 - Reserved

2 - Reserved

1-0 LB1-0

Bit

Mnemonic Description

Oscillator Control Bits

These two bits are used to control the oscillator in order to reduce consumption.

OSCON1 OSCON0 Description

1 1 The oscillator is configured to run from 0 to 32 MHz 1 0 The oscillator is configured to run from 0 to 16 MHz 0 1 The oscillator is configured to run from 0 to 8 MHz 0 0 This configuration shouldn’t be set

User Program Lock Bits

See Table 9-2 on page 28

7683C–USB–11/07

AT83C5134/35/36

9.2.1 Program ROM lock Bits

The lock bits when programmed according to Table 9-2 will provide different level of protection for the on-chip code and data.

Table 9-2. Program Lock bits

Program Lock Bits Protection Description

Security

level LB1 LB0

1 U U No program lock feature enabled.

3 P U Reading ROM data from programmer is disabled.

U: unprogrammed P: programmed

7683C–USB–11/07

10. Stacked EEPROM

10.1 Overview

The AT83C5134/35/36 features a stacked 2-wire serial data EEPROM. The data EEPROM allows to save from 512 Byte for AT24C04 version up to 32 Kbytes for AT24C256 version. The EEPROM is internally connected to the microcontroller on SDA and SCL pins.

10.2 Protocol

In order to access this memory, it is necessary to use software subroutines according to the AT 2 4C x x da t as h ee t . Ne v er t he l es s , be c au se t h e in t e rn al p u ll - u p r e si s to r s of t h e AT83C5134/35/36 is quite high (around 100KΩ), the protocol should be slowed in order to be sure that the SDA pin can rise to the high level before reading it.

Another solution to keep the access to the EEPROM in specification is to work with a software pull-up.

Using a software pull-up, consists of forcing a low level at the output pin of the microcontroller before configuring it as an input (high level).

The C51 the ports are “quasi-bidirectional” ports. It means that the ports can be configured as output low or as input high. In case a port is configured as an output low, it can sink a current and all internal pull-ups are disconnected. In case a port is configured as an input high, it is pulled up with a strong pull-up (a few hundreds Ohms resistor) for 2 clock periods. Then, if the port is externally connected to a low level, it is only kept high with a weak pull up (around 100KΩ), and if not, the high level is latched high thanks to a medium pull (around 10kΩ).

AT83C5134/35/36

Thus, when the port is configured as an input, and when this input has been read at a low level, there is a pull-up of around 100KΩ, which is quite high, to quickly load the SDA capacitance. So in order to help the reading of a high level just after the reading of a low level, it is possible to force a transition of the SDA port from an input state (1), to an output low state (0), followed by a new transition from this output low state to input state; In this case, the high pull-up has been replaced with a low pull-up which warranties a good reading of the data.

7683C–USB–11/07

AT83C5134/35/36

11. On-chip Expanded RAM (ERAM)

ERAM

Upper

128 bytes

Internal

RAM

Lower

128 bytes

Internal

RAM

Special Function Register

80h 80h

0FFh or 3FFh(*)

0FFh

External

Data

Memory

0000

00FFh up to 03FFh (*)

0FFFFh

indirect accesses

direct accesses

direct or indirect

accesses

7Fh

(*) Depends on XRS1..0

The AT83C5134/35/36 provides additional Bytes of random access memory (RAM) space for increased data parameters handling and high level language usage.

AT83C5134/35/36 devices have an expanded RAM in the external data space; maximum size and location are described in Table 11-1.

Table 11-1. Description of Expanded RAM

Address

Part Number ERAM Size

AT83C5134/35/36 1024 00h 3FFh

The AT83C5134/35/36 has on-chip data memory which is mapped into the following four separate segments.

1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 11-1)

The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space.

Figure 11-1. Internal and External Data Memory Address

Start End

When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.

7683C–USB–11/07

AT83C5134/35/36

• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,

accesses the SFR at location 0A0h (which is P2).

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For

example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h).

• The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and

MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available ERAM as explained in Table 11-1. This can be useful if external peripherals are mapped at addresses already used by the internal ERAM.

• With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX atR0, # data where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the ERAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to ERAM above 0FFH can only be done by the use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.

MOVX at Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the highorder eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX at Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM.

7683C–USB–11/07

The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

Table 11-2. AUXR Register

AUXR - Auxiliary Register (8Eh)

7 6 5 4 3 2 1 0

DPU - M0 - XRS1 XRS0 EXTRAM AO

Bit

Number

7 DPU

6 -

5 M0

Bit

Mnemonic Description

Disable Weak Pull Up

Cleared to enabled weak pull up on standard Ports. Set to disable weak pull up on standard Ports.

Reserved

The value read from this bit is indeterminate. Do not set this bit

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods (default).

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

AT83C5134/35/36

Bit

Number

Bit

Mnemonic Description

4 -

3 XRS1 ERAM Size

2 XRS0

1 EXTRAM

0 AO

Reset Value = 0X0X 1100b Not bit addressable

Reserved

The value read from this bit is indeterminate. Do not set this bit

XRS1XRS0 ERAM size

0 0 256 bytes

0 1 512 bytes

1 0 768 bytes

1 1 1024 bytes (default)

EXTRAM bit

Cleared to access internal ERAM using MOVX at Ri at DPTR.

Set to access external memory.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) (default).

Set, ALE is active only when a MOVX or MOVC instruction is used.

7683C–USB–11/07

12. Timer 2

The Timer 2 in the AT83C5134/35/36 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2. It is controlled by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, auto reload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).

Refer to the Atmel 8-bit microcontroller hardware documentation for the description of Capture and Baud Rate Generator Modes.

Timer 2 includes the following enhancements:

• Auto-reload mode with up or down counter

• Programmable Clock-output

12.1 Auto-reload Mode

The Auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel 8-bit micro cont roller hardware de scription). If DCEN bit is set, Timer 2 a cts as an Up/dow n timer/counter as shown in Figure 12-1. In this mode the T2EX pin controls the direction of count.

AT83C5134/35/36

/12 (timer operation) or external pin T2 (counter operation) as

OSC

When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

7683C–USB–11/07

AT83C5134/35/36

Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1)

(DOWN COUNTING RELOAD VALUE)

C/T2

TF2

TR2

EXF2

TH2

(8-bit)

TL2

(8-bit)

RCAP2H

(8-bit)

RCAP2L

(8-bit)

FFh

(8-bit)

FFh

(8-bit)

TOGGLE

(UP COUNTING RELOAD VALUE)

Timer 2

INTERRUPT

CLK PERIPH

T2CON

T2EX:

if DCEN = 1, 1 = UP

if DCEN = 1, 0 = DOWN

if DCEN = 0, up counting

: 6

Cl ock OutF requen cy–

CL KPE RIP H

4 65536 RCAP 2H– RCAP2L⁄( )×

-----------------------------------------------------------------------------------------=

12.2 Programmable Clock Output

In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 12-2). The input clock increments TL2 at frequency F edly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts. The following formula gives the Clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers

For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz (F

CLK PERIPH

(P1.0).

Timer 2 is programmed for the Clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value

or a different one depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

16)

to 4 MHz (F

CLK PERIPH

/2. The timer repeat-

/4). The generated clock signal is brought out to T2 pin

7683C–USB–11/07

AT83C5134/35/36

: 6

EXF2

TR2

OVERFLOW

T2EX

TH2

(8-bit)

TL2

(8-bit)

Timer 2

RCAP2H

(8-bit)

RCAP2L

(8-bit)

T2OE

CLK PERIPH

T2CON

T2MOD

INTERRUPT

Q D

Toggle

EXEN2

It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 12-2. Clock-out Mode C/T2 = 0

7683C–USB–11/07

AT83C5134/35/36

Table 12-1. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7 6 5 4 3 2 1 0

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number

7 TF2

6 EXF2

5 RCLK

4 TCLK

3 EXEN2

2 TR2

Bit

Mnemonic Description

Timer 2 overflow Flag

Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1. When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1).

Receive Clock bit

Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port.

Timer 2 Run control bit

Cleared to turn off Timer 2. Set to turn on Timer 2.

1 C/T2#

0 CP/RL2#

Reset Value = 0000 0000b Bit addressable

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

Timer 2 Capture/Reload bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload on Timer 2 overflow. Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

CLK PERIPH

7683C–USB–11/07

AT83C5134/35/36

Table 12-2. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7 6 5 4 3 2 1 0

- - - - - - T2OE DCEN

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 T2OE

0 DCEN

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

Down Counter Enable bit

Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.

Reset Value = xxxx xx00b Not bit addressable

7683C–USB–11/07

AT83C5134/35/36

13. Programmable Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals:

• Peripheral clock frequency (F

CLK PERIPH

) ÷ 6

) ÷ 2

• Timer 0 overflow

• External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

• rising and/or falling edge capture,

• software timer

• high-speed output, or

• pulse width modulator

Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer", page 48).

When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port pin is not used for the PCA, it can still be used for standard I/O.

PCA Component External I/O Pin

16-bit Counter P1.2/ECI

16-bit Module 0 P1.3/CEX0

16-bit Module 1 P1.4/CEX1

16-bit Module 2 P1.5/CEX2

16-bit Module 3 P1.6/CEX3

16-bit Module 4 P1.7/CEX4

The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can be programmed to run at:

• 1/6 the

• 1/2 the

peripheral clock frequency (F peripheral clock frequency (F

CLK PERIPH

)

• The Timer 0 overflow

• The input on the ECI pin (P1.2)

7683C–USB–11/07

Figure 13-1. PCA Timer/Counter

CIDL CPS1 CPS0 ECF

CH CL

16 Bit Up Counter

To PCA modules

CLK PERIPH

T0 OVF

P1.2

Idle

CMOD 0xD9

WDTE

CF CR

CCON 0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

overflow

AT83C5134/35/36

Table 13-1. CMOD Register

CMOD - PCA Counter Mode Register (D9h)

7 6 5 4 3 2 1 0

CIDL WDTE - - - CPS1 CPS0 ECF

Bit

Number

7 CIDL

6 WDTE

5 -

4 -

3 -

2 CPS1 PCA Count Pulse Select

1 CPS0

0 ECF

Bit

Mnemonic Description

Counter Idle Control

Cleared to program the PCA Counter to continue functioning during idle Mode.

Set to program PCA to be gated off during idle.

Watchdog Timer Enable

Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

CPS1CPS0 Selected PCA input 0 0 Internal clock f

0 1 Internal clock f 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = f

PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt.

CLK PERIPH

/ 4)

7683C–USB–11/07

AT83C5134/35/36

Reset Value = 00XX X000b Not bit addressable

The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and Table 13-1).

• The CIDL bit allows the PCA to stop during idle mode.

• The WDTE bit enables or disables the watchdog function on module 4.

• The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR)

to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (see Table 13-2).

• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this

bit.

• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be

generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software.

• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and

are set by hardware when either a match or a capture occurs. These flags can only be cleared by software.

Table 13-2. CCON Register

CCON - PCA Counter Control Register (D8h)

7 6 5 4 3 2 1 0

CF CR – CCF4 CCF3 CCF2 CCF1 CCF0

Bit

Number

7 CF

6 CR

5 –

4 CCF4

3 CCF3

2 CCF2

Bit

Mnemonic Description

PCA Counter Overflow flag

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software.

PCA Counter Run control bit

Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA Module 4 interrupt flag

Must be cleared by software. Set by hardware when a match or capture occurs.

PCA Module 3 interrupt flag

Must be cleared by software. Set by hardware when a match or capture occurs.

PCA Module 2 interrupt flag

Must be cleared by software. Set by hardware when a match or capture occurs.

7683C–USB–11/07

AT83C5134/35/36

CF CR

CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

Module 4

Module 3

Module 2

Module 1

Module 0

ECF

PCA Timer/Counter

ECCFn

CCAPMn.0CMOD.0

IE.6 IE.7

To Interrupt

priority decoder

EC EA

Bit

Number

1 CCF1

0 CCF0

Reset Value = 000X 0000b Not bit addressable

The watchdog timer function is implemented in module 4 (See Figure 13-4).

The PCA interrupt system is shown in Figure 13-2.

Figure 13-2. PCA Interrupt System

Bit

Mnemonic Description

PCA Module 1 Interrupt Flag

Must be cleared by software. Set by hardware when a match or capture occurs.

PCA Module 0 Interrupt Flag

Must be cleared by software. Set by hardware when a match or capture occurs.

7683C–USB–11/07

PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:

• 16-bit capture, positive-edge triggered

• 16-bit capture, negative-edge triggered

• 16-bit capture, both positive and negative-edge triggered

• 16-bit Software Timer

• 16-bit High-speed Output

• 8-bit Pulse Width Modulator

In addition, module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Table 13-3). The registers contain the bits that control the mode that each module will operate in.

AT83C5134/35/36

• The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the

CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module.

• PWM (CCAPMn.1) enables the pulse width modulation mode.

• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to

toggle when there is a match between the PCA counter and the module's capture/compare register.

• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be

set when there is a match between the PCA counter and the module's capture/compare register.

• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition.

• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

Table 13-4 shows the CCAPMn settings for the various PCA functions.

Table 13-3. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)

CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)

7 6 5 4 3 2 1 0

- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Bit

Number

7 -

6 ECOMn

5 CAPPn

4 CAPNn

3 MATn

2 TOGn

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Enable Comparator

Cleared to disable the comparator function.

Set to enable the comparator function.

Capture Positive

Cleared to disable positive edge capture. Set to enable positive edge capture.

Capture Negative

Cleared to disable negative edge capture. Set to enable negative edge capture.

Match

When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the

CCFn bit in CCON to be set, flagging an interrupt.

Toggle

When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle.

7683C–USB–11/07

AT83C5134/35/36

Bit

Number

1 PWMn

0 ECCFn

Bit

Mnemonic Description

Pulse Width Modulation Mode

Cleared to disable the CEXn pin to be used as a pulse width modulated output.

Set to enable the CEXn pin to be used as a pulse width modulated output.

Enable CCF Interrupt

Cleared to disable compare/capture flag CCFn in the CCON register to generate an interrupt.

Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt.

Reset Value = X000 0000b Not bit addressable

Table 13-4. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function

0 0 0 0 0 0 0 No Operation

X 1 0 0 0 0 X

X 0 1 0 0 0 X

X 1 1 0 0 0 X

16-bit capture by a positive-edge trigger on CEXn

16-bit capture by a negative trigger on CEXn

16-bit capture by a transition on CEXn

1 0 0 1 0 0 X

1 0 0 1 1 0 X 16-bit High Speed Output

1 0 0 0 0 1 0 8-bit PWM

1 0 0 1 X 0 X Watchdog Timer (module 4 only)

16-bit Software Timer/Compare mode.

There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (see Table 13-5 and Table 13-6)

7683C–USB–11/07

AT83C5134/35/36

Table 13-5. CCAPnH Registers (n = 0-4)

CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number

7 - 0 -

Bit

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnH Value

Reset Value = XXXX XXXXb Not bit addressable

Table 13-6. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)

CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number

7 - 0 -

Bit

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnL Value

Reset Value = XXXX XXXXb Not bit addressable

Table 13-7. CH Register CH - PCA Counter Register High (0F9h)

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number

7 - 0 -

Bit

Mnemonic Description

PCA counter

CH Value

Reset Value = 0000 0000b Not bit addressable

7683C–USB–11/07

AT83C5134/35/36

CF CR

CCON 0xD8

CH CL

CCAPnH CCAPnL

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

PCA Counter/Timer

ECOMn

CCAPMn, n = 0 to 4 0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

Cex.n

Capture

Table 13-8. CL Register CL - PCA Counter Register Low (0E9h)

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number

7 - 0 -

Reset Value = 0000 0000b Not bit addressable

13.1 PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (see Figure 13-3).

Figure 13-3. PCA Capture Mode

Bit

Mnemonic Description

PCA Counter

CL Value

13.2 16-bit Software Timer/Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in

7683C–USB–11/07

the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 13-4).

AT83C5134/35/36

Figure 13-4. PCA Compare Mode and PCA Watchdog Timer

CH CL

CCAPnH CCAPnL

ECOMn

CCAPMn, n = 0 to 4

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

16-bit Comparator

Match

CCON

0xD8

PCA IT

Enable

PCA Counter/Timer

RESET

(1)

CIDL CPS1 CPS0 ECF

CMOD

0xD9

WDTE

Reset

Write to

CCAPnL

Write to

CCAPnH

CF CCF2 CCF1 CCF0

CCF3

CCF4

1 0

Note: 1. Only for Module 4

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

13.3 High Speed Output Mode

In this mode, the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode th e TOG, MAT, and EC OM bits in t he module's CCAPMn SFR must be se t (see Figure 13-5).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

7683C–USB–11/07

Figure 13-5. PCA High-speed Output Mode

CH CL

CCAPnH CCAPnL

ECOMn

CCAPMn, n = 0 to 4

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

16-bit Comparator

Match

CF CR

CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

Enable

CEXn

PCA counter/timer

Write to

CCAPnH

Reset

Write to

CCAPnL

AT83C5134/35/36

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen.

13.4 Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 13-6 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.

7683C–USB–11/07

AT83C5134/35/36

Figure 13-6. PCA PWM Mode

CCAPnH

CCAPnL

ECOMn

CCAPMn, n = 0 to 4

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

8-bit Comparator

CEXn

“0”

“1”

≥

Enable

PCA Counter/Timer

Overflow

13.5 PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 13-4 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven low.

In order to hold off the reset, the user has three options:

1. Periodically change the compare value so it will never match the PCA timer

2. Periodically change the PCA timer value so it will never match the compare values, or

3. Disable the watchdog by clearing the WDTE bit before a match occurs and then reenable it

The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

7683C–USB–11/07

14. Serial I/O Port

RITIRB8TB8RENSM2SM1SM0/FE

IDLPDGF0GF1POF-SMOD0SMOD1

To UART Framing Error Control

SM0 to UART Mode Control (SMOD0 = 0)

Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1)

SCON (98h)

PCON (87h)

Data Byte

SMOD0 = X

Stop

Bit

Start

Bit

RXD

D7D6D5D4D3D2D1D0

SMOD0 = 1

The serial I/O port in the AT83C5134/35/36 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates.

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

14.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 14-

1).

Figure 14-1. Framing Error Block Diagram

AT83C5134/35/36

7683C–USB–11/07

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table

14-1) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure

14-2 and Figure 14-3).

Figure 14-2. UART Timings in Mode 1

AT83C5134/35/36

Figure 14-3. UART Timings in Modes 2 and 3

SMOD0 = 0

Data Byte Ninth

Bit

Stop

Bit

Start

Bit

RXD

D8D7D6D5D4D3D2D1D0

SMOD0 = 1

14.2 Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit.

14.2.1 Given Address

To support automatic address recognition, a device is identified by a given address and a broadcast address.

Note: The multiprocessor communication and automatic address recognition features cannot be

enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).

Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t care bits (defined by zeros) to form the device’s given address. The don’t care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:

SADDR0101 0110b SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

7683C–USB–11/07

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

14.2.2 Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t care bits, e.g.:

AT83C5134/35/36

Slave C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

SADDR0101 0110b SADEN1111 1100b

Broadcast = SADDR OR SADEN1111 111Xb

The use of don’t care bits provides flexibility in defining the broadcast address, in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.

14.2.3 Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR = 1111 0011b

SADEN1111 1101b

Broadcast1111 1111b

7683C–USB–11/07

AT83C5134/35/36

SADEN - Slave Address Mask Register (B9h)

RCLK

/ 16

RBCK

INT_BRG

TIMER1

TIMER2

INT_BRG

TIMER1

TIMER2

TIMER_BRG_RX

Rx Clock

/ 16

TIMER_BRG_TX

Tx Clock

TBCK

TCLK

7 6 5 4 3 2 1 0

Reset Value = 0000 0000b Not bit addressable

SADDR - Slave Address Register (A9h)

7 6 5 4 3 2 1 0

Reset Value = 0000 0000b Not bit addressable

14.3 Baud Rate Selection for UART for Mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers.

Figure 14-4. Baud Rate Selection

7683C–USB–11/07

14.3.1 Baud Rate Selection Table for UART

BRG

BRL

INT_BRG

SPD

BRR

SMOD1

auto reload counter

overflow

Peripheral Clock

Baud_Rate =

SMOD1

x FCLK PERIPH

2 x 6

(1-SPD)

x 16 x [256 - (BRL)]

(BRL) = 256

SMOD1

x F

CLK PERIPH

2 x 6

(1-SPD)

x 16 x Baud_Rate

AT83C5134/35/36

TCLK

(T2CON)

0 0 0 0 Timer 1 Timer 1

1 0 0 0 Timer 2 Timer 1

0 1 0 0 Timer 1 Timer 2

1 1 0 0 Timer 2 Timer 2

X 0 1 0 INT_BRG Timer 1

X 1 1 0 INT_BRG Timer 2

0 X 0 1 Timer 1 INT_BRG

1 X 0 1 Timer 2 INT_BRG

X X 1 1 INT_BRG INT_BRG

RCLK

(T2CON)

(BDRCON)

14.3.2 Internal Baud Rate Generator (BRG)

When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register.

Figure 14-5. Internal Baud Rate

TBCK

RBCK

(BDRCON)

Clock Source

UART Tx

Clock Source

UART Rx

7683C–USB–11/07

• The baud rate for UART is token by formula:

Table 14-1. SCON Register – SCON Serial Control Register (98h)

7 6 5 4 3 2 1 0

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

AT83C5134/35/36

Bit

Number

6 SM1

5 SM2

Bit

Mnemonic Description

Framing Error bit (SMOD0 = 1)

SM0

Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected.

SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1

SM0 SM1 Mode Description Baud Rate 0 0 0 Shift Register F 0 1 1 8-bit UART Variable 1 0 2 9-bit UART F

1 1 3 9-bit UART Variable

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0.

CPU PERIPH

CPU PERIPH/

32 or/16

4 REN

3 TB8

2 RB8

1 TI

0 RI

Reception Enable bit

Clear to disable serial reception. Set to enable serial reception.

Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3

Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8/Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.

Receive Interrupt flag

Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and Figure 14-

3. in the other modes.

Reset Value = 0000 0000b Bit addressable

7683C–USB–11/07

AT83C5134/35/36

Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1

= 16.384 MHz F

Baud Rates

115200 247 1.23 243 0.16

57600 238 1.23 230 0.16

38400 229 1.23 217 0.16

28800 220 1.23 204 0.16

19200 203 0.63 178 0.16

9600 149 0.31 100 0.16

4800 43 1.23 - -

OSC

BRL Error (%) BRL Error (%)

Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0

= 16.384 MHz F

OSC

Baud Rates

4800 247 1.23 243 0.16

BRL Error (%) BRL Error (%)

OSC

= 24 MHz

The baud rate generator can be used for mode 1 or 3 (refer to Figure 14-4.), but also for mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 14-4.)

14.4 UART Registers

SADEN - Slave Address Mask Register for UART (B9h)

Reset Value = 0000 0000b

SADDR - Slave Address Register for UART (A9h)

Reset Value = 0000 0000b

2400 238 1.23 230 0.16

1200 220 1.23 202 3.55

600 185 0.16 152 0.16

7 6 5 4 3 2 1 0

– – – – – – – –

7 6 5 4 3 2 1 0

– – – – – – – –

7683C–USB–11/07

SBUF - Serial Buffer Register for UART (99h)

7 6 5 4 3 2 1 0

– – – – – – – –

Reset Value = XXXX XXXXb

AT83C5134/35/36

BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)

7 6 5 4 3 2 1 0

– – – – – – – –

Reset Value = 0000 0000b

Table 14-2. T2CON Register T2CON - Timer 2 Control Register (C8h)

7 6 5 4 3 2 1 0

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number

7 TF2

6 EXF2

5 RCLK

4 TCLK

3 EXEN2

2 TR2

Bit

Mnemonic Description

Timer 2 overflow Flag

Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Receive Clock bit for UART

Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit for UART

Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port.

Timer 2 Run control bit

Cleared to turn off Timer 2. Set to turn on Timer 2.

Timer/Counter 2 select bit

1 C/T2#

0 CP/RL2#

Cleared for timer operation (input from internal clock system: F Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

Timer 2 Capture/Reload bit

Reset Value = 0000 0000b Bit addressable

CLK PERIPH

7683C–USB–11/07

AT83C5134/35/36

Table 14-3. PCON Register

PCON - Power Control Register (87h)

7 6 5 4 3 2 1 0

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number

7 SMOD1

6 SMOD0

5 -

4 POF

3 GF1

2 GF0

1 PD

0 IDL

Bit

Mnemonic Description

Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0 for UART

Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General-purpose Flag

Cleared by user for general-purpose usage. Set by user for general-purpose usage.

General-purpose Flag

Cleared by user for general-purpose usage. Set by user for general-purpose usage.

Power-down Mode Bit

Cleared by hardware when reset occurs. Set to enter power-down mode.

Idle Mode Bit

Cleared by hardware when interrupt or reset occurs. Set to enter idle mode.

7683C–USB–11/07

Reset Value = 00x1 0000b Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.

AT83C5134/35/36

Table 14-4. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7 6 5 4 3 2 1 0

- - - BRR TBCK RBCK SPD SRC

Bit

Number

7 -

6 -

5 -

4 BRR

3 TBCK

2 RBCK

1 SPD

0 SRC

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator.

Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

Cleared to select F Set to select the internal Baud Rate Generator for UARTs in mode 0.

/12 as the Baud Rate Generator (F

OSC

CLK PERIPH

/6 in X2 mode).

Reset Value = xxx0 0000b Not bit addressable

7683C–USB–11/07

15. Dual Data Pointer Register

External Data Memory

AUXR1(A2H)

DPS

DPH(83H) DPL(82H)

DPTR0

DPTR1

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 15-1) that allows the program code to switch between them (see Figure 15-1).

Figure 15-1. Use of Dual Pointer

AT83C5134/35/36

Table 15-1. AUXR1 Register

AUXR1- Auxiliary Register 1(0A2h)

7 6 5 4 3 2 1 0

- - - - GF3 0 - DPS

Bit

Number

7 -

6 -

5 -

4 -

3 GF3 This bit is a general-purpose user flag.

2 0 Always cleared.

1 -

0 DPS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0. Set to select DPTR1.

Reset Value = xxxx x0x0b Not bit addressable

7683C–USB–11/07

a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

AT83C5134/35/36

; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

7683C–USB–11/07

16. Interrupt System

IE1

High priority interrupt

Interrupt Polling Sequence, Decreasing From

High-to-Low Priority

Low Priority

Interrupt

Global DisableIndividual Enable

EXF2

TF2

TF0

INT0

INT1

TF1

IPH, IPL

IE0

PCA IT

KBD IT

SPI IT

UEPINT

USBINT

TWI IT

IT0

TCON.0

IT1

TCON.2

16.1 Overview

The AT83C5134/35/36 has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1.

Figure 16-1. Interrupt Control System

AT83C5134/35/36

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 16-2). This register also contains a global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority

7683C–USB–11/07

AT83C5134/35/36

16.2 Registers

High register (Table 16-4). Table 16-1. shows the bit values and priority levels associated with each combination.

The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same as standard C52 devices.

Table 16-1. Priority Level Bit Values

IPH.x IPL.x Interrupt Level Priority

0 0 0 (Lowest)

0 1 1

1 0 2

1 1 3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence.

7683C–USB–11/07

AT83C5134/35/36

Table 16-2. IEN0 Register

IEN0 - Interrupt Enable Register (A8h)

7 6 5 4 3 2 1 0

EA EC ET2 ES ET1 EX1 ET0 EX0

Bit

Number

7 EA

6 EC

5 ET2

4 ES

3 ET1

2 EX1

1 ET0

Bit

Mnemonic Description

Enable All interrupt bit

Cleared to disable all interrupts. Set to enable all interrupts.

PCA interrupt enable bit

Cleared to disable.

Set to enable.

Timer 2 overflow interrupt Enable bit

Cleared to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt.

Serial port Enable bit

Cleared to disable serial port interrupt. Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Cleared to disable Timer 1 overflow interrupt. Set to enable Timer 1 overflow interrupt.

External interrupt 1 Enable bit

Cleared to disable external interrupt 1. Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.

0 EX0

Reset Value = 0000 0000b Bit addressable

External interrupt 0 Enable bit

Cleared to disable external interrupt 0. Set to enable external interrupt 0.

7683C–USB–11/07

AT83C5134/35/36

Table 16-3. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)

7 6 5 4 3 2 1 0

- PPCL PT2L PSL PT1L PX1L PT0L PX0L

Bit

Number

7 -

6 PPCL

5 PT2L

4 PSL

3 PT1L

2 PX1L

1 PT0L

0 PX0L

Bit

Mnemonic Description

Reset Value = x000 0000b Bit addressable

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt Priority bit

Refer to PPCH for priority level.

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

7683C–USB–11/07

AT83C5134/35/36

Table 16-4. IPH0 Register

IPH0 - Interrupt Priority High Register (B7h)

7 6 5 4 3 2 1 0

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

Bit

Number

7 -

6 PPCH

5 PT2H

4 PSH

3 PT1H

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt Priority high bit.

PPCH PPCL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

Timer 2 overflow interrupt Priority High bit

PT2H PT2L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

Serial port Priority High bit

PSH PSL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

7683C–USB–11/07

2 PX1H

1 PT0H

0 PX0H

Reset Value = x000 0000b Not bit addressable

External interrupt 1 Priority High bit

PX1H PX1L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

External interrupt 0 Priority High bit

PX0H PX0L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

AT83C5134/35/36

Table 16-5. IEN1 Register

IEN1 - Interrupt Enable Register (B1h)

7 6 5 4 3 2 1 0

- EUSB - - - ESPI ETWI EKB

Bit

Number

7 - Reserved

6 EUSB

5 - Reserved

4 - Reserved

3 - Reserved

2 ESPI

1 ETWI

0 EKB

Bit

Mnemonic Description

Reset Value = x0xx x000b Not bit addressable

USB Interrupt Enable bit

Cleared to disable USB interrupt. Set to enable USB interrupt.

SPI interrupt Enable bit

Cleared to disable SPI interrupt. Set to enable SPI interrupt.

TWI interrupt Enable bit

Cleared to disable TWI interrupt. Set to enable TWI interrupt.

Keyboard interrupt Enable bit

Cleared to disable keyboard interrupt. Set to enable keyboard interrupt.

7683C–USB–11/07

AT83C5134/35/36

Table 16-6. IPL1 Register

IPL1 - Interrupt Priority Register (B2h)

7 6 5 4 3 2 1 0

- PUSBL - - - PSPIL PTWIL PKBDL

Bit

Number

7 -

6 PUSBL

5 -

4 -

3 -

2 PSPIL

1 PTWIL

0 PKBL

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

USB Interrupt Priority bit

Refer to PUSBH for priority level.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority bit

Refer to PSPIH for priority level.

TWI Interrupt Priority bit

Refer to PTWIH for priority level.

Keyboard Interrupt Priority bit

Refer to PKBH for priority level.

Reset Value = X0XX X000b Not bit addressable

7683C–USB–11/07

AT83C5134/35/36

Table 16-7. IPH1 Register

IPH1 - Interrupt Priority High Register (B3h)

7 6 5 4 3 2 1 0

- PUSBH - - - PSPIH PTWIH PKBH

Bit

Number

7 -

6 PUSBH

5 -

4 -

3 -

2 PSPIH

1 PTWIH

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

USB Interrupt Priority High bit

PUSBHPUSBLPriority Level 0 0 Lowest 0 1 1 0 1 1 Highest

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority High bit

PSPIHPSPIL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

TWI Interrupt Priority High bit

PTWIHPTWIL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

Keyboard Interrupt Priority High bit

PKBH PKBL Priority Level

0 PKBH

0 0 Lowest 0 1 1 0 1 1 Highest

Reset Value = X0XX X000b Not bit addressable

7683C–USB–11/07

16.3 Interrupt Sources and Vector Addresses

Table 16-8. Vector Table

AT83C5134/35/36

Number

0 0 Reset 0000h

1 1 INT0 IE0 0003h

2 2 Timer 0 TF0 000Bh

3 3 INT1 IE1 0013h

4 4 Timer 1 IF1 001Bh

5 6 UART RI+TI 0023h

6 7 Timer 2 TF2+EXF2 002Bh

7 5 PCA CF + CCFn (n = 0-4) 0033h

8 8 Keyboard KBDIT 003Bh

9 9 TWI TWIIT 0043h

10 10 SPI SPIIT 004Bh

11 11 0053h

12 12 005Bh

13 13 0063h

14 14 USB UEPINT + USBINT 006Bh

Polling Priority

Interrupt

Source

Interrupt

Request

Vector

Address

15 15 0073h

7683C–USB–11/07

AT83C5134/35/36

17. Keyboard Interface

P1.0

Keyboard Interface Interrupt Request

KBD

IE1.0

Input Circuitry

P1.1 Input Circuitry

P1.2 Input Circuitry

P1.3 Input Circuitry

P1.4 Input Circuitry

P1.5 Input Circuitry

P1.6 Input Circuitry

P1.7 Input Circuitry

KBDIT

P1:x

KBE.x

KBF.x

KBLS.x

Vcc

Internal Pull-up

17.1 Introduction

The AT83C5134/35/36 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes.

17.2 Description

The keyboard interface communicates with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 17-3), KBE, The Keyboard interrupt Enable register (Table 17-2), and KBF, the Keyboard Flag register (Table 17-1).

17.2.1 Interrupt

The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 17-1). As detailed in Figure 17-2 each keyboard input has the capability to detect a programmable level according to KBLS.x bit value. Level detection is then reported in interrupt flags KBF.x that can be masked by software using KBE.x bits.

This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1 inputs for other purpose.

Figure 17-1. Keyboard Interface Block Diagram

Figure 17-2. Keyboard Input Circuitry

7683C–USB–11/07

17.2.2 Power Reduction Mode

P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”.

17.3 Registers

Table 17-1. KBF Register KBF - Keyboard Flag Register (9Eh)

7 6 5 4 3 2 1 0

KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0

AT83C5134/35/36

Bit Number

7 KBF7

6 KBF6

5 KBF5

4 KBF4

3 KBF3

2 KBF2

Bit

Mnemonic Description

Keyboard line 7 flag

Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Keyboard line 6 flag

Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.6 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Keyboard line 5 flag

Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.5 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Keyboard line 4 flag

Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.4 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Keyboard line 3 flag

Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.3 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Keyboard line 2 flag

Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.2 bit in KBIE register is set. Must be cleared by software.

7683C–USB–11/07

Keyboard line 1 flag

1 KBF1

0 KBF0

Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.1 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Keyboard line 0 flag

Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software.

Reset Value = 0000 0000b

AT83C5134/35/36

Table 17-2. KBE Register KBE - Keyboard Input Enable Register (9Dh)

7 6 5 4 3 2 1 0

KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0

Bit

Number

7 KBE7

6 KBE6

5 KBE5

4 KBE4

3 KBE3

2 KBE2

1 KBE1

Bit

Mnemonic Description

Keyboard line 7 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request.

Keyboard line 6 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request.

Keyboard line 5 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.5 bit in KBF register to generate an interrupt request.

Keyboard line 4 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.4 bit in KBF register to generate an interrupt request.

Keyboard line 3 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.3 bit in KBF register to generate an interrupt request.

Keyboard line 2 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.2 bit in KBF register to generate an interrupt request.

Keyboard line 1 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.1 bit in KBF register to generate an interrupt request.

0 KBE0

Keyboard line 0 Enable bit

Cleared to enable standard I/O pin. Set to enable KBF.0 bit in KBF register to generate an interrupt request.

Reset Value = 0000 0000b

7683C–USB–11/07

AT83C5134/35/36

Table 17-3. KBLS Register KBLS-Keyboard Level Selector Register (9Ch)

7 6 5 4 3 2 1 0

KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0

Bit Number

7 KBLS7

6 KBLS6

5 KBLS5

4 KBLS4

3 KBLS3

2 KBLS2

1 KBLS1

Bit

Mnemonic Description

Keyboard line 7 Level Selection bit

Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7.

Keyboard line 6 Level Selection bit

Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6.

Keyboard line 5 Level Selection bit

Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5.

Keyboard line 4 Level Selection bit

Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4.

Keyboard line 3 Level Selection bit

Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3.

Keyboard line 2 Level Selection bit

Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2.

Keyboard line 1 Level Selection bit

Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1.

0 KBLS0

Keyboard line 0 Level Selection bit

Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0.

Reset Value = 0000 0000b

7683C–USB–11/07

AT83C5134/35/36

18. Programmable LED

AT83C5134/35/36 have up to 4 programmable LED current sources, configured by the register LEDCON.

Table 18-1. LEDCON Register LEDCON (S:F1h) LED Control Register

7 6 5 4 3 2 1 0

LED3 LED2 LED1 LED0

Bit Number

7:6 LED3

5:4 LED2

3:2 LED1

1:0 LED0

Bit Mnemonic Description

Reset Value = 00h

Port LED3 Configuration

0 0 Standard C51 Port 0 1 2 mA current source when P3.7 is low 1 0 4 mA current source when P3.7 is low 1 1 10 mA current source when P3.7 is low

Port /LED2 Configuration

0 0 Standard C51 Port 0 1 2 mA current source when P3.6 is low 1 0 4 mA current source when P3.6 is low 1 1 10 mA current source when P3.6 is low

Port/ LED1 Configuration

0 0 Standard C51 Port 0 1 2 mA current source when P3.5 is low 1 0 4 mA current source when P3.5 is low 1 1 10 mA current source when P3.5 is low

Port/ LED0 Configuration

0 0 Standard C51 Port 0 1 2 mA current source when P3.3 is low 1 0 4 mA current source when P3.3 is low 1 1 10 mA current source when P3.3 is low

7683C–USB–11/07

19. Serial Peripheral Interface (SPI)

Slave 1

MISO

MOSI

SCK

MISO MOSI SCK SS

PORT

0 1 2 3

Slave 3

MISO

MOSI

SCK

Slave 4

MISO

MOSI

SCK

Slave 2

MISO

MOSI

SCK

VDD

Master

The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.

19.1 Features

Features of the SPI module include the following:

• Full-duplex, three-wire synchronous transfers

• Master or Slave operation

• Eight programmable Master clock rates

• Serial clock with programmable polarity and phase

• Master mode fault error flag with MCU interrupt capability

• Write collision flag protection

19.2 Signal Description

Figure 19-1 shows a typical SPI bus configuration using one Master controller and many Slave

peripherals. The bus is made of three wires connecting all the devices:

AT83C5134/35/36

Figure 19-1. SPI Master/Slaves Interconnection

The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices.

19.2.1 Master Output Slave Input (MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

19.2.2 Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

7683C–USB–11/07

AT83C5134/35/36

19.2.3 SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines.

19.2.4 Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port pins (Figure 19-1). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Statu s registe r (SPSTA) to pre vent mult iple masters f rom driving MOSI and SCK (s ee Section “Error Conditions”, page 79).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of

configuration can be found when only one Master is driving the network and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be

(1)

set

• The Device is configured as a Slave with CPHA and SSDIS control bits set

configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device.

Notes: 1. Clearing SSDIS control bit does not clear MODF.

(2)

This kind of

2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this mode, the SS is used to start the transmission.

19.2.5 Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128.

Table 19-1 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 19-1. SPI Master Baud Rate Selection

SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)

0 0 0 Don’t Use No BRG

0 0 1 F

0 1 0 F

0 1 1 F

1 0 0 F

1 0 1 F

1 1 0 F

1 1 1 Don’t Use No BRG

CLK PERIPH

/4 4

/8 8

/16 16

/32 32

/64 64

/128 128

7683C–USB–11/07

19.3 Functional Description

Shift Register

234567

Internal Bus

Pin Control Logic

MISO

MOSI

SCK

Clock Logic

Clock Divider

Clock Select

/64

/128

SPI Interrupt Request

8-bit bus

1-bit signal

FCLK PERIPH

/32

/16

Receive Data Register

SPDAT

SPI Control

SPSTA

CPHA

SPR0

SPR1

CPOLMSTRSSDISSPEN

SPR2

SPCON

WCOL MODFSPIF

- - - -

SSERR

Figure 19-2 shows a detailed structure of the SPI module.

Figure 19-2. SPI Module Block Diagram

AT83C5134/35/36

19.3.1 Operating Modes

7683C–USB–11/07

The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI module is made through one register:

• The Serial Peripheral CONtrol register (SPCON)

Once the SPI is configured, the data exchange is made using:

• SPCON

• The Serial Peripheral STAtus register (SPSTA)

• The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 19-3).

AT83C5134/35/36

19.3.1.1 Master Mode

8-bit Shift Register

SPI

Clock Generator

Master MCU

8-bit Shift Register

MISOMISO

MOSI

SCK SCK

VSS

VDD

SSSS

Slave MCU

Figure 19-3. Full-duplex Master/Slave Interconnection

The SPI operates in Master mode when the Master bit, MSTR

(1)

, in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT.

19.3.1.2 Slave Mode

The SPI operates in Slave mode when the Master bit, MSTR cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to’0’. SS must remain low until the transmission is complete.

In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module. After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte enters the shift register complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.

19.3.2 Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock POLarity (CPOL the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.

(2)

, in the SPCON register is

(3)

. A Slave SPI must

(4)

) and the Clock PHAse (CPHA4). CPOL defines

1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Mas-

ter SPI should be configured before the Slave SPI.

2. The SPI module should be configured as a Slave before it is enabled (SPEN set).

3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.

4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).

7683C–USB–11/07

Figure 19-4. Data Transmission Format (CPHA = 0)

MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB

bit6 bit5 bit4 bit3 bit2 bit1MSB LSB

1 32 4 5 6 7 8

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB

bit6 bit5 bit4 bit3 bit2 bit1

MSB LSB

1 32 4 5 6 7 8

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

Byte 1 Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

Figure 19-5. Data Transmission Format (CPHA = 1)

AT83C5134/35/36

Figure 19-6. CPHA/SS Timing

As shown in Figure 19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 19-2).

Figure 19-6 shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv-

ing its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 19-1). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line.

19.3.3 Error Conditions

7683C–USB–11/07

The following flags in the SPSTA signal SPI error conditions:

AT83C5134/35/36

19.3.3.1 Mode Fault (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control. In this case, the SPI system is affected in the following ways:

• An SPI receiver/error CPU interrupt request is generated,

• The SPEN bit in SPCON is cleared. This disable the SPI,

• The MSTR bit in SPCON is cleared

When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes “0”.

However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master attempt to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.

19.3.3.2 Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT.

19.3.3.3 Overrun Condition

An overrun condition occurs when the Master device tries to send several data bytes and the Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost.

This condition is not detected by the SPI peripheral.

19.3.4 Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Table 19-2. SPI Interrupts

Flag Request

SPIF (SP Data Transfer) SPI Transmitter Interrupt request

MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = “0”)

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests.

7683C–USB–11/07

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent

SSDIS

MODF

CPU Interrupt Request

SPI Receiver/Error

CPU Interrupt Request

SPI Transmitter

SPI

CPU Interrupt Request

SPIF

with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests.

Figure 19-7 gives a logical view of the above statements.

Figure 19-7. SPI Interrupt Requests Generation

19.3.5 Registers

There are three registers in the module that provide control, status and data storage functions. These registers are

describes in the following paragraphs.

19.3.5.1 Serial Peripheral Control Register (SPCON)

• The Serial Peripheral Control Register does the following:

– Selects one of the Master clock rates

– Configure the SPI module as Master or Slave

– Selects serial clock polarity and phase

– Enables the SPI module

– Frees the SS pin for a general-purpose

Table 19-3 describes this register and explains the use of each bit.

AT83C5134/35/36

Table 19-3. SPCON Register

7 6 5 4 3 2 1 0

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

Bit

Number Bit Mnemonic Description

7 SPR2

6 SPEN

5 SSDIS

5 MSTR

4 CPOL

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate.

Serial Peripheral Enable

Cleared to disable the SPI interface.

Set to enable the SPI interface.

SS Disable

Cleared to enable SS in both Master and Slave modes.

Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA = “0”.

Serial Peripheral Master

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

Clock Polarity

Cleared to have the SCK set to “0” in idle state.

Set to have the SCK set to “1” in idle state.

7683C–USB–11/07

AT83C5134/35/36

Bit

Number Bit Mnemonic Description

Clock Phase

3 CPHA

2 SPR1

1 SPR0

Cleared to have the data sampled when the SCK leaves the idle state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see CPOL).

SPR2 SPR1 SPR0 Serial Peripheral Rate

0 0 0 Reserved

0 0 1 F

0 1 0 F

0 1 1 F

1 0 0 F

1 0 1 F

1 1 0 F

1 1 1 Reserved

Reset Value = 0001 0100b

Not bit addressable

19.3.5.2 Serial Peripheral Status Register (SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

• Data transfer complete

• Write collision

• Inconsistent logic level on SS pin (mode fault error)

Table 19-4 describes the SPSTA register and explains the use of every bit in the register.

CLK PERIPH/

128

Table 19-4. SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

Table 3.

7 6 5 4 3 2 1 0

SPIF WCOL SSERR MODF - - - -

Bit Number

7 SPIF

6 WCOL

5 SSERR

Bit

Mnemonic Description

Serial Peripheral data transfer flag

Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence.

Set by hardware to indicate that a collision has been detected.

Synchronous Serial Slave Error flag

Set by hardware when SS is de-

asserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

7683C–USB–11/07

Bit Number

4 MODF

AT83C5134/35/36

Bit

Mnemonic Description

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence.

Set by hardware to indicate that the SS pin is at inappropriate logic level.

3 -

2 -

1 -

0 -

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = 00X0 XXXXb Not Bit addressable

19.3.5.3 Serial Peripheral Data Register (SPDAT)

The Serial Peripheral Data Register (Table 19-5) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register.

Table 19-5. SPDAT Register SPDAT - Serial Peripheral Data Register (0C5H)

7683C–USB–11/07

7 6 5 4 3 2 1 0

R7 R6 R5 R4 R3 R2 R1 R0

Reset Value = Indeterminate

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no ongoing exchange. However, special care should be taken when writing to them while a transmission is on-going:

• Do not change SPR2, SPR1 and SPR0

• Do not change CPHA and CPOL

• Do not change MSTR

• Clearing SPEN would immediately disable the peripheral

• Writing to the SPDAT will cause an overflow

AT83C5134/35/36

20. Two Wire Interface (

SCL

SDA

device2device1 deviceNdevice3

...

This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 100 Kbit/s in standard mode. Various communication configuration can be designed using this bus. Figure

20-1 shows a typical 2-wire bus configuration. All the devices connected to the bus can be mas-

ter and slave.

Figure 20-1. 2-wire Bus Configuration

TWI

)

7683C–USB–11/07

Figure 20-2. Block Diagram

Address Register

Comparator

Timing & Control logic

Arbitration & Sink Logic

Serial clock generator

Shift Register

Control Register

Status Register

Status Decoder

Input Filter

Output Stage

Input Filter

Output Stage

ACK

Status Bits

Internal Bus

Timer 1 overflow

CLK PERIPH

Interrupt

SDA

SCL

SSADR

SSCON

SSDAT

SSCS

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

20.1 Description

SDA

SCL

start

condition

MSB

1 2

8 9

ACK

acknowledgement

signal from receiver

acknowledgement

signal from receiver

1 2 3-8 9

ACK

stop

condition

clock line held low

while interrupts are serviced

The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; Table 20-10), the Synchronous Serial Data register (SSDAT; Table 20-11), the Synchronous Serial Control and Status register (SSCS; Table 20-

12) and the Synchronous Serial Address register (SSADR Table 20-13).

SSCON is used to enable the TWI interface, to program the bit rate (see Table 20-3), to enable slave modes, to acknowledge or not a received data, to send a START or a STOP condition on the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI module.

SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus. The three least significant bits are always zero. The five most significant bits contains the status code. There are 26 possible status codes. When SSCS contains F8h, no relevant state information is available and no serial interrupt is requested. A valid status code is available in SSCS one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. to Table 20-9. give the status for the master modes and miscellaneous states.

SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always contains the last byte present on the bus.

SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI module will respond when programmed as a slave transmitter or receiver. The LSB is used to enable general call address (00h) recognition.

Figure 20-3 shows how a data transfer is accomplished on the 2-wire bus.

Figure 20-3. Complete Data Transfer on 2-wire Bus

The four operating modes are:

• Master Transmitter

• Master Receiver

• Slave transmitter

• Slave receiver

Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to Figure 20-7.. These figures contain the following abbreviations:

S : START condition

7683C–USB–11/07

R : Read bit (high level at SDA)

W : Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P : STOP condition

In Figure 20-4 to Figure 20-7, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSCS. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software.

When the serial interrupt routine is entered, the status code in SSCS is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table to Table 20-9.

20.1.1 Master Transmitter Mode

In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (Figure 20-4). Before the master transmitter mode can be entered, SSCON must be initialised as follows:

AT83C5134/35/36

Table 20-1. SSCON Initialization

CR2 SSIE STA STO SI AA CR1 CR0

bit rate 1 0 0 0 X bit rate bit rate

CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used. SSIE must be set to enable TWI. STA, STO and SI must be cleared.

The master transmitter mode may now be entered by setting the STA bit. The 2-wire logic will now test the 2-wire bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON) is set, and the status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that loads SSDAT with the slave address and the data direction bit (SLA+W).

When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, SI is set again and a number of status code in SSCS are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted.

SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master receiver mode by loading SSDAT with SLA+R.

20.1.2 Master Receiver Mode

In the master receiver mode, a number of data bytes are received from a slave transmitter (Figure 20-5). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave

7683C–USB–11/07

AT83C5134/35/36

address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared before the serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted.

20.1.3 Slave Receiver Mode

In the slave receiver mode, a number of data bytes are received from a master transmitter (Figure 20-6). To initiate the slave receiver mode, SSADR and SSCON must be loaded as follows:

Table 20-2. SSADR: Slave Receiver Mode Initialization

A6 A5 A4 A3 A2 A1 A0 GC

own slave address

The upper 7 bits are the address to which the TWI module will respond when addressed by a master. If the LSB (GC) is set the TWI module will respond to the general call address (00h); otherwise it ignores the general call address.

Table 20-3. SSCON: Slave Receiver Mode Initialization

CR2 SSIE STA STO SI AA CR1 CR0

bit rate 1 0 0 0 1 bit rate bit rate

CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the TWI. The AA bit must be set to enable the own slave address or the general call address acknowledgement. STA, STO and SI must be cleared.

When SSADR and SSCON have been initialised, the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 0 (W) for the TWI to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine.The appropriate action to be taken for each of these status code is detailed in Table . The slave receiver mode may also be entered if arbitration is lost while TWI is in the master mode (states 68h and 78h).

If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the module from the 2-wire bus.

7683C–USB–11/07

20.1.4 Slave Transmitter Mode

In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine. The appropriate action to be taken for each of these status code is detailed in Table . The slave transmitter mode may also be entered if arbitration is lost while the TWI module is in the master mode.

If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the transfer and enter state C0h or C8h. the TWI module is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1’s as serial data. While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the TWI module from the 2-wire bus.

20.1.5 Miscellaneous States

There are two SSCS codes that do not correspond to a define TWI hardware state (Table 20-9 ). These codes are discuss hereafter.

AT83C5134/35/36

Status F8h indicates that no relevant information is available because the serial interrupt flag is not set yet. This occurs between other states and when the TWI module is not involved in a serial transfer.

Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus error is caused when a START or a STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions happen during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This causes the TWI module to enter the not addressed slave mode and to clear the STO flag (no other bits in SSCON are affected). The SDA and SCL lines are released and no STOP condition is transmitted.

20.2 Notes

the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock line) and SDA (serial data line). To avoid low level asserting on these lines when the TWI module is enabled, the output latches of SDA and SLC must be set to logic 1.

Table 20-4. Bit Frequency Configuration

Bit Frequency ( kHz)

CR2 CR1 CR0 F

0 0 0 47 62.5 256

= 12 MHz F

OSCA

= 16 MHz F

OSCA

divided by

OSCA

0 0 1 53.5 71.5 224

0 1 0 62.5 83 192

0 1 1 75 100 160

7683C–USB–11/07

AT83C5134/35/36

Bit Frequency ( kHz)

S SLA W A Data A P

08h 18h

28h

S SLA W

A P

10h

20h

30h

A or A

continues

38h38h

continues

68h

Other master

78h B0h

To corresponding states in slave mode

Successfull transmission to a slave receiver

Next transfer started with a repeated start condition

Not acknowledge received after the slave address

Not acknowledge received after a data

Arbitration lost in slave address or data byte

Arbitration lost and addressed as slave

byte

A or A

continues

Other master

Data A

From master to slave

From slave to master

Any number of data bytes and their associated acknowledge bits

This number (contained in SSCS) corresponds to a defined state of the 2-wire bus

CR2 CR1 CR0 F

1 0 0 - - Unused

1 0 1 100 133.3 120

1 1 0 200 266.6 60

1 1 1 0.5 <. < 62.5 0.67 <. < 83

= 12 MHz F

OSCA

= 16 MHz F

OSCA

Timer 1 in mode 2 can be used as TWI baudrate

generator with the following formula:

96.(256-”Timer1 reload value”)

Figure 20-4. Format and State in the Master Transmitter Mode

divided by

OSCA

7683C–USB–11/07

Table 20-5. Status in Master Transmitter Mode

Application software response

Status

Code

SSSTA

Status of the Twowire Bus and Twowire Hardware

A START condition has

08h

been transmitted

SSSTA SSSTO SSI SSAA

Write SLA+W X 0 0 X SLA+W will be transmitted.

AT83C5134/35/36

To SSCON

Next Action Taken by Two-wire HardwareTo/From SSDAT

A repeated START

10h

condition has been transmitted

SLA+W has been

18h

transmitted; ACK has been received

SLA+W has been

20h

transmitted; NOT ACK has been received

Data byte has been

28h

transmitted; ACK has been received

Data byte has been

30h

transmitted; NOT ACK has been received

Write SLA+W

Write SLA+R

Write data byte

No SSDAT action

Write data byte

No SSDAT action

Write data byte

No SSDAT action

Write data byte

No SSDAT action

SLA+W will be transmitted.

SLA+R will be transmitted.

Logic will switch to master receiver mode

Data byte will be transmitted.

Repeated START will be transmitted.

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

Data byte will be transmitted.

Repeated START will be transmitted.

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

Data byte will be transmitted.

Repeated START will be transmitted.

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

Data byte will be transmitted.

Repeated START will be transmitted.

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

Arbitration lost in

38h

SLA+W or data bytes

7683C–USB–11/07

No SSDAT action

Two-wire bus will be released and not addressed

slave mode will be entered.

A START condition will be transmitted when the bus

becomes free.

AT83C5134/35/36

Figure 20-5. Format and State in the Master Receiver Mode

S SLA R A

Data

08h

40h

58h

S SLA R

A P

10h

48h

A or A

continues

38h38h

continues

68h

Other master

78h B0h

To corresponding

states in slave mode

Successfull transmission to a slave receiver

Next transfer started with a repeated start condition

Not acknowledge received after the slave address

Arbitration lost and addressed as slave

continues

Other master

From master to slave

From slave to master

Any number of data bytes and their associated acknowledge bits

This number (contained in SSCS) corresponds to a defined state of the 2-wire bus

Data

50h

Arbitration lost in slave address or acknowledge bit

Data A

7683C–USB–11/07

Table 20-6. Status in Master Receiver Mode

Application software response

Status

Code

SSSTA

Status of the Twowire Bus and Twowire Hardware

A START condition has

08h

been transmitted

Write SLA+R X 0 0 X SLA+R will be transmitted.

To SSCON

SSSTA SSSTO SSI SSAA

AT83C5134/35/36

Next Action Taken by Two-wire HardwareTo/From SSDAT

A repeated START

10h

condition has been transmitted

Arbitration lost in

38h

SLA+R or NOT ACK bit

SLA+R has been

40h

transmitted; ACK has been received

SLA+R has been

48h

transmitted; NOT ACK has been received

Data byte has been

50h

received; ACK has been returned

Data byte has been

58h

received; NOT ACK has been returned

Write SLA+R

Write SLA+W

No SSDAT action

Read data byte

SLA+R will be transmitted.

SLA+W will be transmitted.

Logic will switch to master transmitter mode.

Two-wire bus will be released and not addressed

slave mode will be entered.

A START condition will be transmitted when the bus

becomes free.

01Data byte will be received and NOT ACK will be

returned.

Data byte will be received and ACK will be returned.

Repeated START will be transmitted.

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

01Data byte will be received and NOT ACK will be

returned.

Data byte will be received and ACK will be returned.

Repeated START will be transmitted.

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

7683C–USB–11/07

AT83C5134/35/36

Figure 20-6. Format and State in the Slave Receiver Mode

S SLA W A

Data A

Data

P or S

General Call A

Data A

Data

P or S

60h

68h

80h

A0h

88h

70h 90h

90h

A0h

P or S

98h

78h

Data A

From master to slave

From slave to master

Any number of data bytes and their associated acknowledge bits

This number (contained in SSCS) corresponds to a defined state of the 2-wire bus

Reception of the own slave address and one or more data bytes. All are acknowledged.

Last data byte received is not acknowledged.

Arbitration lost as master and addressed as slave

Reception of the general call address and one or more data bytes.

Last data byte received is not acknowledged.

Arbitration lost as master and addressed as slave by general call

7683C–USB–11/07

Table 20-7. Status in Slave Receiver Mode

AT83C5134/35/36

Application Software Response

Status

Code

(SSCS)

60h

68h

70h

78h

80h

Status of the 2-wire bus and

2-wire hardware

Own SLA+W has been

received; ACK has been

returned

Arbitration lost in SLA+R/W as master; own SLA+W has been

received; ACK has been

returned

General call address has been

received; ACK has been

returned

Arbitration lost in SLA+R/W as

master; general call address

has been received; ACK has

been returned

Previously addressed with own

SLA+W; data has been

received; ACK has been

returned

To/from SSDAT To SSCON

STA STO SI AA

No SSDAT action or

No SSDAT action

No SSDAT action or

No SSDAT action

No SSDAT action or

No SSDAT action

No SSDAT action or

No SSDAT action

No SSDAT action or

No SSDAT action

000

Next Action Taken By 2-wire Software

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be

returned

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be

returned

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be

returned

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be

returned

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be

returned

88h

90h

Previously addressed with own

SLA+W; data has been

received; NOT ACK has been

returned

Previously addressed with

general call; data has been

received; ACK has been

returned

Read data byte or

Read data byte

Read data byte or

Read data byte

Switched to the not addressed slave mode; no

000

recognition of own SLA or GCA

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1

Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START

condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted when the bus becomes free

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be

returned

7683C–USB–11/07

AT83C5134/35/36

Table 20-7. Status in Slave Receiver Mode (Continued)

Application Software Response

Status

Code

(SSCS)

98h

A0h

Status of the 2-wire bus and

2-wire hardware

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

A STOP condition or repeated

START condition has been

received while still addressed

as slave

To/from SSDAT To SSCON

STA STO SI AA

Read data byte or

Read data byte

No SSDAT action or

No SSDAT action

Next Action Taken By 2-wire Software

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1

Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START

condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; no recognition of own SLA or GCA

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1

Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START

condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted when the bus becomes free

7683C–USB–11/07

Figure 20-7. Format and State in the Slave Transmitter Mode

S SLA R

Data A

Data

P or S

A8h

B8h C0h

P or S

C8h

All 1’s

B0h

Data A

From master to slave

From slave to master

Any number of data bytes and their associated acknowledge bits

This number (contained in SSCS) corresponds to a defined state of the 2-wire bus

Reception of the own slave address and one or more data bytes

Arbitration lost as master and addressed as slave

Last data byte transmitted. Switched to not addressed slave (AA=0)

AT83C5134/35/36

Table 20-8. Status in Slave Transmitter Mode

Application Software Response

Status

Code

(SSCS)

A8h

B0h

B8h

Status of the 2-wire bus and

received; ACK has been

Arbitration lost in SLA+R/W as

master; own SLA+R has been

received; ACK has been

Data byte in SSDAT has been

transmitted; NOT ACK has

2-wire hardware

Own SLA+R has been

returned

been received

To/from SSDAT To SSCON

Load data byte or

Load data byte

Load data byte or

Load data byte

Load data byte or

Load data byte

STA STO SI AA

Next Action Taken By 2-wire Software

Last data byte will be transmitted and NOT ACK

will be received

Data byte will be transmitted and ACK will be

received

Last data byte will be transmitted and NOT ACK

will be received

Data byte will be transmitted and ACK will be

received

Last data byte will be transmitted and NOT ACK

will be received

Data byte will be transmitted and ACK will be

received

7683C–USB–11/07

AT83C5134/35/36

Table 20-8. Status in Slave Transmitter Mode (Continued)

Application Software Response

Status

Code

(SSCS)

C0h

C8h

Status of the 2-wire bus and

2-wire hardware

Data byte in SSDAT has been

transmitted; NOT ACK has

been received

Last data byte in SSDAT has

been transmitted (AA=0); ACK

has been received

To/from SSDAT To SSCON

STA STO SI AA

No SSDAT action or

No SSDAT action

No SSDAT action or

No SSDAT action

Next Action Taken By 2-wire Software

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1

Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START

condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; no recognition of own SLA or GCA

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1

Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START

condition will be transmitted when the bus becomes free

Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted when the bus becomes free

(SSCS)

Status

Code

F8h

00h

Table 20-9.

Status of the 2-wire bus and

2-wire hardware

No relevant state information

available; SI= 0

Bus error due to an illegal

START or STOP condition

Miscellaneous Status

Application Software Response

To/from SSDAT To SSCON

STA STO SI AA

No SSDAT action No SSCON action Wait or proceed current transfer

No SSDAT action 0 1 0 X

Next Action Taken By 2-wire Software

Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and STO is reset.

7683C–USB–11/07

20.3 Registers

AT83C5134/35/36

Table 20-10. SSCON Register

SSCON - Synchronous Serial Control Register (93h)

7 6 5 4 3 2 1 0

CR2 SSIE STA STO SI AA CR1 CR0

Bit Number

7 CR2

6 SSIE

5 STA

4 ST0

3 SI

2 AA

1 CR1

Bit

Mnemonic Description

Control Rate bit 2

See .

Synchronous Serial Interface Enable bit

Clear to disable SSLC. Set to enable SSLC.

Start flag

Set to send a START condition on the bus.

Stop flag

Set to send a STOP condition on the bus.

Synchronous Serial Interrupt flag

Set by hardware when a serial interrupt is requested. Must be cleared by software to acknowledge interrupt.

Assert Acknowledge flag

Clear in master and slave receiver modes, to force a not acknowledge (high level on SDA). Clear to disable SLA or GCA recognition. Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter modes. Set in master and slave receiver modes, to force an acknowledge (low level on SDA). This bit has no effect when in master transmitter mode.

Control Rate bit 1

See Table 20-4

7683C–USB–11/07

0 CR0

Control Rate bit 0

See Table 20-4

Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write)

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

7 6 5 4 3 2 1 0

Bit Number

7 SD7 Address bit 7 or Data bit 7.

6 SD6 Address bit 6 or Data bit 6.

5 SD5 Address bit 5 or Data bit 5.

4 SD4 Address bit 4 or Data bit 4.

3 SD3 Address bit 3 or Data bit 3.

2 SD2 Address bit 2 or Data bit 2.

Bit

Mnemonic Description

AT83C5134/35/36

Bit

Bit Number

1 SD1 Address bit 1 or Data bit 1.

0 SD0 Address bit 0 (R/W) or Data bit 0.

Mnemonic Description

Table 20-12. SSCS (094h) Read - Synchronous Serial Control and Status Register

7 6 5 4 3 2 1 0

SC4 SC3 SC2 SC1 SC0 0 0 0

Bit Number

0 0 Always zero

1 0 Always zero

2 0 Always zero

3 SC0

4 SC1

5 SC2

6 SC3

7 SC4

Bit

Mnemonic Description

Status Code bit 0

See Table 20-5 to Table 20-9

Status Code bit 1

See Table 20-5 to Table 20-9

Status Code bit 2

See Table 20-5 to Table 20-9

Status Code bit 3

See Table 20-5 to Table 20-9

Status Code bit 4

See Table 20-5 to Table 20-9

Table 20-13. SSADR (096h) - Synchronous Serial Address Register (read/write)

7 6 5 4 3 2 1 0

A7 A6 A5 A4 A3 A2 A1 A0

100

Bit Number

7 A7 Slave address bit 7.

6 A6 Slave address bit 6.

5 A5 Slave address bit 5.

4 A4 Slave address bit 4.

3 A3 Slave address bit 3.

2 A2 Slave address bit 2.

1 A1 Slave address bit 1.

0 GC

Bit

Mnemonic Description

General call bit

Clear to disable the general call address recognition. Set to enable the general call address recognition.

7683C–USB–11/07

ATMEL AT83C5136 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

3. Block Diagram

4. Pinout Description

4.1 Pinout

4.2 Signals

5. Typical Application

5.1 Recommended External components

5.2 PCB Recommandations

6. Clock Controller

6.1 Introduction

6.2 Oscillator

6.3 PLL

6.3.1 PLL Description

6.3.2 PLL Programming

6.3.3 Divider Values

6.4 Registers

7. SFR Mapping

8. Program/Code Memory

8.1 External Code Memory Access

8.1.1 Memory Interface

8.1.2 External Bus Cycles

9. AT89C5131 ROM

9.1 ROM Structure

9.1.1 Hardware Configuration Byte

9.2 ROM Lock System

9.2.1 Program ROM lock Bits

10. Stacked EEPROM

10.1 Overview

10.2 Protocol

11. On-chip Expanded RAM (ERAM)

12. Timer 2

12.1 Auto-reload Mode

12.2 Programmable Clock Output

13. Programmable Counter Array (PCA)

13.1 PCA Capture Mode

13.2 16-bit Software Timer/Compare Mode

13.3 High Speed Output Mode

13.4 Pulse Width Modulator Mode

13.5 PCA Watchdog Timer

14. Serial I/O Port

14.1 Framing Error Detection

14.2 Automatic Address Recognition

14.2.1 Given Address

14.2.2 Broadcast Address

14.2.3 Reset Addresses

14.3 Baud Rate Selection for UART for Mode 1 and 3

14.3.1 Baud Rate Selection Table for UART

14.3.2 Internal Baud Rate Generator (BRG)

14.4 UART Registers

15. Dual Data Pointer Register

16. Interrupt System

16.1 Overview

16.2 Registers

16.3 Interrupt Sources and Vector Addresses

17. Keyboard Interface

17.1 Introduction

17.2 Description

17.2.1 Interrupt

17.2.2 Power Reduction Mode

17.3 Registers

18. Programmable LED

19. Serial Peripheral Interface (SPI)

19.1 Features

19.2 Signal Description

19.2.1 Master Output Slave Input (MOSI)

19.2.2 Master Input Slave Output (MISO)

19.2.3 SPI Serial Clock (SCK)

19.2.4 Slave Select (SS)

19.2.5 Baud Rate

19.3 Functional Description

19.3.1 Operating Modes

19.3.1.1 Master Mode

19.3.1.2 Slave Mode

19.3.2 Transmission Formats

19.3.3 Error Conditions