ATMEL AT83C5111, AT87C5111 User Manual

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Features

• 80C51 Compatible

– Three I/O Ports – Two 16-bit Timer/Counters – 256 Bytes RAM

• 4K Bytes ROM/OTP Program Memory with 64 Bytes Encryption Array and 3 Security

Levels

• High-Speed Architecture

– 33 MHz at 5V (66 MHz Equivalent) – 20 MHz at 3V (40 MHz Equivalent) – X2 Speed Improvement Capability (6 Clocks/Machine Cycle)

• 10-bit, 8 Channels A/D Converter

• Hardware Watchdog Timer

• Programmable I/O Mode: Standard C51, Input Only, Push-pull, Open Drain

• Asynchronous Port Reset

• Full Duplex Enhanced UART with Baud Rate Generator

• SPI, Master Mode

• Dual System Clock

– Crystal or Ceramic Oscillator (33/40 MHz) – Internal RC Oscillator (12 MHz) – Programmable Prescaler

• Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width

Modulation and Watchdog Timer Capabilities

• Interrupt Structure

– 8 Interrupt Sources – 4 Interrupt Priority Levels

• Power Control Modes

– Idle Mode – Power-down Mode – Power-off Flag

• Power Supply: 2.7 - 5.5V

• Temperature Range: Industrial (-40 to 85

• Package: SO24, DIL24, SSOP24

Low Pin Count 8-bit Microcontroller with A/D Converter

AT83C5111 AT87C5111

Description

The AT8xC5111 is a high-performance ROM/OTP version of the 80C51 8-bit microcontroller in low pin count package.

The AT8xC5111 retains all the features of the standard 80C51 with 4K Bytes ROM/OTP program memory, 256 bytes of internal RAM, an 8-source, 4-level interrupt system, an on-chip oscillator and two timer/counters.

The AT8xC5111 is dedicated for analog interfacing applications. For this, it has a 10bit, 8 channels A/D converter and a five-channel Programmable Counter Array.

In addition, the AT8xC5111 has a Hard ware Watchdog Timer, a versatile serial chan nel that facili tates mu ltiproc ess or com munic ation (E UART) with an i ndepen dent baud rate generator, an SPI serial bus controller an d a X2 spe ed im prov eme nt mechanism. The X2 feature permits keeping the same CPU power at an oscillator frequency divided by two. The prescaler allows to decrease CPU and peripherals clock frequency.

The fully static design of the AT8xC5111 can reduce system powe r consumption b y bringing the clock frequency down to any value, even DC, without loss of data.

The AT8xC5111 has 3 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode, the CPU is frozen while the peripherals are still operating. In the quiet mode, only the A/D converter is operating.

Rev. 4190A–8051–11/0 2

Block Diagram

(2)

XTAL1

(2)

XTAL2

Xtal Osc

Osc

In the power-down mode, the RAM is saved and all other functions are inoperative. Two oscillator sources, crystal and RC, provide a versatile power management.

The AT8xC5111 is proposed in low-pin count packages. Port 0 and Port 2 (address/data buses) are not available .

MISO

MOSI

SPSCK

(3)

SPI

(3)

Watch

Dog

CPU

RxD

(2)(2)

EUART

BRG

TxD

C51

CORE

RAM

256

IB-bus

Vss

Vcc

ROM /OTP

4K *8

(1)

ECI

(1)

PCA

CEX0-4

(3)

(2)

Notes: 1. Alternate function of Port 1.

2. Alternate function of Port 3.

3. Alternate function of Port 4.

Timer 0 Timer 1

(2) (3) (2) (3)

RST/V

INT Ctrl

INT0

A/D

Converter

(3)

INT1

REF

AIN0-7

Parallel I/O Ports

Port 3

Port 1

Port 4

AT8xC5111

4190A–8051–11/02

AT8xC5111

SFR Mapping The Special Function Registers (SFRs) of the AT8xC5111 belong to the following

categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

• I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2

• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON

• Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON,

CKRL

• Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1

• Watchdog Timer: WDTRST, WDTPRG

• SPI: SPCON, SPSTA, SPDAT

• PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H,

CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON

• ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF

4190A–8051–11/02

Table 1. SF R Addres se s and Res et Val ues

0/8 1/9 72/A 3/B 4/C 5/D 6/E 7/F

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

0000 0000

ACC

0000 0000

CCON

00X0 0000

PSW

0000 0000

1111 1111

IPL0

0000 0000

1111 1111

IE0

0000 0000

CMOD

X000 0000

SADEN

0000 0000

IE1

0000 0000

SADDR

0000 0000

CCAP0H

XXXX XXXX

ADCLK

0000 0000

CCAP0L

XXXX XXXX

P1M2

0000 0000

CCAPM0

00XX X000

IPL1

0000 0000

CCAP1H

XXXX XXXX

ADCON

0000 0000

CCAP1L

XXXX XXXX

CCAPM1

X000 0000

SPCON

0001 0100

IPH1

0000 0000

CCAP2H

XXXX XXXX

ADDL

XXXXXX00

CCAP2L

XXXX XXXX

P3M2

0000 0000

CCAPM2

X000 0000

P1M1

0000 0000

SPSTA

XXXXXXXX

CCAP3H

XXXX XXXX

ADDH

0000 0000

CCAP3L

XXXX XXXX

P4M2

0000 0000

CCAPM3

X000 0000

P3M1

0000 0000

SPDAT

XXXX XXXX

CCAP4H

XXXX XXXX

ADCF

0000 0000

CCAP4L

XXXX XXXX

CCAPM4

X000 0000

P4M1

0000 0000

CONF

IPH0

X000 0000

CKCON1

XXXX XXX0

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A0h

98h

90h

88h

80h

0000 0000

Reserved

AUXR1

XXXXXXX0

SCON

1111 1111

TCON

0/8 1/9 2/A 3/B 4/C 5/ D 6/E 7/F

SBUF

XXXX XXXX

TMOD

0000 0000

0000 0111

BRL

0000 0000

TL0

0000 0000

DPL

0000 0000

BDRCON

0000 0000

TL1

0000 0000

DPH

0000 0000

TH0

0000 0000

TH1

0000 0000

CKSEL

XXXX XXX1

WDRST

0000 0000

OSCCON

XXXX XX01

WDTPRG

0000 0000

CKRL

1111 1111

CKCON0

X000X000

PCON

00X1 0000

A7h

9Fh

97h

8Fh

87h

AT8xC5111

4190A–8051–11/02

Pin Configuration

AT8xC5111

P4.4/MISO/AIN4 P4.5/MOSI/AIN5

P4.6/SPSCK/AIN6

P4.7/AIN7

RST

P1.7/CEX4

P1.6/CEX3

VREF

VSS

VCC

/VPP XTAL2 XTAL1

6 7

SO24 DIL24

Pin Descriptions

Mnemoni c Type Name and Fun c t i on

VREF I VREF: A/D converter positive reference input

/VPP

RST

I Ground: 0V reference I Power Supply: This is the power supply voltage for normal, idle and power-down operation.

RST/VPP: Reset/Programming Supply Voltage: A low on this pin for two machine cycles while the oscillator is running, resets the device. This pin

has no pull-up. In order to use the internal power-on reset, an external pull-up resistor must be connected.

This pin also rec eives the 12 V programm ing pulse w hich will start th e EPROM pro gramming and the manufacturer test modes.

P4.2/SS/AIN2

P4.1/AIN1/T1 P4.0/AIN0

P3.0/RxD

P3.1/TxD

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P3.2/INT0

P3.3/T0

P4.3/INT1/AIN3

P4.4/MISO/AIN4 P4.5/MOSI/AIN5

P4.6/SPSCK/AIN6

VREF

VSS

AVSS

AVCC

VCC

RST

/VPP XTAL2 XTAL1

P1.6/CEX3

3 4

SSOP24

6 7

8 9 10 11

P4.2/SS/AIN2

22 21

P3.0/RxD

20 19 18

16 15 14

P4.3/INT1/AIN3

P4.1/AIN1/T1 P4.0/AIN0

P3.1/TxD P1.2/ECI P1.3/CEX0 P1.4/CEX1

P1.5/CEX2

P3.2/INT0

P3.3/T0

XTAL1 I XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits XTAL2 O XTAL2 : Output from the inverting oscillator amplifier

P1.2 - P1.7

I/O

Port 1: Port 1 is an 6-bit programmable I/O port . See Section “Ports”, page 18 for a description of I/O ports.

Alternate functions for Port 1 include: I/O ECI (P1.2): External Clock for the PCA I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

P3.0 - P3.3 I/O

Port 3: Port 3 is an 6-bit programmable I/O port with internal pull-ups. See Section "Ports", page 18

for a description of I/O ports.

Port 3 also serves the special features of the 80C51 family, as listed below. I/O RXD (P3.0): Serial input port

I/O TXD (P3.1): Serial output port

4190A–8051–11/02

Mnemoni c Type Name and Fun c t i on

I/O INT0 (P3.2): External interrupt 0 I/O T0 (P3.3): Timer 0 external input

P4.0 - P4.7

Port 4: Port 4 is an 8-bit programmable I/O port w i th in tern al p ull -up s . See Sec tio n "Po rt s" , p a ge18 I/O

I/O AIN0 (P4.0): A/D converter input 0

I/O

I/O AIN7 (P4.7): A/D converter input 7

for a description of I/O ports.

Port 4 is also the input port of the analog-to-digital converter.

AIN1 (P4.1): A/D converter input 1

T1: Timer 1 external input

AIN2 (P4.2): A/D converter input 2

: Slave select input of the SPI controllers

AIN3 (P4.3): A/D converter input 3

: External interrupt 1

INT1

AIN4 (P4.4): A/D converter input 4

MISO: Master IN, Slave OUT of the SPI controllers

AIN5 (P4.5): A/D converter input 5

MOSI: Master OUT, Slave IN of the SPI controllers

AIN6 (P4.6): A/D converter input 6

SPSCK: Clock I/O of the SPI controll ers

AT8xC5111

4190A–8051–11/02

AT8xC5111

Clock System The AT8xC5111 oscillator system provides a reliable clocking system with full mastering

of speed versus CPU power trade off. Several clock sources are possible:

• External clock input

• High-speed crystal or ceramic oscillator

• Integrated high-speed RC oscillator

The selected clock source can be divided by 2 - 512 before clocking the CPU and the peripherals. When X2 function is set, the CPU needs 6 clock periods per cycle.

Clocking is controlled by several SFR registers: OSCON, CKCON0, CKCON1, CKRL.

Blocks Description The AT8xC5111 includes the following oscillators:

• Crystal osci ll ator

• Integrated high-speed RC oscillator, with typical frequency of 12 MHz

Crystal Oscillator: OSCA The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output.

Both crystal and ceramic resonators can be use d. An oscillator source on XTAL1 is mandatory to start the product.

OSCAEN in OSCCON register is an enabl e signal for the crys tal oscill ator or the exte rnal oscillator input.

Integrated High-speed RC Oscillator: OSCB

Clock Selector CKS bit in CKS register is used to select from crystal to RC oscillator.

Clock Prescaler Before supplying the CPU and the per iph eral s, the mai n cloc k is div ided by a fac tor of 2

The high-speed RC osci ll ato r typ ical fre que nc y i s 12 MHz. Note that the on c hi p osci ll ator has a ±50% frequency to lerance and may not be sui table for use in some applications.

OSCBEN in OSCCON register is an enable signal for the high-speed RC oscillator.

OSCBEN bit in OSCCON register is used to enable the RC oscillator. OSCAEN bit in OSCCON registe r is used to enable the crys tal oscilla tor or the ex terna l

oscillator input.

to 512, as defined by the CKRL register . The CPU need s from 12 to 256*12 c lock periods per instruction. This allows:

• to accept any cyclic ratio to be accepted on XTAL1 input.

• to reduce the CPU power consumption.

The X2 bit allows to bypass the clock prescaler; in this case, the CPU needs only 6 clock periods per machine cycle. In X2 mode, as th is divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

4190A–8051–11/02

Functional Block Diagram

ResetB

Reload

: 128

Timer 0 Clock

Sub Clock

WD Clock

A/D Clock

CkAdc

Peripherals Clock

CkIdle

CPU Clock

Idle

Xtal1

Xtal2

OSCAEN

OSCBEN

Xtal_Osc OSCA

PwdOsc

RC_Osc OSCB

PwdRC

Mux

Filter

CKS

Ckrl

OscOut

8-bit

Prescaler-Divider

CkOut

Quiet

Pwd

Operating Modes

Functional Modes

Normal Modes • CPU and Peripheral clocks depend on the software selection using CKCON0,

CKCON1, CKSEL and CKRL registers.

• CKS bit selects either Xtal_Osc or RC_Osc.

• CKRL register determines the frequency of the selected clock, unless X2 bit is set.

In this case the prescaler/divider is not used, so CPU core needs only 6 clock periods per machine cycle. According to the value of the peripheral X2 individual bit, each peripheral needs 6 or 12 clock periods per instruction.

• It is always possible to switch dynamically by software from Xtal_Osc to RC_Osc, and vice versa by changing CKS bit, a synchronization cell allowing to avoid any spike during transition.

Idle Modes • IDLE modes are achieved by using any instruction that writes into PCON.0 sfr

• IDLE modes A and B depend on previous software sequence, prior to writing into

PCON.0 register:

– IDLE MODE A: Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1) – IDLE MODE B: RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)

• The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing

OSCAEN or OSCBEN, respectively.

• Exit from IDLE mode is achieved by Reset, or by activation of an enabled interrupt.

• In both cases, PCON.0 is cleared by hardware.

AT8xC5111

4190A–8051–11/02

AT8xC5111

• Exit from IDLE modes will leave the oscillator control bits OSCAEN, OSCBEN and CKS unchanged.

Power-down Modes • POWER-DOWN modes are achieved by using any instruction that writes into

PCON.1 sfr

• Exit from POWER-DOWN mode is achieved either by a hardware Reset, or by an external interruption.

• By RST signal: The CPU will restart on OSCA.

• By INT0 or INT1 interruptions, if enabled. The oscillators control bits OSCAEN,

OSCBEN and CKS will not be changed, so the selected oscillator before entering into Power-down will be activated.

Table 1. Power Modes

PD IDLE CKS OSCBEN OSCAEN S elected Mode Comment

0 0 1 X 1 NORMAL MODE A OSCA: XTAL clock X X 1 X 0 INVALID No active clock 0 0 0 1 X NORMAL MODE B OSCB: high-speed RC clock XX0 0 XINVALID

0 1 1 X 1 IDLE MODE A

0 1 0 1 X IDLE MODE B

1XX X X

TOTAL POWERDOWN

Prescaler Divi der • An hardware RESET selects the prescaler divider:

– CKRL = FFh: internal clock = OscOut/2 (Standard C51 feature) – X2 = 0,

• After Reset, any value between FFh down to 00h can be written by software into

CKRL sfr in order to divide frequency of the selected oscillator:

– CKRL = 00h: minimum frequency = OscOut/512 – CKRL = FFh: maximum frequency = OscOut/2

The frequency of the CPU and peripherals clock CkOut is related to the frequency of the main oscillator OscOut by the following formula:

CkOut

= F

/(512 - 2*CKRL)

OscOut

Some examples can be found in the table below:

OscOut

MHz X2 CKRL F

12 0 FF 6

The CPU is off, OSCA supplies the peripherics

The CPU is off, OSCB supplies the peripherics

The CPU is off, OSCA and OSCB are stopped

(Mhz)

CkOut

4190A–8051–11/02

12 0 FE 3 12 1 x 12

• A software instruction which sets X2 bit de-activates the prescaler/divider, so the internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit.

Timer 0: Clock Inputs

CkIdle

T0 pin

Sub Clock

Gate

INT0

TR0

: 6

SCLKT0

OSCCON

C/T

TMOD

Timer 0

Control

The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allows to perform a Real-Time Clock function.

SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode). SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input. When the subclock input is select ed for Time r 0 and the cr ystal os cillat or is sele ct ed for

CPU and peripherals , the CKRL pr escaler mu st be set to FF ( divisi on factor 2) in order to assure a proper count on Timer 0.

With an external a 32 kHz oscillator, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real-Time Clock (RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 kHz most of the time. When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others peripherals.

Registers

Clock Control Register The clock control register is used to define the clock system behavior.

Table 2. OSCCON - Clock Control Register (8Fh)

76543210

-----SCLKT0OSCBENOSCAEN

Bit

Number

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

AT8xC5111

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4190A–8051–11/02

AT8xC5111

Bit

Number

2SCLKT0

1OSCBEN

0OSCAEN

Bit

Mnemonic Description

Sub Clock Timer0

Cleared by software to select T0 pin Set by software to select T0 Sub Clock

Enable RC oscillator

This bit is used to enable the high-speed RC oscillator 0: The oscillator is disabled 1: The oscillator is enabled.

Enable crystal oscillator

This bit is used to enable the crystal oscillator 0: The oscillator is disabled 1: The oscillator is enabled.

Reset value = 0XXX X001b Not bit addressable

Clock Selection Register The clock selection register is used to define the clock system behavior

Table 3. CKSEL - Clock Selection Register (85h)

76543210

------CKS

Bit

Number

0CKS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Active oscillator selection

This bit is used to select the active oscillator. 1: The crystal oscillator is selected. 0: The high-speed RC oscillator is selected.

Reset value = XXXX XXX 1 b Not bit addressable

4190A–8051–11/02

Clock Prescaler Register This register is used to reload the clock prescaler of the CPU and peripheral clock.

Table 4. CKRL - Clock Prescaler Register (97h)

76543210

Bit

Number

7: 0 CKRL

Bit

Mnemonic Descripti on

0000 0000b: Division factor equal 512 1111 1111b: Division factor equal 2 M: Division factor equal 2*(256-M)

Reset value = 1111 1111b Not bit addressable

Clock Control Register This register is used to control the X2 mode of the CPU and peripheral clock.

Table 5. CKCON0 Register (8Fh)

76543210

- WdX2 PcaX2 SiX2 - T1X2 T0X2 X2

Bit

Number

7-Reserved

6WdX2

Bit

Mnemonic Description

Watchdog c lock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (This control bit is validated when the CPU

5PcaX2

4SiX2

3-Reserved

2T1X2

1T0X2

clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the

CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

AT8xC5111

4190A–8051–11/02

AT8xC5111

Bit

Number

0X2

Bit

Mnemonic Description

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.

Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.

Reset value = X000 0000b Not bit addressable

Table 6. CKCON1 Register (AFh)

7 6 5 43210

- - - ---BRGX2SPIX2

Bit

Number

7-Reserved 6-Reserved 5-Reserved 4-Reserved

Bit

Mnemonic Descripti on

3-Reserved 2-Reserved

BRG clock (This control bit is validated when the CPU clock X2 is set; when

1BRGX2

0 SPIX2

X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle. SPI clock (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reset value = XXXX XX00 b Not bit addressable

4190A–8051–11/02

AT8xC5111

Reset and Power Management

The power monitoring and management can be used to supervise the Power Supply (V

) and to start up properly when AT8xC5111 is powered up.

It consists of the features listed below and explained hereafter:

• Power-off flag

• Idle mode

• Power-down mode

• Reduced EMI mode

All these features are controlled by several registers, the Power Control register (PCON) and the Auxiliary register (AUXR) detailed at the end of this section.

AUX register not available on all versions.

Functional Description Figure 1 shows the block diagram of the possible sources of microcontroller reset.

Figure 1. Reset Sources

(1)

RST Pin

Hardware WD

RST Pin

Notes: 1. RST pin available only on 48 and 52 pins versions.

(2)

2. RST

PCA WD

pin available only on LPC versions.

Reset

Power-off Flag When the power is tur ned off or fails, the data retent ion is n ot guarant eed. A Pow er-off

Flag (POF, Table 8 on page 15) allows to det ect this conditi on. POF i s set by hard ware during a reset wh ich follo ws a power-u p or a powe r-fail. Thi s is a cold reset. A war m reset is an external or a watchdog reset without power failure, hence which preserves the internal memory content and POF. To use POF, test and cl ear this bit just after reset. Then it will be set only after a cold reset.

4190A–8051–11/02

Registers

PCON: Power Configuration Register

Table 1. PCON Register (87h)

76543210

SMOD1 SMOD0 – POF GF1 GF0 PD IDL

Bit

Number

7SMOD1

6SMOD0

5 –

4POF

3GF1

Bit

Mnemonic Description

Double Baud Rate bit

Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register.

SCON Select bit

When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit. When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register.

Reserved

Must be cleared.

Power-off flag

Set by hardware when V has been set off. Must be cleared by software.

General Purpose flag 1

One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.

rises above V

to indicate that the Power Supply

RET+

2GF0

1PD

0IDL

General Purpose flag 0

One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence.

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.

Reset value = 0000 0000b

Port Pins The value of port pins in the different operating modes is shown on Table 9.

Table 2. Pin Conditions in Special Operating Modes

Mode Program Memory Port 1 Pins Port 3 Pins Port 4 Pins

Reset Don’t care Weak High Weak High Weak High Idle Internal Data Data Data Power-down Internal Data Data Data

AT8xC5111

4190A–8051–11/02

AT8xC5111

Hardware Watchdog Timer (WDT)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is by defa ult disable d from exitin g reset. To e nable the WDT, the user must write 01EH and 0E1H in sequ ence to the WDTRS T, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle (6 internal clock periods) and there is no way to disable the WDT except throu gh reset (eit her hardw are reset or WD T ov erfl ow r es et). T he T0 bit of t he W DT PRG r egi ster is use d to se lec t th e overflow after 10 or 14 bits. When WDT overflows, it will generate an i nternal reset. It will also drive an output RESET HIG H pulse at the e mulator RS T-pin. T he lengt h of the reset pulse is 24 clock periods of the WD clock.

Using the WDT To enable the WDT, the user must write 01E H and 0E1H in sequen ce to the WDTR ST,

SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1 FFFH) and thi s will r es et the dev ice. W hen WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RS T pin. The RESET pu lse duration is 96 x T 1/F code that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2 capability, ranking fr om 16 ms to 2s at F ture, refer to WDTPRG register description, Table 11 (SFR0A7h).

. To make the best use of the W DT, it should b e servic ed in t hose se ctions of

OSC

counter has been added to extend the Time- out

= 12 MHz and T0 = 0. To manage this fea-

OSC

, where T

OSC

Table 1. WDT RS T Register WDTRST Address (0A6h)

765 4 3 2 1

Reset value X X X X X X X

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

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Table 2. WDT PR G Regi st er

WDTPRG Address (0A7h)

76543210

T4 T3 T2 T1 T0 S2 S1 S0

Bit

Number

7T4 6T3 5T2 4T1

3T0

2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0

Bit

Mnemonic Description

Reserved

Do not try to set this bit.

WDT overflow select bit 0: Overflow after 14 bits 1: Overflow after 10 bits

S1 S0 Selected Time-out with T0 = 0

000 (214 - 1) machine cycles, 16.3 ms at 12 MHz 001 (2 010 (2 011 (2 100 (2 101 (2 110 (2 111 (2

- 1) machine cycles, 32.7 ms at 12 MHz

- 1) machine cycles, 65.5 ms at 12 MHz

- 1) machine cycles, 131 ms at 12 MHz

- 1) machine cycles, 262 ms at 12 MHz

- 1) machine cycles, 542 ms at 12 MHz

- 1) machine cycles, 1.05 s at 12 MHz

- 1) machine cycles, 2.09 s at 12 MHz

Reset value = XXX0 0000 Write only register

WDT During Power-down and Idle

Power-down In Power-down mode the oscill ator stops, whi ch means the W DT also stops . While in

Power-down mode the us er doe s not need to service the W DT . The re ar e 2 m etho ds of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabl ed p rio r to e nter ing Po wer-do wn mo de. W hen Powe r-down is e xite d wit h hardware reset, servicing the WDT should occur as normal whenever the AT8xC5111 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. Wh en the interru pt is brought hig h, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not over flow wi thin a few sta tes of ex iting of power-down, it is best to reset the WDT just before entering power-down.

Idle Mode In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

AT8xC5111 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.

AT8xC5111

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AT8xC5111

Ports The low pin count versions of the AT8xC5111 has 3 I/O ports, port 1, port 3, and port 4.

All port1, port3 and port4 I/O port pins on the AT8xC5111 may be software configured to one of four types o n a bi t-by-b it basis , as shown i n Tab le 13. T hese are: qua si b i-dire ctional (standard 80C51 port outputs), push-pull, open drain, and input only. Two configuration registers for each port choose the output type for each port pin.

Table 1. Port Output Configuration Settings Using PxM1 and PxM2 Registers

PxM1.y Bit PxM2.y Bit Port Output Mode

0 0 Quasi bidirectional 0 1 Push-pull 1 0 Input Only (High Impedance) 1 1 Open Drain

Port Types

Quasi Bi-directional Output Configuration

The default port output configuration for standard AT8xC5111 I/O ports is the quasi bidirectional outp ut that is c ommon on th e 80C5 1 and mos t of i ts d erivativ es. Th is o utput type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features are somewhat simil ar t o an op en drai n output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The very weak pull- up sou rces a very small cur ren t t hat wil l pul l the pi n h igh i f i t i s lef t fl oat ing . A s ec ond pu ll -up, c al le d the "weak" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logi c 1 level. This pull-up prov ides the prim ary sour ce current for a quasi-bidirectiona l p in that is ou tputtin g a 1. If a pi n that h as a logi c 1 o n it i s pulle d low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these cond itions, the external devi ce has to sink enough current to ove rpower the weak pul l-up and take the vol tage on the port pin below its input threshold.

The third pull-up is referred to as the "strong" pull-up. T his pull-up is used to speed up low-to-high transitions on a quasi bi-directional port pin when the port latch changes from a logic 0 to a lo gic 1. When this occur s, the strong pull-up turns o n fo r a b rief tim e, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again.

The quasi bi-directional port configuration is shown in Figure 2.

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Figure 1. Quasi bi-directional Output

Port Latch Data

Open-drain Output Configuration

Figure 2. Open-drain Output

Port Latch Data

2 CPU CLOCK DELAY

Input Data

Strong

Very Weak

Weak

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch co ntains a logic 0. To be used as a logic output, a port configur ed in thi s manne r must have an exter nal pul l-up , typical ly a resi stor tied to V

. The pull-down for this mode is the sam e as for the quasi bi-directional

mode. The open-drain port configuration is shown in Figure 3.

Push-pull Output Configuration

Input Data

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi bi-directional output modes, but provides a continuous strong pullup when the port latch contain s a logic 1. Th e push-pul l mode may be used when mor e source current is needed from a port output. The push-pull port configuration is shown in Figure 4.

AT8xC5111

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Figure 3. Push-pull Output

AT8xC5111

Strong

Port latch Data

Input Data

Input Only Configuration The input only configuration is a pure input with neither pull-up nor pull-down.

The input only configuration is shown in Figure 5.

Figure 4. Input only

Input Data

Ports Description

Ports P1, P3 and P4 Every output on the AT8xC5111 may potentially be used as a 20 mA sink LED drive out-

put. However, there is a maximu m total o utput curre nt for all p orts whic h must no t be exceeded. All port pins of the AT8xC5111 have slew rate controlled outputs. This is to limit noise g enerated b y quic kly s wit chin g outp ut si gnals . T he s lew rate is facto ry set to approximately 10 ns rise and fall times.

The inputs of each I/O port of the AT8xC5111 are TTL level Schmitt triggers with hysteresis.

Ports P0 and P2 The high pin-count version of the AT8xC5 111 has standard address and data ports P0

and P2. These ports are standard C51 po rts (Qua si bi-di rection al I/O). Th e control li nes are provided on the pi ns: ALE, P SEN, EA P1.1 and P1.0 .

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, Reset; RD and WR signals are on the bits

Registers Table 2. P1M1 Address (D4h)

76543210

P1M1.7 P1M1.6 P1M1.5 P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0

Bit Number

7:0 P1M1.x

Bit

Mnemonic Description

Port Output configura tion bit

See Table 10. for configuration definition

Reset value = 0000 00XX

Table 3. P1M2 Address (E2h)

76543210

P1M2.7 P1M2.6 P1M2.5 P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0

Bit Number

7:0 P1M2.x

Bit

Mnemonic Description

Port Output configura tion bit

See Table 10. for configuration definition

Reset value = 0000 00XX

Table 4. P3M1 Address (D5h)

76543210

P3M1.7 P3M1.6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0

Bit Number

7:0 P3M1.x

Bit

Mnemonic Description

Port Output configura tion bit

See Table 10 for configuration definition

Reset value = 0000 0000

Table 5. P3M2 Address (E4h)

76543210

P3M2.7 P3M2.6 P3M2.5 P3M2.4 P3M2.3 P3M2.2 P3M2.1 P3M2.0

Bit

Number

7:0 P3M2.x

Bit

Mnemonic Description

Port Output configura tion bit

See Table 10 for configuration definition

Reset value = 0000 0000

AT8xC5111

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AT8xC5111

Table 6. P4M1 Address (D6h)

76543210

P4M1.7 P4M1.6 P4M1.5 P4M1.4 P4M1.3 P4M1.2 P4M1.1 P4M1.0

Bit Number

7:0 P4M1.x

Bit

Mnemonic Description

Port Output configura tion bit

See Table 10. for configuration definition.

Reset value = 0000 0000

Table 7. P4M2 Address (E5h)

76543210

P4M2.7 P4M2.6 P4M2.5 P4M2.4 P4M2.3 P4M2.2 P4M2.1 P4M2.0

Bit Number

7:0 P4M2.x

Bit

Mnemonic Description

Port Output configura tion bit

See Table 10. for configuration definition.

Reset value = 0000 0000

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AT8xC5111

Dual Data Pointer Register

Figure 1. Use of Dual Pointer

AUXR1(A2H)

The additional data pointer can be used to speed up code execution and reduce code size in a number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (see Table 19) that allows the program code to switch between them (See Figure 6).

External Data Memory

DPS

DPTR1

DPTR0

DPH(83H) DPL(82H)

Table 1. AUXR1: Auxiliary Registe r 1

76543210

-------DPS

Bit

Number

0DPS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Clear to select DPTR0. Set to select DPTR1.

Note: User software shoul d not wr ite 1s to res erved b its . These bit s may be us ed in fu ture 805 1

family products to invoke new features. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

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Application Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare, search...) are well served by using one data poin ter a s a ’source’ pointer and the oth er one as a "des tination" pointer.

ASSEMBLY LANGUAGE

; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,atDPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX atDPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, bu t simply togg les it. In simple routines , such as the block mov e examp le, only the fact that DPS is togg led in th e pr op er se quen ce matt er s, n ot i ts a ctu al val ue. In other words, th e block m ove rout ine work s the same whether DPS is '0' or '1' on en try. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

AT8xC5111

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AT8xC5111

Serial I/O Ports Enhancements

The serial I/O ports in the AT 8xC5111 are compatible with the serial I/O port in the 80C52.

They provide both synchronous and asynchronous communication modes. They operate as Univers al Asyn chrono us Recei ver a nd Transm itter (U ART) in three full-dupl ex modes (modes 1, 2 and 3 ). A syn chro nous tr ansm iss ion and r ecep tion ca n occu r si multaneously and at different baud rates.

Serial I/O ports include the following enhancements:

• Framing error detection

• Automatic address recognition

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framin g bi t erro r de tection feature, set SMOD0 bit in PCO N regi ster (see Figure 7).

Figure 1. Framing Error Block Diagram

SCON for UART (98h) (SCON_1 for UART_1 (C0h))

SM0/FE

SMOD0SMOD1

SM1

RENSM2

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART)

SM0 to UART mode control (SMOD0 = 0 for UART)

POF

GF1

RB8TB8

GF0

RITI

PCON for UART (87h) (SMOD bits for UART_1

IDLPD

are located in BDRCON_1)

Figure 2. UART Timings in Mode 1

RXD

SMOD0 = X

SMOD0 = 1

To UART framing error control

When this feature i s enabled, the receiv er c hec ks e ac h incoming data frame for a va li d stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (see Table 25) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE b it. W hen FE featur e is enab led, RI rise s on st op bit i nstead of th e last data bit (see Figure 8 and Figure 9).

D7D6D5D4D3D2D1D0

Start

Bit

Data Byte

Stop

Bit

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Figure 3. UART Timings in Modes 2 and 3

RXD

D8D7D6D5D4D3D2D1D0

Automatic Address Recognition

Start

Bit

Data Byte Ninth

Bit

Stop

Bit

SMOD0 = 0

SMOD0 = 1

The automatic address recognition feature is enabled for each UART when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).

Implemented i n hardwa re, au tomati c addre ss reco gnition enhan ces the m ultip roces sor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port re cognizes it s own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices.

If desired, you may enabl e the automatic address re cognition fea ture in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s addre ss and is te rminated by a valid stop bit.

To support automatic a ddr ess re co gni tio n, a dev ic e i s identified by a given add re ss and a broadcast address.

Note: The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).

Given Address Each UART has an individual ad dress that is sp ecified in SADDR r egiste r; the SA DEN

register is a mask byte that contains don’t care bits (defined by zeros) to form the device’s given address. The don’t care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:

SADDR0101 0110b SADEN

1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN

1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

Slave C:SADDR1111 0010b

1111 1001b

SADEN

Given1111 0XX1b

SADEN

1111 1101b

Given1111 00X1b

AT8xC5111

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