8K Bytes of Factory Programmable QuickFlash™ Memory
•
Fully Static Operation: 0 Hz to 20 MHz
•
Three-Level Program Memory Lock
•
256 x 8-Bit Internal RAM
•
32 Programmable I/O Lines
•
Three 16-Bit Timer/Counters
•
Eight Interrupt Sources
•
Programmable Serial Channel
•
Low Power Idle and Power Down Modes
•
8-Bit
Description
The AT80F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of Qui ckF lash memo ry. The dev ice i s m anuf actu red u sin g A tmel ’s hi gh d ens ity
nonvolatile memory technology and is compatib le with the indu stry standard 80C51
and 80C52 instruction set and pinout. The on-chip QuickFlash allows custom codes to
be quickly programmed in the factory. B y co mbi nin g a v ersa til e 8-bit CPU with QuickFlash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which
provides a highly flex ible and co st effe ctive solu tion to many embedd ed con trol app lications.
The AT80F52 provides the following standard features: 8K
bytes of QuickF lash, 25 6 bytes of RAM, 32 I/ O lines, three
16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip os cillator, and
clock circuitry. In addition, the AT80F52 is designed with
static logic for operation down to zero frequency and supports two softwar e selectable po wer saving modes . The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial p or t, and int er rupt s yst em to co nti nue
functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as highimpedance inputs.
Port 0 can also be configu red to be the multiplex ed loworder address/data bus during accesses to ex ternal program and data memory. In this mode, P0 has internal pullups.
Port 0 also out puts the c ode b yt es d uring p ro gram verification. External pu llups are requ ired dur ing pro gram ver ification.
Port 1
Port 1 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins , they are p ulled hi gh by
the internal pullups and can be used as inputs. As inputs ,
Port 1 pins that are externally being pulled low will source
current (I
In addition, P1.0 and P1. 1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during
QuickFlash verification.
Port PinAlternate Functions
P1.0T2 (external count input to Timer/Counter2),
P1.1T2EX (Timer/Counter 2 capture/reload trigger
) because of the internal pullups.
IL
clock-out
and direction control)
Port 2
Port 2 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 2 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I
) because of the internal pullups.
IL
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory th at u se 16 -b it a ddres s es ( MO VX @
DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 3 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
) because of the pullups.
IL
Port 3 also serv es t he fun ctions of v arious spe cial f eatures
of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for QuickFlash
verification.
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external memory.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE
pulse is skipped d ur in g ea ch ac c ess to ex ter na l d ata mem ory.
3-17
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT80F52 is executing code from external program memory, PSEN
cycle, except that two PSEN
is activated twice each machine
activations are skipped during
each access to external data memory.
EA
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA
will be
internally latched on reset.
should be strapped to VCC for internal program execu-
EA
tions.
XTAL1
Input to the inverting oscillator am plifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Table 1.
AT80F52 SFR Map and Reset Values
0F8H0FFH
0F0H
0E8H0EFH
0E0H
0D8H0DFH
0D0H
0C8H
0C0H0C7H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
B
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111
T2MOD
XXXXXX00
SBUF
XXXXXXXX
TMOD
00000000
SP
00000111
RCAP2L
00000000
TL0
00000000
DPL
00000000
RCAP2H
00000000
TL1
00000000
DPH
00000000
TL2
00000000
TH0
00000000
TH2
00000000
TH1
00000000
PCON
0XXX0000
0F7H
0E7H
0D7H
0CFH
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
3-18
AT80F52
AT80F52
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke
Table 2.
Symbol Function
TF2Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
EXF2Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =
T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8HReset Value = 0000 0000B
Bit Addressable
BitTF2EXF2RCLKTCLKEXEN2TR2C/T2
76543210
RCLK = 1 or TCLK = 1.
1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2
must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
new features. In th at case, th e reset or inac tive valu es of
the new bits will always be 0.
Timer 2 Registers:
Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCA P2L )
are the Capture/ Reloa d regist ers for Timer 2 i n 16-bit c apture mode or 16-bit auto-reload mode.
Interrupt Registers:
The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
CP/RL2
RCLKReceive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial
port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLKTrans mit clock enable. When set, causes the serial port to use Timer 2 o v erf lo w puls es f o r its tr ansm it clock in serial
port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX
if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
CP/RL2
Data Memory
The AT80F52 implements 256 bytes of on-chip RAM. The
upper 128 bytes oc cupy a parallel ad dress space to the
Special Function Register s. That means the u pper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on neg ativ e tran sitions at T2 EX if EXEN2 = 1. CP/RL 2
= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2
= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing inst ructi on, where R0 contains 0A 0H, a cc es ses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail able as stack space.
3-19
Timer 0 and 1
Timer 0 and Timer 1 in the AT80F52 operate the same way
as Timer 0 and Timer 1 in the AT89C51.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8- bi t regi st er s, TH2 and TL2. I n the
Timer function, the TL2 r egister is incremented ever y
machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In thi s func tion, the extern al i nput is sa mpled
during S5P2 of every machin e cycle. When the samples
in the SFR T2 C ON (sh o w n i n Ta bl e 2).
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator perio ds ) ar e re qui red to recognize a 1-to -0 tr an si tion, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 p er forms t he sa me operation, but a 1 to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, resp ective ly. In addi tion, th e transit ion at T2E X
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
is set to 0 so that ti mer 2 will defa ult to count u p. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.
Figure 1.
OSC
T2EX PIN
Timer in Capture Mode
÷12
T2 PIN
TRANSITION
DETECTOR
C/T2 = 0
C/T2 = 1
EXEN2
CONTROL
TR2
CAPTURE
CONTROL
TH2TL2
RCAP2LRCAP2H
EXF2
TF2
OVERFLOW
TIMER 2
INTERRUPT
3-20
AT80F52
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