ATMEL AT80F52-12AI, AT80F52-12AC, AT80F52-20PI, AT80F52-20PC, AT80F52-20JI Datasheet

Features

Compatible with MCS-51™ Products

•

8K Bytes of Factory Programmable QuickFlash™ Memory

•

Fully Static Operation: 0 Hz to 20 MHz

•

Three-Level Program Memory Lock

•

256 x 8-Bit Internal RAM

•

32 Programmable I/O Lines

•

Three 16-Bit Timer/Counters

•

Eight Interrupt Sources

•

Programmable Serial Channel

•

Low Power Idle and Power Down Modes

•

8-Bit

Description

The AT80F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of Qui ckF lash memo ry. The dev ice i s m anuf actu red u sin g A tmel ’s hi gh d ens ity
nonvolatile memory technology and is compatib le with the indu stry standard 80C51
and 80C52 instruction set and pinout. The on-chip QuickFlash allows custom codes to
be quickly programmed in the factory. B y co mbi nin g a v ersa til e 8-bit CPU with Quick­Flash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which
provides a highly flex ible and co st effe ctive solu tion to many embedd ed con trol app li­cations.

(continued)

Pin Configurations

TQFP

INDEX
CORNER

P1.5
P1.6
P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

P1.4

44

1
2
3
4
5
6
7
8
9
10
11

13

12

(WR) P3.6

P1.3

P1.2

424340

41

15

14

XTAL2

(RD) P3.7

P1.1 (T2 EX)

16

XTAL1

P1.0 (T2)

39

17

GND

NC

38

18

GND

VCC

37

19

(A8) P2.0

P0.1 (AD1)

P0.0 (AD0)

36

35

21

20

(A9) P2.1

(A10) P2.2

P0.2 (AD2)

P0.3 (AD3)

34

33
32

31
30
29
28
27
26
25
24
23

22

(A11) P2.3

(A12) P2.4

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA

NC

ALE
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

(T2) P1.0

(T2 EX) P1.1

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

P1.2

P1.3
P1.4
P1.5
P1.6
P1.7

RST
(RXD) P3.0
(TXD) P3.1

(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7 P2.3 (A11)

XTAL2 P2.2 (A10)
XTAL1 P2.1 (A9)

GND P2.0 (A8)

INDEX
CORNER

P1.5
P1.6
P1.7

RST

NC

(T0) P3.4
(T1) P3.5

PDIP

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA
ALE
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)

PLCC

NC

VCC

P0.0 (AD0)

P0.2 (AD2)

P1.0 (T2)

1

23

GND

NC

424340

252827

26

(A9) P2.1

(A8) P2.0

P0.1 (AD1)

41

(A10) P2.2

(A11) P2.3

P1.2

P1.1 (T2 EX)

P1.3

P1.4

65444

2

3

7
8
9
10
11
12
13
14
15
16
17 29

21

181920 24

22

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

P0.3 (AD3)

39

38
37

36
35
34
33
32
31
30

(A12) P2.4

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA

NC

ALE
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

Microcontroller
with 8K Bytes
Quic kFlash

™

Memory

AT80F52

0980A-A–12/97

3-15

Block Diagram

V

CC

GND

RAM ADDR.

REGISTER

B

REGISTER

ACC

TMP2

P0.0 - P0.7

PORT 0 DRIVERS

RAM

PORT 0

LATCH

TMP1

PORT 2 DRIVERS

PORT 2

LATCH

POINTER

P2.0 - P2.7

QUICK
FLASH

STACK

PROGRAM

ADDRESS

REGISTER

BUFFER

PSEN

ALE

EA

RST

TIMING

AND

CONTROL

OSC

INSTRUCTION

REGISTER

ALU

PSW

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PC

INCREMENTER

PROGRAM

COUNTER

DPTR

3-16

AT80F52

AT80F52

The AT80F52 provides the following standard features: 8K
bytes of QuickF lash, 25 6 bytes of RAM, 32 I/ O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi­tecture, a full duplex serial port, on-chip os cillator, and
clock circuitry. In addition, the AT80F52 is designed with
static logic for operation down to zero frequency and sup­ports two softwar e selectable po wer saving modes . The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial p or t, and int er rupt s yst em to co nti nue
functioning. The Power Down Mode saves the RAM con­tents but freezes the oscillator, disabling all other chip func­tions until the next hardware reset.

Pin Description

V

CC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 can also be configu red to be the multiplex ed low­order address/data bus during accesses to ex ternal pro­gram and data memory. In this mode, P0 has internal pul­lups.

Port 0 also out puts the c ode b yt es d uring p ro gram verifica­tion. External pu llups are requ ired dur ing pro gram ver ifica­tion.

Port 1

Port 1 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins , they are p ulled hi gh by
the internal pullups and can be used as inputs. As inputs ,
Port 1 pins that are externally being pulled low will source
current (I

In addition, P1.0 and P1. 1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port 1 also receives the low-order address bytes during
QuickFlash verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter2),

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

) because of the internal pullups.

IL

clock-out

and direction control)

Port 2

Port 2 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 2 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory th at u se 16 -b it a ddres s es ( MO VX @
DPTR). In this application, Port 2 uses strong internal pul­lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during QuickFlash verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 3 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serv es t he fun ctions of v arious spe cial f eatures
of the AT89C51, as shown in the following table.

Port 3 also receives some control signals for QuickFlash
verification.

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD

(external interrupt 0)

(external data memory write strobe)

(external data memory read strobe)

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

ALE

Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem­ory.

In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim­ing or clocking purposes. Note, however, that one ALE
pulse is skipped d ur in g ea ch ac c ess to ex ter na l d ata mem ­ory.

3-17

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT80F52 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN

is activated twice each machine

activations are skipped during

each access to external data memory.

EA

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA

will be

internally latched on reset.

should be strapped to VCC for internal program execu-

EA
tions.

XTAL1

Input to the inverting oscillator am plifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1.

AT80F52 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

B

00000000

ACC

00000000

PSW

00000000

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

RCAP2L

00000000

TL0

00000000

DPL

00000000

RCAP2H

00000000

TL1

00000000

DPH

00000000

TL2

00000000

TH0

00000000

TH2

00000000

TH1

00000000

PCON

0XXX0000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

3-18

AT80F52

AT80F52

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke

Table 2.

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =

T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

76543210

RCLK = 1 or TCLK = 1.

1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2
must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

new features. In th at case, th e reset or inac tive valu es of
the new bits will always be 0.

Timer 2 Registers:

Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCA P2L )
are the Capture/ Reloa d regist ers for Timer 2 i n 16-bit c ap­ture mode or 16-bit auto-reload mode.

Interrupt Registers:

The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.

CP/RL2

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial

port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Trans mit clock enable. When set, causes the serial port to use Timer 2 o v erf lo w puls es f o r its tr ansm it clock in serial

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX

if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2

CP/RL2

Data Memory

The AT80F52 implements 256 bytes of on-chip RAM. The
upper 128 bytes oc cupy a parallel ad dress space to the
Special Function Register s. That means the u pper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge

triggered).

Capture/Reload select. CP/RL2 = 1 causes captures to occur on neg ativ e tran sitions at T2 EX if EXEN2 = 1. CP/RL 2

= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2

= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing inst ructi on, where R0 contains 0A 0H, a cc es ses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail ­able as stack space.

3-19

Timer 0 and 1

Timer 0 and Timer 1 in the AT80F52 operate the same way
as Timer 0 and Timer 1 in the AT89C51.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.

Timer 2 consists of two 8- bi t regi st er s, TH2 and TL2. I n the
Timer function, the TL2 r egister is incremented ever y
machine cycle. Since a machine cycle consists of 12 oscil­lator periods, the count rate is 1/12 of the oscillator fre­quency.

Table 3.

RCLK +TCLK CP/RL2 TR2 MODE

Timer 2 Operating Modes

0 0 1 16-Bit Auto-Reload
0 1 1 16-Bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)

In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In thi s func tion, the extern al i nput is sa mpled
during S5P2 of every machin e cycle. When the samples

in the SFR T2 C ON (sh o w n i n Ta bl e 2).

show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator perio ds ) ar e re qui red to recognize a 1-to -0 tr an si ­tion, the maximum count rate is 1/24 of the oscillator fre­quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 p er forms t he sa me operation, but a 1 ­to-0 transition at external input T2EX also causes the cur­rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, resp ective ly. In addi tion, th e transit ion at T2E X
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus­trated in Figure 1.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
is set to 0 so that ti mer 2 will defa ult to count u p. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.

Figure 1.

OSC

T2EX PIN

Timer in Capture Mode

÷12

T2 PIN

TRANSITION

DETECTOR

C/T2 = 0

C/T2 = 1

EXEN2

CONTROL

TR2

CAPTURE

CONTROL

TH2 TL2

RCAP2LRCAP2H

EXF2

TF2

OVERFLOW

TIMER 2

INTERRUPT

3-20

AT80F52

AT80F52

Figure 2 shows Timer 2 au tomatically counting u p when
DCEN = 0. In this mod e, two options a re selecte d by bit
EXEN2 in T2CON. If EXEN2 = 0, Tim er 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The over­flow also causes the tim er regi ste r s to be re loa ded with the
16-bit value in RCAP2H and RCAP2L. The valu es in Timer
in Capture ModeRCAP 2H and RCAP2 L are pre set b y soft­ware. If EXEN2 = 1, a 16 -bit rel oad can be tr igger ed ei ther
by an overflow or by a 1-t o-0 transition at ex ternal input
T2EX. This transition also sets the EXF2 bit. Both the TF2
and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enabl es Time r 2 to coun t up o r d own ,
as shown in Figure 3. In this mode, the T2EX pin controls

Figure 2.

Timer 2 Auto Reload Mode (DCEN = 0)

OSC

T2 PIN

÷12

C/T2 = 0

C/T2 = 1

CONTROL

TR2

the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overfl ow also causes the 16-bit va lue in
RCAP2H and RCAP2L to be reloaded into the timer regis­ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stor ed in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.

TH2 TL2

OVERFLOW

RELOAD

TIMER 2

RCAP2LRCAP2H

INTERRUPT

TRANSITION

DETECTOR

T2EX PIN

CONTROL

EXEN2

Table 4.

Symbol Function

— Not implemented, reserved for future
T2OE Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable

——————T2OEDCEN

Bit76543210

TF2

EXF2

3-21

Figure 3.

Timer 2 Auto Reload Mode (DCEN = 1)

OSC

Figure 4.

12

÷

T2 PIN

C/T2 = 0

TR2

C/T2 = 1

Timer 2 in Baud Rate Generator Mode

(DOWN COUNTING RELOAD VALUE)

0FFH0FFH

OVERFLOW

TH2 TL2

CONTROL

RCAP2LRCAP2H

(UP COUNTING RELOAD VALUE)

TOGGLE

EXF2

TF2

TIMER 2

INTERRUPT

COUNT
DIRECTION
1=UP
0=DOWN

T2EX PIN

OSC

T2 PIN

T2EX PIN

2

÷

TRANSITION

DETECTOR

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12

C/T2 = 0

TH2 TL2

CONTROL

TR2

C/T2 = 1

EXF2

CONTROL

EXEN2

TIMER 1 OVERFLOW

2

÷

"1"

"0"

SMOD1

"1"

"0"

RCLK

16

÷

"1"

"0"

RCAP2LRCAP2H

TIMER 2

INTERRUPT

TCLK

16

÷

Rx

CLOCK

Tx

CLOCK

3-22

AT80F52

AT80F52

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the baud
rates for transmit and receive can be different if Timer 2 is
used for the rece iver or tr ansm itter a nd Tim er 1 is used f or
the other function. Setting RCLK and/or TCLK puts Timer 2
into its baud rate generator mode, as shown in Figure 4.

The baud rate gener ator mod e is s imilar to the au to-rel oad
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.

The baud rates in Mod es 1 a nd 3 ar e det ermin ed by Tim er
2’s overflow rate according to the following equation.

Modes 1 and 3 Baud Rates

The Timer can be configured for either timer or counter
operation. In most applicat ions, it is configured for tim er
operation (CP/T2

= 0). The timer ope ration is different for
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency ). As a ba ud rate generator , howev er, it

Timer 2 Overflow Rate

----------------------------------------------------------- -=

16

increments every state time (at 1/2 the oscillator fre­quency). The baud rate formula is given below.

Modes 1 and 3

---------------------------------------

Baud Rate

Oscillator Frequency

---------------------------------------------------------------------------------------------=

32 65536 RCAP2H RCAP2L

(,)–[]×

where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener­ate an interrupt . Note too, th at if EXEN2 i s set, a 1-t o-0
transition in T2EX will set E XF2 but will not caus e a reload
from (RCAP2H, RCAP2L) to (TH2, TL2 ). Thus when Timer
2 is in use as a baud rate gen erator , T2EX can be used as
an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP2 registers may be
read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.

Figure 5.

(T2EX)

Timer 2 in Clock-Out Mode

OSC

P1.0

(T2)

TRANSITION
DETECTOR

P1.1

÷2

EXEN2

TR2

C/T2 BIT

EXF2

(8-BITS)

RCAP2L RCAP2H

÷2

TIMER 2
INTERRUPT

TL2

T2OE (T2MOD.1)

TH2

(8-BITS)

3-23

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu­lar I/O pin, has two alternat e functions. It can be pro­grammed to input the e xte rn al clo ck for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 4
MHz at a 16

MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit

(T2CON.1) must be cleared and bit T2OE (T2MOD.1)

C/T2
must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator fre­quency and the r eload valu e of Time r 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.

Clock-Out Frequency

Oscillator Fequency

------------------------------------------------------------------------------------------=

4 65536 RCAP2H RCAP2L

(,)–[]×

In the clock-out mode, Timer 2 roll-overs will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock g enerator simul ta­neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.

UART

The UART in the AT80F52 operates the same way as the
UART in the AT89C52.

Table 5.

(MSB) (LSB)

Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0,

— IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits,

because they may be used in future AT89 products.

Figure 6.

Interrupt Enable (IE) Register

EA — ET2 ES ET1 EX1 ET0 EX0

no interrupt is acknowledged. If
EA = 1, each interrupt source is
individually enab led or disabled
by setting or c learing its enable
bit.

Interrupt Sources

Interrupts

The AT80F52 has a total o f s ix in terr upt vec tor s : two exter ­nal interrupts (INT0
ers 0, 1, and 2), and the s erial port i nterrupt. T hese in ter­rupts are all shown in Figure 6.

Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Fu nction
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.

Note that T able 5 show s that bit position IE.6 is u nimple­mented. In the AT89C51, bit position IE.5 is also unimple­mented. User software should not write 1s to these bit posi­tions, since they may be used in future AT89 products.

Timer 2 interrupt is gen er ated by the log ic al OR o f bi ts TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware whe n the servi ce routine i s vectored
to. In fact, the service rout ine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.

The Timer 0 and Timer 1 fl ags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers ov erflow. The va lues
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.

and INT1), three timer interrupts (Tim-

INT0

TF0

INT1

TF1

TF2

EXF2

0

1

0

1

TI

RI

IE0

IE1

3-24

AT80F52

AT80F52

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, resp ectively,
of an inverting amplifier that can be confi gured for use as
an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 8.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi­mum voltage high and low time specifications must be
observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on­chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe­cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any en abled
interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware
reset, the device norm ally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi­nated by a reset, the instruction following the one that
invokes idle m ode s hou ld not write to a por t p in or to exter ­nal memory.

Power Do wn Mode

In the power down mode, the oscillator is stopped, and the
instruction t hat invo kes po wer down is th e last instru ction
executed. The on-chip RAM and Special Function Regis­ters retain their values until the power d own m ode is ter mi­nated. The only exit fr om power do wn is a hard ware reset .
Reset redefines the SFRs but does not change the on-c hip
RAM. The reset should not be activated before V

CC

is

restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta­bilize.

Figure 7.

Note: C1, C2 = 30 pF ± 10 pF for Crystals

Figure 8.

Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

= 40 pF ± 10 pF for Ceramic Resonators

External Clock Drive Configuration

NC

EXTERNAL

OSCILLATOR

SIGNAL

XTAL2

XTAL1

GND

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Po w er Down Internal 0 0 Data Data Data Data
Power DownExternal 00FloatDataDataData

3-25

Program Memory Lock Bits

The AT80F52 has three lock bits that can be left unpro­grammed (U) or can be programmed (P) to obtain the addi­tional features listed in the following table.

Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features.
2 P U U MOVC instructions executed

from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on reset,
and further programming of
the QuickFlas h mem ory is
disable d.

3 P P U Same as mode 2, but verify is

also disabled.

4 P P P Same as mode 3, but external

execution is also disabled.

When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during rese t. If the device is pow­ered up without a reset, the latch initi alizes to a random

value and holds that value until reset is activated. The
latched value of EA
at that pin in order for the device to function properly.

must agree wi th the cu rre nt logic level

Programming/Verifying the QuickFlash

The AT80F52 can only be p rogrammed by Atmel. Cus­tomer codes should be submitted in
disk or uploaded to Atmel ’s bu lleti n board or Web sit e. The
code should be in the Intel Hex format. The desired states
of the Lock Bits should be specified. Once programmed,
the code memory and Lock Bits cannot be erased or repro­grammed.

Please consult the factory or Atmel’s representati ves for
details on submitting custom codes.

Program Verify:

programmed, the programmed code data can be read back
via the address and data line s for verific ation . The lock bits
cannot be verified dire ctly. Verificati on of the lock bits is
achieved by observing that their features are enabled.

Reading the Signature Bytes:

read by the same procedure as a normal verification of
locations 030H, 031H, and 032H, except that P 3.6 and
P3.7 must be pulled to a logic low. The values retur ned are
as follows.

(030H) = 1EH indicates manufactured by Atmel
(031H) = 80H indicates QuickFlash
(032H) = 02H indicates AT80F52

If lock bits LB1 and LB2 have not been

duplicate

The signature bytes are

on a floppy

QuickFlash Verification Modes

Mode

Read Code Data H L H H L L H H
Read Signature Byte H L H H L L L L

RST PSEN ALE EA P2.6 P2.7 P3.6 P3.7

3-26

AT80F52

AT80F52

Figure 9.

Verifying the QuickFlash Memory

OOOOH/1FFFH

SEE QUICK FLASH

VERIFICATION

MODES TABLE

3-20 MHz

ADDR.

A0 - A7

A8 - A12

AT80F52

P1
P2.0 - P2.4
P2.6
P2.7
P3.6
P3.7
XTAL2 EA

XTAL1
GND

V

P0

ALE

RST

PSEN

CC

+5V

PGM DATA
(USE 10K
PULLUPS)

V

IH

V

IH

QuickFlash Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0 ± 10%

Symbol Parameter

1/t

CLCL

t

AVQV

t

ELQV

t

EHQZ

Oscillator Frequency 3 20 MHz
Address to Data Valid 48t
ENABLE Low to Data Valid 48t
Data Float After ENABLE 0 48t

QuickFlash Verification Waveforms

P1.0 - P1.7
P2.0 - P2.4

PORT 0

ALE

EA

Min Max Units

VERIFICATION

ADDRESS

t

AVQV

DATA OUT

LOGIC 1
LOGIC 0

LOGIC 1
LOGIC 0

CLCL
CLCL
CLCL

P2.7

(ENABLE)

t

ELQV

t

EHQZ

3-27

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

Storage Temperature.....................................-65°C to +150°C

age to the de vice . This is a s tress r ating onl y and

functional opera tion of the de vice at these or an y
Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

Maximum Operating Voltage.............................................6.6V

conditions for extended periods may affect

device reliability.

DC Output Current......................................................15.0 mA

DC Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted.

Symbol Parameter Condition Min Max Units

V

IL

V

IL1

V

IH

V

IH1

V

OL

V

OL1

V

OH

V

OH1

I

IL

I

TL

I

LI

RRST Reset Pulldown Resistor 50 300 K
C

IO

I

CC

Notes: 1. Under steady state (non-transient) conditions, IOL must be external ly limited as follows:

2. Minimum V

Input Low V oltage (Except EA)-0.50.2 V
Input Low Voltage (EA)-0.50.2 V
Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V
Input High Volt age (XTAL1, RST) 0.7 V
Output Low Voltage
Output Low Voltage

(Port 0, ALE , PSEN)
Output High Voltage

(Ports 1,2,3, ALE, PSEN

Output High Voltage
(Port 0 in External Bus Mode)

Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50
Logical 1 to 0 Transition Current

(Ports 1,2,3)
Input Leakage Current (Port 0, EA) 0.45 < VIN < V

Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
Power Supply Current Active Mode, 12 MHz 25 mA

Power Down Mode

Maximum I
Maximum I

per port pin: 10 mA

OL

per 8-bit port:

OL

(1)

(Ports 1,2,3) IOL = 1.6 mA 0.45 V

(1)

)

(1)

I

= 3.2 mA 0.45 V

OL

I

= -60 µA, VCC = 5V ± 10% 2.4 V

OH

I

= -25 µA 0.75 V

OH

I

= -10 µA0.9 VCCV

OH

IOH = -800 µA, VCC = 5V ± 10% 2.4 V
I

= -300 µA 0.75 V

OH

I

= -80 µA0.9 VCCV

OH

VIN = 2V, VCC = 5V ± 10% -650

CC

Idle Mode, 12 MHz
VCC = 6V
VCC = 3V

CC

CC

CC

-0.1 V

CC

-0.3 V

CC

VCC+0.5 V

±

10

6.5 mA

100

40

Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total I
If I

exceeds the test condition, V

OL

for all output pins: 71 mA

OL

OL

may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

for Power Down is 2V.

CC

V

V

µ

A

µ

A

µ

A

Ω

µ

A

µ

A

3-28

AT80F52

AT80F52

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs =
80 pF.

External Program and Data Memory Characteristics

Symbol Parameter 12 MHz Oscillator Variable Oscillator Units

Min Max Min Max

1/t

CLCL

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

PLAZ

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

t

WHLH

Oscillator Frequency 0 20 MHz
ALE Pulse Width 127 2t
Address Valid to ALE Low 43 t
Address Hold After ALE Low 48 t
ALE Low to Valid Instruction In 233 4t
ALE Low to PSEN Low 43 t
PSEN Pulse Width 205 3t
PSEN Low to Valid Instruction In 145 3t

-40 ns

CLCL

-13 ns

CLCL

-20 ns

CLCL

-65 ns

CLCL

-13 ns

CLCL

-20 ns

CLCL

-45 ns

CLCL

Input Instruction Hold After PSEN 00ns
Input Instruction Float After PSEN 59 t
PSEN to Address Valid 75 t

-8 ns

CLCL

Address to Valid Instruction In 312 5t

-10 ns

CLCL

-55 ns

CLCL

PSEN Low to Address Float 10 10 ns
RD Pulse Width 400 6t
WR Pulse Width 400 6t
RD Low to Valid Data In 252 5t

-100 ns

CLCL

-100 ns

CLCL

-90 ns

CLCL

Data Hold After RD 00ns
Data Float After RD 97 2t
ALE Low to Valid Data In 517 8t
Address to Valid Data In 585 9t
ALE Low to RD or WR Low 200 300 3t
Address to RD or WR Low 203 4t
Data Valid to WR Transition 23 t
Data Valid to WR High 433 7t
Data Hold After WR 33 t

-50 3t

CLCL

-75 ns

CLCL

-20 ns

CLCL

-120 ns

CLCL

-20 ns

CLCL

-28 ns

CLCL

-150 ns

CLCL

-165 ns

CLCL

+50 ns

CLCL

RD Low to Address Float 0 0 ns
RD or WR High to ALE High 43 123 t

-20 t

CLCL

+25 ns

CLCL

3-29

External Program Memory Read Cycle

t

LHLL

ALE

t

AVLL

t

LLPL

PSEN

t

LLAX

PORT 0

PORT 2

A0 - A7 A0 - A7

t

AVIV

A8 - A15

External Data Memory Read Cycle

t

LHLL

ALE

t

PLAZ

t

LLIV

t

PLIV

t

PXIZ

t

PXIX

INSTR IN

t

PLPH

t

PXAV

t

WHLH

A8 - A15

PSEN

RD

PORT 0

PORT 2

t

LLDV

t

LLWL

t

LLAX

t

AVLL

A0 - A7 FROM RI OR DPL

t

AVWL

P2.0 - P2.7 OR A8 - A15 FROM DPH

t

AVDV

t

RLAZ

t

RLRH

t

RLDV

DATA IN INSTR IN

t

RHDZ

t

RHDX

A0 - A7 FROM PCL

A8 - A15 FROM PCH

3-30

AT80F52

External Data Memory Write Cycle

t

LHLL

ALE

PSEN

t

LLWL

t

WLWH

t

WHLH

AT80F52

WR

PORT 0

PORT 2

t

AVLL

A0 - A7 FROM RI OR DPL

P2.0 - P2.7 OR A8 - A15 FROM DPH

t

AVWL

t

LLAX

t

QVWX

External Clock Drive Waveforms

t

0.7 V

CC

CHCX

CC

0.45V

V - 0.5V

CC

0.2 V - 0.1V

t

t

QVWH

DATA OUT INSTR IN

t

CLCH

t

CLCX

WHQX

A0 - A7 FROM PCL

A8 - A15 FROM PCH

t

CHCX

t

CLCL

t

CHCL

External Clock Drive

Symbol Parameter Min Max Units

1/t

CLCL

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

Oscillator Frequency 0 20 MHz
Clock Period 41.6 ns
High Time 15 ns
Low Time 15 ns
Rise Time 20 ns
Fall Time 20 ns

3-31

Serial Port Timing: Shift Register Mode Test Conditions

V

LOAD

+ 0.1V

Timing Reference

Points

V

LOAD

- 0.1V

LOAD

V

V

OL

+ 0.1V

V

OL

- 0.1V

The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF.

Symbol Parameter 12 MHz Osc Variable Oscillator Units

Min Max Min Max

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

Serial Port Clock Cycle Time 1.0 12t
Output Data Setup to Clock Rising Edge 700 10t
Output Data Hold After Clock Rising Edge 50 2t

CLCL

-133 ns

CLCL

-117 ns

CLCL

Input Data Hold After Clock Rising Edge 0 0 ns
Clock Rising Edge to Input Data Valid 700 10t

-133 ns

CLCL

Shift Register Mode Timing Waveforms

s

µ

INSTRUCTION

0

1

2

ALE

t

CLOCK

t

QVXH

WRITE TO SBUF

OUTPUT DATA

CLEAR RI

0

t

XHDV

VALID VALIDVALID VALIDVALID VALIDVALID VALID

INPUT DATA

AC Testing Input/Output Waveforms

V - 0.5V

CC

0.45V

0.2 V + 0.9V

CC

TEST POINTS

0.2 V - 0.1V

CC

XLXL

t

XHQX

1

(1)

3

2

t

XHDX

4

5

3

Float Waveforms

6

4

5

7

6

8

7

SET TI

SET RI

(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing mea­surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.

3-32

AT80F52

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change fro m load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded V

OH/VOL

level occurs.

Ordering Information

AT80F52

Speed

(MHz)

12 5V ± 20% AT80F52-12AC

16 5V ± 20% AT80F52-16AC

20 5V ± 20% AT80F52-20AC

Power

Supply O rdering Code Package Operation Range

AT80F52-12JC
AT80F52-12PC

AT80F52-12AI
AT80F52-12JI
AT80F52-12PI

AT80F52-16JC
AT80F52-16PC

AT80F52-16AI
AT80F52-16JI
AT80F52-16PI

AT80F52-20JC
AT80F52-20PC

AT80F52-20AI
AT80F52-20JI
AT80F52-20PI

44A
44J
40P6

44A
44J
40P6

44A
44J
40P6

44A
44J
40P6

44A
44J
40P6

44A
44J
40P6

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

44A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

3-33