ATMEL AT76C101 Datasheet
Features
•
Compatible with the JPEG Baseline Standard as Defined by ISO IS 109 18-1
•
Highly-integrated, Low-cost Single Chip Solution
•
Up to 40 Mbytes/sec Sustained Compression Rate
•
Maximum Processing Rate of 1.6 million pixels/sec
•
Supports 8-bit Grayscale and YUV 4:2:2 Color Space Input and Output Formats
•
Handles Images of Size up to 1024 x 1024 Pixels
•
Fast DCT/IDCT Processor On-chip
•
User-defined Quantiz atio n and Huffman Tables
•
Support for Fast as well as Slow/Inexpensive Memories
•
Provides Direct Interface for Microcontroller/Microprocessor Access
JPEG Image
Applications
The AT76C101 JPEG Processor is optimized for use in the following applications:
• Digital Cameras
• Color Printers and Plotters
• Low-cost Image Compression Systems
• Video Editing (3-4 frames/sec at CCIR 720 x 480 Image Resolution)
Hardware Resources
• On-chip Video Interface
• Custom Discrete Cosine Transform and Quantization Processor
• Variable Length and Huffman Encoder/Decoder
• Programmable Memory Interface (Supports Slow Memories)
• Microcontroller/Microprocessor Access Bus
Pin Configuration
100-Pin QFP
SRDATA
SRADDR
PXWE
PXRE
PXIN
PXOUT
STOP_PIXEL
SRDRIVE
H_SYNC
V_SYNC
PX_CLK
CLK_IN
15-0
14-0
M_ADDR
MASTER_CS
MASTER_WR
MASTER_OE
19-0
M_DATA
MEM_CS
TEST
RESET
FRAMEND
FREEZE
BUSY
BST_TEST
7-0
Compression
Processor
AT76C101
Rev. 0751A–04/98
1
Description
The AT76C101 is an Image Compression/Decompression
Processor that performs the JPEG Baseline Algorithm. The
system is cap able of h igh q uality com pres sion an d deco mpression of co ntinues -tone c olor or mono chrom e imag es.
The AT76C101 performs the Discrete Cosine Transform,
Quantization, and Entropy Encoding during the compression stage and ca rries out all inve rse operat ions during th e
decompression ph ase. The AT76C101 use s an external
SRAM as working memory, which is accessed by an onchip video interface.
The AT76C101 is designed to operate with minimum host
intervention. A host processor is required to program the
chip in the required operating mode, and to extract the
JPEG header from the compressed bit stream during the
decompression phase. Based on this information, it then
initializes the internal registers. Once the chip has been initialized, the AT76C101 operates continuously until it has
completed compression/decompression of a image frame.
The image compression ratio is contr olled by the user supplied quantization tables, which are loaded before the compression/decompression operation. Compression ratios
from 1:1 to 50:1 are possib le depe nding on the quality an d
storage requirements of the application.
Basic System Configuration
An AT76C101-based i mage comp ression sy stem is show n
in Figure 1. The AT76C101 requires the following external
devices:
• A microcontrolle r to program and in itial ize the chip in the
required operating mode. This device is also used to
strip the JPEG header during decompression and to
provide the AT76C101 with the header information.
• An external working memory (SRAM) for handling
uncompressed/decompressed images. The size of this
memory depends on the size of the image being
processed. The formula to assess the memory size is
give n in the Pixel Interface section of this manual.
• An external memory device to store the compressed
data stream. This external memo ry can be either a fast
memory or a slow inexpensive memory. The size of this
memory depends on the needs of the specific
application.
Figure 1.
IMAGE TO
DISPLAY
AT76C101-based Image Compression System
RAW_OUT
YUV
BUFFER
OUTPUT
INPUT
BUFFER
DATA15-0 ADDR15-0
SAMPLING & COLOR
CONVERSION
RGB
VIDEO
LOGIC
INTERFACE
24-BIT
RGB
Image
Source
32K x 16
SRAM
RE
WE
SRDATA
15-0
SRADDR
14-0
PXWE
PXRE
PXIN
PXOUT
STOP_PIXEL
SRDRIVE
H_SYNC
V_SYNC
PX_CLK
CLK_IN
AT76C101
M_ADDR
19-0
M_DATA
MEM_CS
TEST
RESET
FRAMEND
FREEZE
MASTER_CS
MASTER_WR
MASTER_OE
BUSY
7-0
MICROCONTROLLER
ADDR19-0
DATA7-0
CS
COMPRESSED
DATA
MEMORY
WR
OE
2
AT76C101
System Overview
AT76C101
Pixel Interface
The pixel interface is used to input uncompressed data during the compression mode, or to output decompres sed
data during the decompression mode. The AT76C101
expects uncompresse d image d ata eithe r in YUV 4:2 :2 (for
color images), or in gray scale format. D uring decompre ssion, the AT76C101 generates images in the same format.
This interface requires an external buffer as work ing memory (Figure 2). During co mpression , the exter nal buffer is
used to store the incoming pixel s. After 8 scan lines are
read in, the AT7 6C101 perf orms a ra ster t o 8 x8 blo ck conversion of the in put data . During the invers e opera tion, th e
AT76C101 converts the outgoing pixels into the raster format and stores them in the external buffer. The uncompressed data is synchronized with the PX_CLK signal. This
clock runs at twice the pixel rate so that two transfers can
occur for each pixel, one to read pixel data from the external SRAM and one to write pixel data to the external
SRAM.
Two signals synchronize video interface operation, HSync
and VSync. These are active low, bi-directional signals and
they are controlled fr om th e Ma st er bit of th e Mo de register
of the chip. When Master is high, HSync and VS ync are
generated and driven by the chip. When Mas ter is low,
these two signa ls a re rea d a s input s by t he ch ip. In Mas ter
mode, the registers HPeriod, HSyncWidth, VPeriod, and
VSyncWidth are used to generate HSync and VSync. HPeriod contains the total number of pixels per s can line, and
HSyncWidth, the width of active HSync in number of pixels.
VPeriod and VSyncWidth provide the same type of information for VSync in terms of scan lines, rather than pixels.
These registers and others are used to control the video
interface of the chip. The other registers are HDelay, HActive, VDelay, and VActive. HDelay contains the number of
pixels between falling HSync and the first active pixel of a
line. HActive contains the number of active blocks in a line.
The size of the working memory depends on the size of the
image being processed. The external buffer should be
deep enough to store 16 scan li nes of dat a at the hi ghest
horizontal resolution. The equations for determining the
external buffer size are:
• Buffer bus width = 16 bits [For YUV data], 8 bits [For
Grayscale data]
• Buffer size = 16 x (No. of pixels per line)
As an example, a system designed to process images of
the maximum size of 1024 x 1024 pixels would have the
following external buffer requirements:
• Buffer size = 16 x 1024 = 16,384 words
Thus, this system would requ ire 1 6K x 1 6 workin g memo ry
to process YUV images (color) and 16K x 8 working memory to process grayscale images . As the minimum size of
available SRAM is 32K x 8, the SRAM requirements are as
follows: YUV/grayscale images: two 32K x 8 SRAM’s to
form a 32K x 16 SRAM.
Figure 2.
Memory Organization
32K x 16 SRAM
0000h
DATABANK A
2000h
NOT USED
4000h
DATABANK B
6000h
NOT USED
7FFFh
SRAM ORGANIZATION FOR MAXIMUM SCAN LINE SIZE OF 1024 PIXELS.
EACH DATABANK STORES 8 SCAN LINES OF THE RAW IMAGE.
4000h
4400h
5C00h
DATABANK B
SCAN LINE 1
SCAN LINE 2
SCAN LINE 8
1024 PIXELS
000h
001h
002h
3FEh
3FFh
SCAN LINE
YU
YV
YU
YV
YU
YV
16 BITS
AFTER COMPRESSION
YU
YV
8 BITS
AFTER DECOMPRESSION
8 BITS
8 BITS
UY
UV
8 BITS
3
Host Interface
This is a 8-bi t i nter face that all ows t he AT76 C101 to t ran sfer the compressed data to an external memory device.
This interfaces als o allows an external micr ocontroller/microprocessor (complexity of AT89C51) to access the
internal memory (registers and tables) of the AT76C101.
Two types of transfers can be carried out through this interface: the compressed data transfers and the microcontroller data accesses.
Compressed Data Mode
The host interface can work with a number of external
memory devices. It has two programmable registers
through which the user can specify up to eight wait states
that allows the chip to inter face w ith sl ow mem ory dev ices.
Data transfers are 8 bit wide and are carried out through
the Data Bus, Address Bus and the control signals
MEM_CS, MASTER_OE and MASTER_WR. The
AT76C101 is the bu s mast er and co ntrols all tran sfers t o
the external memory. Other device s cannot access the
memory while the AT76C101 is in the operating mode.
The cycle time of the compressed data transfer varies from
one to eight CLK cycles. This cycle time is contr olled by
two registers, the Read_Cnt_Reg whi ch contro ls the read
cycle time, and Write_Cnt_Reg which controls the write
cycle time. These registers are programmed by the microcontroller during initialization. The addr ess bus is also i nitialized from the Mem _Start_A ddr reg ister, wh ich ho lds th e
start address of the compressed data memory.
Microcontroller Access Mode
In this mode, the main function of the host interface is to
allow extern al de vices , (i .e. mi croco ntrol ler or a ho st p rocessor) to access the internal memory of the JPEG chip.
This is required to program the AT76C101 in the desired
mode of operation , to load the inte rnal quantiz ation and
Huffman tables during initialization, and to read the status
of the chip for testing purposes.
All transfers to the internal memory and tables of the JPEG
codec are 8-bit wide . Data is transferr ed using the Dat a
Bus, Address Bus, and the control s ignals MASTER_WR,
MASTER_OE, MAST ER_ CS an d BUS_ BUSY. All t rans fer s
carried out in this mo de are contr olled by th e microco ntroller.
When the AT76C101 ch ip is ope ra tin g in normal mode (i.e.
either compression or decompression), it acts as a bus
master on the external memory/microcontroller bus. Since
the AT76C101 has higher priority over the micro controller
for these bus accesses, the microcontroller has to check
the availability of the bus (by check ing BU S_BU SY) bef ore
it can access it. Once all the internal registers of the
AT76C101 are set up and the tab les are loaded, the
AT76C101 is activated by setting the Start_Reg register.
Once the compression/decompression operation starts, the
AT76C101 takes control of the bus, and gives it up only
after the chip has processed the image.The microcontroller
can access the internal memo ry of the AT76C101 only
between frames and not during normal mode of operation.
Data Control
During compression, the AT76C101 monitors the internal
image buffers and s ends a stall sign al (STOP) to prevent
the external video interface logic from generating new pixels, in case the inter nal buf fers are full . Duri ng dec ompression, the AT76C10 1 controls the tran sfer rate from the
compressed data interface, based on the status of the compressed data FIFO (Figure 3).
Figure 3.
SRDATA [15:0]
PX_CLK
SRADDR [14:0]
PXRE
PXWE
PXIN
PXOUT
H_SYNC
V_SYNC
BLANK
STOP_PIXEL
4
Data Control
PIXEL
BUFFER
PIXEL
BUFFER
PIXEL
INTERFACE
QUANTIZATION
TABLE
DCT/IDCT &
QUANTIZATION
MODULE
AT76C101
BUFFER
DCT COEFFICIENT
UNIT
ZIGZAG
HUFFMAN
ENCODER
HUFFMAN
TABLES
HUFFMAN
DECODER
HIGH LEVEL
CONTROL
UNIT
BIT STUFFER
FIFO
COMP. DATA
REGISTER FILE
& TEST MODULE
HOST
INTERFACE
TEST
MASTER_CS
MASTER_OE
MASTER_WR
M_ADDR
M_DATA
MEM_CS
BUS_BUSY
RESET
END_FRAME
FREEZE
CLK_IN
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