Datasheet AT76C002 Datasheet (ATMEL)

Programmable
FIR Filter

AT76C002

Features

16 Multiplier-Accumulators

•

16 Bit Data and 12 Bit Coefficients, 32 Bit Internal Accuracy

•

16 Banks of 12 Bit Coefficients

•

16 Taps at 33 MHz

•

Up to 32 Taps for Symmetrical or Inte rleaved Zeroed Coeffi cient Filters at 33 MHz

•

Up to 63 Taps for Symmetrical Halfb an d Fi lters at 33 MHz

•

Programmable Dec im ation by 2, 4, 8 or 16

•

Cascadable Kee pi ng Symmetry Advantage s

•

Output Gain Multiplier

•

Programmable Micropro ce ss or In terfa ce

•

208-pin QFP Package

•

Description

The AT76C002 FIR filter contains 16 multiplier-accumulators which enable it to imple­ment a 16th order non-symmetrical FIR filter or a 32nd order symmetrical FIR filter,
operating at 33 MHz. Furthermore, it can be configured to implement a 64th order
filter where the even order coefficients are zero, also running at 33 MHz. The incom­ing samples are 16 bit coded, the coefficients are 12 bit coded and the internal accu­racy is 32 bits.

The AT76C002 contains 16 banks of 2 bit coefficients that can be selected in one
clock cycle. These banks can also be used to perform decimation by 2, 4, 8 or 16
using FIR filters from 32 taps up to 256 taps. In decimation mode, the symmetry
capabilities cannot be used.

In order to implement long FIR filters at the highest frequency (i.e. 33 MHz) the circuit
can be cascaded, with no limits except the internal accuracy. Symmetry properties
can be used in cascade mode. This halves the number of cascaded circuits to imple­ment symmetrical filters.

In order to increase the accuracy of the intermediate results, the AT76C002 includes
an output gain multiplier which enables the whole 12 bit dy namic of the coefficients to
be used. Cascadability cannot be used in decimation mode.

The AT76C002 includes a 16 bit microprocessor interface that can be configured to
be Intel or Motorola compatible.

Applications

High sample rate digital filtering

•

Image process ing

•

Video processing

•

Matrix multiplication

•

Block Diagram

BXP

FXP

CLOCK

RESET

ADR

RD

DATA

WR/DS

CS

Coeffic-

ient

Bank

Control Unit

Configuration

Register

Output Gain

Register

Interface

Decimation

Micro

Control

Timing and

Control

ALU

Register

Register

PRA

Coeffic-

ient

Bank

Backward Delay Line

Forward Delay Line

ALU

Register

Register

Adder Array

Register

Mux

Decimat-

ion

Dual-Port

RAM

Mux

Register

Coeffic-

ient

Bank

Register

0 to

8-bit

Down

Shifter

Mux

ALU

Register

Register

8-bit

Down

Shifter

Register

GAIN

Coeffic-

ient

Bank

Mux

ALU

Register

Register

Register

DOUT

Mux

BXN

FXN

Internal Structur e

FIR Structure

The AT76C002 is built around an array of 16 17x12 multi­plier-accumulators, a forward and a backward delay line
which enable FIR filters of up to 32 taps to be implemented
with odd and even symmetry. FIR filters with interleaved
zeroed coefficients (such as half-band filters) are handled
in an efficient way since a 64 tap half-band symmetrical
FIR can be implemented in only one device.

Coefficient Banks

The AT76C002 contains 16 banks of 12 bit coefficients
that can be selected by writing to an internal register. The
12 bit coefficients are loaded using the 16 bit microproces­sor data bus where the least significant 12 bits are for the
coefficient and the most significant 4 bits are for the ad­dress within the bank. The bank number is selected by
writing to a configuration register.

2 AT76C002

Decimation

Using these coefficient banks, the AT76C002 can imple­ment decimation filters by 2, 4, 8 or 16, the output rate
being 2, 4, 8 or 16 times lower than the input rate. The
value of the decimation is programmed in an internal con­figuration register using the microprocessor interface. Us­ing the SEN Sample Enable input signal, the circuit can
handle a variable incoming data rate.

Cascadability

The ATC76C002 can be cascaded in order to implement
long high-rate FIR filters. Even in a cascaded structure,
the AT76C002 can efficiently handle symmetrical and in­terleaved zeroed coefficient FIR filters, by cascading both
forward and backward delay lines. In that way, a 128 tap
symmetrical FIR filter or a 256 tap symmetrical half-band
FIR filter would only require two cascaded AT76C002 de­vices.

AT76C002

Pin Description

Name Function

V

CC

GND Ground
CLOCK Clock input
CKEN_SYNC Synchronous clock enable input
CKEN Asynchronous clock enable input
RESET Master reset input
ADR 3 bit microprocessor interface input address bus
DATA 16 bit microprocessor interface bidirectional data bus
RD Microprocessor interface read input
WR/DS Microprocessor interface writ e/dat a strobe input
CS Microprocessor interface chip select input
MOTO/

nINTEL
SEN Sample enable input
FXP 16 bit forward delay line input (for cascadability)
FXN 16 bit forward delay line output (for casc adabi li ty)
BXP 16 bit backward delay li ne output (for cas cadability)
BXN 16 bit backward delay line input (for cascadability)
PRA 32 bit intermediate result input bus (for cascadability)
SF 2 bit output configuration input bus
DOUT 32 bit filter output bus
OUT_DEN Output data valid
ENA0 Least significant 16 bit data out enable (active high)
ENA0_N Least significant 16 bit data out enable (active low)
ENA1 Most significant 16 bit data out enable (active high)
ENA1_N Most significant 16 bit data out enable (active low)

Supply voltage

Microprocessor interface confi gurati on sel ec tion input

Arithmetic Precisi o n

The AT76C002 includes several features to tune the dy­namic of the output results. First of all, the 32 bit output of
the FIR structure can be divided by 256 (8 bit down
shifter), divided by 1 to 256 (0 to 8 bit down shifter), and
then bits 23 to 8 of the data can be multiplied by a 10 bit
gain. All features are accessible via the microprocessor
bus. These features are useful in cascade mode be­cause, in long filters, most of the coefficients are very low
compared with the central ones. Consequently, in a cas­cade chain, for a device which implements a part of the
filter with low coefficients, the coefficients can be tuned in
order to use as much as possible the whole 12 bit dy­namic. The result is then re-tuned before being transmit­ted to the next device in the cascade chain.

Microprocessor Interface

The AT76C002 contains a 16 bit microprocessor interface
which can be configured, using the MOTO/nINTEL input,
to have a Motorola or Intel compatible protocol. In Mo­torola mode, the protocol uses CS (Chip Select), DS (Data
Strobe) and RDW (Read/nWrite) signals. In Intel mode,
the protocol uses CS (Chip Select), DS/WR (Write) and
RDWR (Read) signals.

3

Electrical Specifications

0676A/76C002-A-9/96/15M

© Copyright Atmel Corporation 1996.

Atmel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an
Atmel Corporation product. No other circuit patent licenses are implied. Atmel Corporation’s products are not
authorized f or use as c ritical compon ents in life sup port dev ices or s ystems.

Absolute Maximum Ratings

Symbol Parameter Min Max Unit Conditions

I

DC input diode

diode current

output current

output current

outputs shorted

Temperature

temperature

DC supply

voltage

DC input

voltage

DC output

voltage

current

DC output

Continuous

Continuous

Time of

range

Storage

-0.5 5.5 V
VDD +

-0.5

-0.5

0.5V

VDD +

0.5V
10 mA

20 mA

V or see +-IIk

V or see +-IOk

< -0.5V

V

I

V

> VDD + 0.5V

I

< -0.5V

V

O

V

> V

+ 0.5V

O

DD

10 mA Industrial

10 mA Industrial

5sec

-40 +85 C Industrial

-65 +150 C

+-IIk

+-IOk

I

OL

I

OH

V

DD

V

V

O

MAX

MAX

T

SH

T

A

T

SG

Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit Conditions

V

DD

V

I

V

O

T

A

T

R

T

F

DC supply

voltage

DC input

voltage

DC output

voltage

Temperature

range

Input rise time 15 ns

Input fall time 15 ns

4.5 5.0 5.5 V

0 5.0 V

0 5.0 V

DD

DD

V

V

-40 +85 C Industrial
10% - 90%

CMOS

10% - 90%

CMOS

DC Characteristics

Symbol Parameter Min Max Unit Conditions

Input leakage,

I

IH

I

IL

no pullup

Input leakage,

no pullup

-1.0 +1.0

-1.0 +1.0

High-

impedance

I

OZ

output current

-1.0 +1.0

bi-directional

pins

Low level input

V

IL

V

IH

V

OL

V

OH

C

IN

voltage

High level

input voltage

Low level

output voltage

High level

output voltage

Input

capacitance

70%

VDD -

0.5V

30%

V

DD

V

DD

0.5 V I

7pF

VIN = VDD =

µA

µA

µA

V

DD

V

DD

CMOS inputs

V

V

VI

and bi-dir

CMOS inputs

and bi-dir

OL

OH

5.5V

VIN = 0

= 5.5V

= 5.5V

= 5.0 mA

= 5.0 mA

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