Available in a 208-lead PQFP Package and 256-ball BGA Package
•
Power Supplies
– VDDIO 3.3V nominal
– VDDCORE and VDDOSC 1.8V nominal
•
0°C to + 70°C Operating Temperature Range
®
Smart Internet
Appliance
Processor
(SIAP™)
AT75C221
Summary
Description
The AT75C221, Atmel’s latest device in the family of smart internet appliance p roce ssors (SIAP
appliance appl icatio ns such as the Et her net IP phone. Th e AT75C221 is built aroun d
an ARM7TDMI microcontroller core running at 40 MHz with an OakDSPCore coprocessor running at 60 MHz and a dual Ethernet 10/100 Mbits/sec MAC interface.
In a typical standalone IP phone, the DSP handles the voice processing functions
(voice compression, acoustic echo cancellation, etc.) while the dual-por t Ether net
10/100 Mbits/sec MAC interface establishes the connection to the Ethernet physical
layer (PHY) that links the network and the PC. In such an application, the power of the
ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control
tasks.
Atmel provides the A T75C221 with several software modules, including:
•A set of drivers for a Linux
•A comprehensive set of tuna ble DSP algorithms for voice processing, tailored to
be run by the DSP subsystem.
™
), is a high-performance processor de signed for professional inter net
®
kernel capable of driving the embedded peripherals.
6033CS–INTAP–05/04
Pinout
The AT75C221 ships in two alternative packages:
•208-lead PQFP
•256-ball BGA
The product feature s of the 25 6-bal l BG A pack age ar e incre ased com pared to the 2 08-
lead PQFP package.
The features available only with the BGA pac kage ar e:
•The 32-bit wide data bus (In PQFP, only a 16-bit wide data bus is supported.)
•The Parallel I/O lines PA13 to PA18 and PA20 to PA31
VDDIOI/O Lines Power Supply
VDDCOREDevice Core Power Supply
VDDOSCPLL and Oscillator Power Supply
GNDGround
A0-A23Address BusOutput
D0-D31Data BusInput/Output
SDCKSDRAM ClockOutput
DQM0-DQM3SDRAM Byte MasksOutput
SDCSSDRAM Chip Select Output
SDA10SDRAM Address Line 10Output
RASRow Address StrobesOutput
CASColumn Address StrobesOutput
WEWrite EnableOutput
BA0-BA1Bank Address LineOutput
NCE0-NCE3Chip SelectsOutput
NWE0-NWE3Byte Select/Write EnableOutput
NSOEOutput EnableOutput
NWRMemory Block Write EnableOutput
PIO Controller APA0-PA31PIO Controller A I/O Lines Input/Output
PIO Controller BPB0-PB15PIO Controller B I/O Lines Input/Output
TCLK0-TC LK2Timer Counter Clock 0 to 2Input
Timer Counter
Serial Peripheral Interface
TIOA0-TIOA2Timer Counter I/O Line A 0 to 2Input/Output
TIOB0-TIOA2Timer Counter I/O Line B 0 to 2Input/Output
DBW32Ex ternal Data Bus Width for CS0 (1 = 32 bits)Input
ACLKOARM Clock OutputOutput
10
AT75C221 Summary
6033CS–INTAP–05/04
Block Diagram
AT75C221 Summary
Figure 3.
JTAG Debug
Audio Codec
and I/O Lines
AT75C221 Block Diagra m
Interface
MII PHY
Interface
MII PHY
Interface
ICE
Ethernet
10/100 Mbps
MAC Interface
Ethernet
10/100 Mbps
MAC Interface
OSC.
PLL
OakDSPCore
DSP Subsystem
System
Controller
ARM7TDMI MCU Core
ASB/ASB
Bridge
32k Bytes
SRAM
Peripheral Bridge
Boot ROM
External Bus
Interface
SDRAMC
SMC
Peripheral Data
Controller
SPI
16- or 32-bit data
Memory Bus
Serial Peripherals
Boot DataFlash
Interrupt and
Fast Interrupt
I/O Lines
I/O Lines
Advanced
Interrupt
Controller
PIO Controller A
PIO Controller B
USART A
USART B
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Serial Port
Serial Port
PWM Signals
PWM Signals
PWM Signals
6033CS–INTAP–05/04
11
Application Example
M
Figure 4.
DSP Subsystem
32K x 16
Program RAM
Oak Program BusOak Data Bus
2K x 16 X-RAM
Codec Interface
2K x 16 Y-RAM
16K x 16
OakDSPCore
General-
purpose RAM
On-chip
Emulation
Module
256 x 16
Dual-port
Mailbox
Bus Interface Unit
Figure 5.
Network
PC
Speaker
icrophone
Handset
DSP Subsystem
ASB
Application Example Overview: Standalone Ethernet Telephone
Keyboard Screen
Ethernet
10/100 Mbps PHY
Ethernet
10/100 Mbps PHY
Speaker
Phone
Interface
Analog Front End
Voice
Codec
Dual-port
Ethernet
10/100 Mbps
MAC
Interface
Voice
Processing
DSP Subsystem
ARM7TDMI Core
VolP
Protocol
Stack
AT75C221
SDRAM
Controller
External Bus
Interface
SRAM
Controller
SDRAM
Flash
12
AT75C221 Summary
6033CS–INTAP–05/04
Functional
Description
AT75C221 Summary
ARM7TDMI Core
DSP Subsystem
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, c haracterized by a single data and
address bus for instruc tions an d data . The CPU ha s two inst ruction sets: the ARM an d
the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum pe rformanc e. Thumb ins truction s are 16-bit wi de and give m aximum
code density.
Instructions operate on 8-bit, 16-bit and 32-bit data types.
The CPU has seven operating modes. Each operating mode has dedicated banked reg-
isters for fast exception handling. The processor has a total of 37 32-bit registers,
including six status registers.
The AT75C221 DSP subsystem is composed of:
•An OakDSPCore running at 60 MIPS
•2K x 16 of X-RAM
•2K x 16 of Y-RAM
•16K x 16 of General Purpose Data RAM
•32K x 16 of Loadable Program RAM
•One 256 x 16 Dual-port Mailbox
•One Codec Interface
The DSP subsystem is fully autonomous. T he local X- and Y-RAM allow s it to reach its
maximum processing rate , and a local large data RAM enab les complex DSP algorithms to be impl eme nted . T he l ar ge size of the loadable p rogr am RAM pe r mit s the us e
of functions as complex as a low bit-rate vocoder.
Ethernet MAC
During boot time, the ARM7TDMI core has the ability to maintain the OakDSPCore i n
reset state and to uploa d DSP cod e. When the Oa kDSP Core rev erts to an active s tate,
this code is executed.
When the OakDSPC ore is run ning the dua l-port ma ilbox i s used as the c ommunic ation
channel between the ARM7TDMI and the OakDSPCore.
A programmable codec interface is directly connected to the OakDSPCore. It allows the
connection of most industrial voice, multimedia or data codecs.
The AT75C221 features two identi cal Ethernet MACs with the same attribut es as
follows:
•Compatible with IEEE Standard 802.3
•10 and 100 Mbits per Second Data Throughput Capability
•Full- and Half-duplex Operation
•Media Independent Interface to the Physical Layer
•Register Interface to Address, Status and Control Registers
•DMA Interface
•Interrupt Generation to Signal Receive and Transmit Completion
•28-byte Transmit and 28-byte Receive FIFOs
•Automatic Pad and CRC Generation on Transmitted Frames
6033CS–INTAP–05/04
13
•Address Checking Logic to Recognize Four 48-bit Addresses
•Supports Promiscuous Mode Where All Valid Frames are Copied to Memory
•Supports Physical Layer Management through MDIO Interface
The Ethernet MAC is the har dware i mpl em enta tio n of th e MA C su b- layer O SI refe re nce
model between the physical layer (PHY) and the logical link layer (LLC). It controls the
data exchange between a host and a PHY layer according to Ethernet IEEE 802.3u data
frame format. The Ethernet MAC contains the required logic and transmit and receive
FIFOs for DMA m anagement . In addi tion, it is inter faced thr ough MDIO /MDC pins for
PHY layer management. The Ethernet MAC transfers data in media-independent interface (MII).
Peripheral Multiple x ing
on PIO Lines
Power Supplies
System Controller
The AT75C2 21 feat ures tw o PIO Control lers , PIOA a nd PIO B, mul tiple xing I/ O lines of
the peripheral set.
The PIO Controller A m anages 32 I/O lin es, P A0 to PA31, b ut onl y the I/O lines PA0 to
PA12 PA19 and PA22 are available in the 208-lead package.
The PIO Controller B manages only 16 I/O lines, PB0 to PB15, but only the I/O lines
PB0 to PB9 are available in the 208-lead package.
Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O.
The AT75C221 has three types of power supply pins:
•VDDCORE pins power the core, including the ARM7TDMI processor, the DSP
subsystem, the memories and the peripherals; voltage is between 1.65V and 1.95V,
1.8V nominal.
•VDDIO pins power the I/O lines, including those of the External Bus Interface and
those of the peripherals; voltage is between 3.0V and 3.6V, 3.3V nominal.
•VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and
1.95V, 1.8V nominal.
Ground pins are common to all power supplies.
The AT75C221 features a System Controller, which takes care of and controls:
•The Test Mode
•The Reset
•The Clocks of the System
•The Chip Identifier
Memory Controller
14
AT75C221 Summary
The System Controller manages the reset of the entire system and integ rates a clock
generator made up of an oscillator and a PLL.
The AT75C221 architecture is made up of two Advanced System Buses, the ARM ASB
and the MAC ASB. Both handle a single memory space.
The ARM ASB handles the acc ess r equ ests of t he AR M7TD M I and th e PDC. It hand les
also the access reque sts comi ng from the MAC AS B. It connec ts with the Exter nal Bus
Interface, the Peripheral Bridge and the Internal Memories, including the mailbox with
the DSP Subsystem. It also connects with the MAC ASB.
The MAC ASB handles the access requests of the DMAs of both Ethernet MACs. It also
handles the access requests coming from the the ARM ASB. It connects essentially with
the Frame Buffer, but also connects with the ARM ASB.
6033CS–INTAP–05/04
AT75C221 Summary
The major advantage of this double-ASB architecture is that the Ethernet traffic does not
occupy the main ASB bandwidth, ensuring that the ARM7TDMI can perform at its maximum speed while the Ethernet traffic goes through the Frame Buffer.
Boot Program
Peripherals
PDC: Peripheral Data
Controller
The AT75C221 can boot in sev eral wa ys; inclu ding from i nternal boot soft ware and a
hardware connection of Data Flash. When t he ARM7TDMI processor is released fro m
reset, it basically attempts a fetch from address 0x00000000. Depending on the hardware configuration, the memory mapping can be altered and thus modify how the
system boots.
The Peripheral Bridge allows access to the embe dded peripheral user interface s. It is
optimized for low power consumption, as it is built without usage of any clock. However,
any access on the peripheral is performed in two cycles.
The AT75C221 peripherals are design ed to be prog rammed with a minimu m number of
instructions. Each peripheral has 16K bytes of address space allocated in the upper part
of the address space.
The AT75C221 features a six-chan nel Peripheral Data Controller (PDC) dedic ated to
the two on-chip UA RTs and the SPI . One P DC chan nel is c onnected to the re ceivin g
channel and one to the transmitting channel of each UART and of the SPI.
Each PDC channel operates as DMA (Direct Memory Access).
The User Interface of a PDC channel is integ rated i n the me mor y spa ce of eac h peri ph-
eral. It contains a 32-bit address pointer register and a 16-bit count register. When the
programmed number of bytes is transferred, an end- of-transfer signal is sent to the
peripheral and is vi sible in the p erip heral st atus regi ster . This st atus bit mig ht trigge r an
interrupt.
EBI: External Bus
Interface
SDRAMC: SDRAM
Controller
SMC: Static Memory
Controller
The External Bus Interface generates the signals which control access to external memories or peripheral devices. It contains two controllers: the SDRAM Controller and the
Static Memory Controller and mana ges the sh aring of data and address buses between
both controllers.
The SDRAM Controller extends the memory capabilities of a chip by providing the interface to an external 16- or 32-bit SDRAM device. The page size su ppor ts ranges from
2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), halfword (16-bit) and word (32- bit) access es. The maximum addr essable SDRAM size is
256M bytes.
The SDRAM Controller suppor ts a read or wr ite burst length of one location. It keeps
track of the active row in each bank, thus maximizing SDRAM performance, e.g., the
application may be placed in one bank and data in the other banks. So as to optimize
performance, it is advisable to avoid accessing different rows in the same bank.
The SDRAM Controller’s function is to make the SDRAM device acc ess protocol tr ansparent to the user.
The AT75C221 features a S tati c Memor y Cont roll er that e nabl es interfacing with a wide
range of external static memory on peripheral devices, including Flash, ROM, static
RAM, and parallel peripherals.
The SMC provides a gl ueless memory interface to exter nal memory us ing common
address, data bus and dedic ated co ntrol sig nals. The SMC is hig hly progr ammab le and
6033CS–INTAP–05/04
15
has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines.
The SMC supports differ en t ac ce ss proto co ls al lowing single clock-cycle accesses. The
SMC is programme d as an internal peripheral that has a stand ard APB bus in terface
and a set of memory-mapped registers. It shares the external address and data buses
with the SDMC.
AIC: Advanced Interrupt
Controller
PIO: Programmable I/O
Controller
U ART: Universal
Asynchronous Receiver
Transmitter
The AT75C221 integrates an A dv anced Inter rupt Controller (AIC) which is con nected to
the fast interrupt requ est (nF IQ) a nd the stan dard in terr upt requ est ( nIRQ) inputs of th e
ARM7TDMI pro cessor . The proc essor’ s nFIQ lin e can on ly be ass erted by th e exter nal
fast interrupt request input (FIQ). The nIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the two external interrupt request lines, IRQ0 to
IRQ1.
An 8-level priorit y encoder allo ws the user to def ine the priori ty between the differ ent
interrupt sources. Internal sources are p rogrammed to be level-s ensitive or e dge-triggered. Extern al so urces ca n be pro gramm ed to be po sitiv e- or neg ativ e-edge tr igger ed
or high- or low-level sensitive.
The AT75C221 integ rates 24 progr ammab le I/O pins. E ach pin can be programm ed as
an input or an output. Each pin can also generate an interrupt. The programmable I/O is
implemented as two blocks, called PIO A and PIO B, 32 and 16 pins each, respectively.
These pins are used for several functions:
•External I/O for internal peripherals
•Keypad controller function
•General-purpose I/O
The AT75C221 provides two identical full-duplex, Universal Asynchronous Receiver
Transmitters as UART A and UART B. These peripherals sit on the APB bus but are
also connected to the ASB bus (and hence external memory) via a dedicated DMA.
The main features of the UART are:
•Programmable Baud Rate Generator
•Parity, Framing and Overrun Error Detection
•Line Break Generation and Detection
•Automatic Echo, Local Loopback and Remote Loopback Channel Modes
•Interrupt Generation
•Two Dedicated Peripheral Data Controller Channels
•6-, 7- and 8-bit Character Length
•Modem Control Signals
TC: Timer/Counter
16
AT75C221 Summary
The AT75C221 features a timer/counter block which includes three identical 16-bit
timer/counter channels. Each channel can be independently programmed to perform a
wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation.
Each timer/counter channel has thr ee externa l cloc k inputs , five inter nal cl ock in puts,
and two multi-purpose input/output signals that can be configured by the user. Each
channel drives an internal interrupt si gnal that ca n be programme d to generate processor interrupts via the AIC.
The timer/counter block has two global registers which act upon all three TC channels.
The Block Control Reg ister allows the three chan nels to be started sim ultaneo usly with
6033CS–INTAP–05/04
AT75C221 Summary
the same instruction. The Block Mode Register defines the external clock inputs for
each timer/counter channel, allowing them to be chained.
SPI: Serial Peripheral
Interface
The Serial Peripheral Interface circuit is a synchronous serial data link that provides
communication with exter nal devi ces in Maste r or Slave Mode. It als o allows com munication between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data
bits to other SPI's. During a data transfer, one SPI system acts as the “master”' which
controls the data flow, whi le the other system acts as the “s la ve '' wh ic h h as data sh ifte d
into and out of it by the master. Different CPU's can take turn being masters ( Multiple
Master Protocol opposi te to Single Master Protocol whe re one CPU is always the master while all of the others are always slaves), and one master may simultaneously shift
data into multiple slaves. However, only one slave may drive its output to write data
back to the master at any given time.
The main features of the SPI are:
•Four Chip Selects with External Decoder Support Allow Communication with Up to
15 Peripherals
•Serial Memories, such as DataFlash and 3-wire EEPROMs
•Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
•External Coprocessors
•Master or Serial Peripheral Bus Interface
•8- to 16-bit Programmable Data Length Per Chip Select
•Programmable Phase and Polarity Per Chip Select
•Programmable Transfer Delays Between Consecutive Transfers and Between Clock
and Data Per Chip Select
•Programmable Delay Between Consecutive Transfers
•Selectable Mode Fault Detection
•Connection to PDC Channel Capabilities Optimizes Data Transfers
•One Channel for the Receiver, One Channel for the Transmitter
6033CS–INTAP–05/04
17
Orderi ng Information
Table 2 below provides package ordering information for the AT75C221.
Table 2.
Ordering CodePackageOperating Temperature Range
AT75C221-Q208 PQFP2080° to 70° C
AT75C221-C256BGA2560° to 70° C
Ordering Informa tion
18
AT75C221 Summary
6033CS–INTAP–05/04
Mechanical Characteristics and Packaging Information
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Disclaimer:
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errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
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