ATMEL AT75C221 User Manual
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Features
•
ARM7TDMI® ARM® Thumb® Processor Core
– In-Circuit Emulator, 40 MHz operation
•
16-bit Fixed-point OakDSPCore®
– Up to 60 MHz operations
– 104K bytes of Integrated Fast RAM, Codec Interface
•
Ethernet Bridge
– Dual Ethernet 10/100 Mbps MAC Interface
– 16-Kbyte Frame Buffer
•
1 K-Byte Boot ROM, Embedding a Boot Program
– Enable Application Download from DataFlash
•
External Bus Interface
– On-chip 32-bit SDRAM Controller
– 4 Chip Select Static Memory Controller
•
Multi-level Priority, Individually Maskable, Vectored Interrupt Controller
•
Three 16-bit Timer/Counters
•
Two UARTs with Modem Control Lines
•
Serial Peripheral Interfa ce (SPI)
•
Two PIO Controllers, Managing up to 48 General-purpose I/O Pins
•
Supported by a Wide Range of Ready-to-use Application Software
– Multi-tasking Operating System, Networking
– Voice-processing Functions
•
Available in a 208-lead PQFP Package and 256-ball BGA Package
•
Power Supplies
– VDDIO 3.3V nominal
– VDDCORE and VDDOSC 1.8V nominal
•
0°C to + 70°C Operating Temperature Range
®
Smart Internet
Appliance
Processor
(SIAP™)
AT75C221
Summary
Description
The AT75C221, Atmel’s latest device in the family of smart internet appliance p roce ssors (SIAP
appliance appl icatio ns such as the Et her net IP phone. Th e AT75C221 is built aroun d
an ARM7TDMI microcontroller core running at 40 MHz with an OakDSPCore coprocessor running at 60 MHz and a dual Ethernet 10/100 Mbits/sec MAC interface.
In a typical standalone IP phone, the DSP handles the voice processing functions
(voice compression, acoustic echo cancellation, etc.) while the dual-por t Ether net
10/100 Mbits/sec MAC interface establishes the connection to the Ethernet physical
layer (PHY) that links the network and the PC. In such an application, the power of the
ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control
tasks.
Atmel provides the A T75C221 with several software modules, including:
• A set of drivers for a Linux
• A comprehensive set of tuna ble DSP algorithms for voice processing, tailored to
be run by the DSP subsystem.
™
), is a high-performance processor de signed for professional inter net
®
kernel capable of driving the embedded peripherals.
6033CS–INTAP–05/04
Pinout
The AT75C221 ships in two alternative packages:
• 208-lead PQFP
• 256-ball BGA
The product feature s of the 25 6-bal l BG A pack age ar e incre ased com pared to the 2 08-
lead PQFP package.
The features available only with the BGA pac kage ar e:
• The 32-bit wide data bus (In PQFP, only a 16-bit wide data bus is supported.)
• The Parallel I/O lines PA13 to PA18 and PA20 to PA31
• The Parallel I/O lines PB10 to PB16
2
AT75C221 Summary
6033CS–INTAP–05/04
208-lead PQFP Package Pinout
AT75C221 Summary
Table 1.
Pin
Number Signal Name
1 GND 37 MB_TXD0 73 A15 109 RAS
2 SCLKA 38 MB_TXD1 74 A16 110 CAS
3 VDDIO 39 MB_TXD2 75 A17 111 NC
4 FSA 40 GND 76 A18 112 WE
5 STXA 41 MB_TXD3 77 A19B/A0 113 DQM0
6 SRXA 42 MB_TXEN 78 A20/BA1 114 DQM1
7 NTRST 43 MB_TXCLK 79 A21 115 NC
8 MA_COL 44 MB_RXD0 80 D0 116 GND
9 MA_CRS 45 MB_RXD1 81 D1 117 NC
10 MA_TXER 46 MB_RXD2 82 D2 118 VDDCORE
11 MA_TXD0 47 MB_RXD3 83 D3 119 GND
12 MA_TXD1 48 MB_RXER 84 GND 120 VDDOSC
13 MA_TXD2 49 MB_RXCLK 85 D4 121 PLLRC
14 MA_TXD3 50 MB_RXDV 86 VDDIO 122 GND
15 MA_TXEN 51 MB_MDC 87 D5 123 GND
16 VDDIO 52 VDDIO 88 D6 124 XTALOUT
17 MA_TXCLK 53 GND 89 D7 125 XTALIN
18 GND 54 MB_MDIO 90 D8 126 VDDCORE
19 MA_RXD0 55 MB_LINK 91 D9 127 NCE0
20 MA_RXD1 56 A0 92 D10 128 NCE1
21 MA_RXD2 57 A1 93 D11 129 NCE2
22 MA_RXD3 58 A2 94 D12 130 VDDIO
23 MA_RXER 59 A3 95 D13 131 NCE3
24 MA_RXCLK 60 A4 96 D14 132 NWE0
25 GND 61 A5 97 VDDCORE 133 NWE1
26 VDDCORE 62 A6 98 GND 134 NC
27 MA_RXDV 63 A7 99 D15 135 VDDIO
28 MA_MDC 64 A8 100 VDDIO 136 GND
29 MA_MDIO 65 A9 101 GND 137 NC
30 MA_LINK 66 A10 102 VDDIO 138 NWR
31 MB_COL 67 A11 103 NC
32 MB_CRS 68 A12 104 VDDIO 140 GND
33 GND 69 VDDIO 105 GND 141 VDDCORE
34 VDDCORE 70 GND 106 SDCK 142 VDDIO
35 VDDIO 71 A13 107 SDCS 143 MISO
36 MB_TXER 72 A14 108 SDA10 144 MOSI
Pinout for 208-lead PQFP Package
Pin
Number Signal Name
Pin
Number Signal Name
(1)
Pin
Number Signal Name
(1)
(1)
(1)
(1)
(1)
139 NSOE
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Table 1.
Pinout for 208-lead PQFP Package (Continued)
Pin
Number Signal Name
145 SPCK 161 TMS 177 PA5 193 GND
146 PA22 162 TCK 178 PA4 194 PB0
147 VDDIO 163 PA19 179 PA3 195 PB1
148 GND 164 VDDCORE 180 PA2 196 PB2
149 NRST 165 GND 181 PA1 197 PB3
150 FIQ 166 PA12 182 PA0 198 PB4
151 IRQ0 167 GND 183 GND 199 PB5
152 TST 168 VDDIO 184 RXDA 200 PB6
153 GND 169 PA11 185 TXDA 201 PB7
154 VDDCORE 170 PA10 186 NRSTA 202 PB8
155 NC
156 VDDIO 172 PA8 188 NDTRA 204 VDDIO
157 GND 173 PA7 189 NDSRA 205 DBW32
158 VDDIO 174 PA6 190 NDCDA 206 GND
159 TDO 175 VDDIO 191 RXDB 207 BO256
160 TDI 176 NC
(1)
Pin
Number Signal Name
171 PA9 187 NCTSA 203 PB9
(1)
Pin
Number Signal Name
192 TXDB 208 VDDIO
Pin
Number Signal Name
Note: 1. NC pins should be left unconnected.
Figure 1.
208-lead PQFP Package Orientation (Top View)
105156
157
208
152
104
53
4
AT75C221 Summary
6033CS–INTAP–05/04
256-ball BGA Package Pinout
AT75C221 Summary
Table 1.
Pinout for 256-ball BGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 GND B18 TDI D15 VDDIO H20 NSOE
A2 PB9 B19 NC
A3 PB4 B20 NC
(1)
(1)
D16 PA24 J1 MA_TXEN
D17 GND J2 MA_TXD3
A4 PB1 C1 PB10 D18 PA29 J3 MA_TXD2
A5 NDSRB C2 PA28 D19 VDDCORE J4 MA_TXD1
A6 NRSTB C3 DBW32 D20 IRQ1 J17 NWR
A7 RXDB C4 PB6 E1 STXA J18 NWE3
A8 NDSRA C5 PB2 E2 FSA J19 NC
(1)
A9 TXDA C6 NRIB E3 SCLKA J20 NWE2
A10 PA2 C7 NCTSB E4 PA25 K1 MA_RXD0
A11 PA3 C8 NRIA E17 PA30 K2 MA_TXCLK
A12 PA6 C9 NCTSA E18 TST K3 NC
(1)
A13 PA10 C10 PA0 E19 IRQ0 K4 VDDIO
A14 PA13 C11 PA4 E20 NC
(1)
K17 NWE1
A15 PA15 C12 PA8 F1 PB13 K18 NWE0
A16 PA19 C13 PA12 F2 PB12 K19 NCE3
A17 NC
(1)
C14 PA14 F3 SRXA K20 NCE2
A18 PA23 C15 PA18 F4 VDDIO L1 MA_RXD1
A19 TDO C16 PA21 F17 VDDIO L2 MA_RXD2
A20 NC
B1 BO256 C18 NC
B2 PB8 C19 NC
(1)
C17 TCK F18 FIQ L3 MA_RXD3
(1)
(1)
F19 NC
F20 SPCK L17 VDDIO
(1)
L4 MA_RXER
B3 PB7 C20 PA31 G1 MA_COL L18 NCE0
B4 PB3 D1 PB11 G2 PB15 L19 NC
(1)
B5 PB0 D2 PA27 G3 PB14 L20 NCE1
B6 NDTRB D3 PA26 G4 NTRST M1 MA_RXCLK
B7 TXDB D4 GND G17 NRST M2 VDDCORE
B8 NDCDA D5 PB5 G18 PA22 M3 MA_RXDV
B9 NRSTA D6 VDDIO G19 MOSI M4 MA_MDC
B10 PA1 D7 NDCDB G20 MISO M17 PLLRC
B11 PA5 D8 GND H1 MA_TXD0 M18 NC
(1)
B12 PA7 D9 NDTRA H2 MA_TXER M19 XTALOUT
B13 PA11 D10 RXDA H3 MA_CRS M20 XTALIN
B14 VDDCORE D11 VDDIO H4 GND N1 MA_MDIO
B15 PA16 D12 PA9 H17 GND N2 MA_LINK
B16 PA20 D13 GND H18 VDDIO N3 MB_COL
B17 TMS D14 PA17 H19 VDDCORE N4 GND
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Table 1.
Pinout for 256-ball BGA Package (Continued)
Pin Signal Na m e Pin Signal Name Pin S ignal Name Pin Signal Name
N17 GND T20 SDCS V7 A11 W14 D12
N18 DQM3 U1 MB_RXD0 V8 A14 W15 VDDCORE
N19 VDDCORE U2 MB_RXD2 V9 A18 W16 D17
N20 VDDOSC U3 MB_RXCLK V10 A22 W17 D20
P1 MB_CRS U4 GND V11 D2 W18 D24
P2 VDDCORE U5 A1 V12 D6 W19 VDDIO
P3 MB_TXD0 U6 VDDIO V13 D10 W20 NC
P4 MB_TXD3 U7 A8 V14 D14 Y1 NC
P17 RAS U8 GND V15 NC
(1)
Y2 MB_MDIO
(1)
(1)
P18 DQM0 U9 A17 V16 D19 Y3 A2
P19 DQM1 U10 VDDIO V17 D23 Y4 A3
P20 DQM2 U11 D3 V18 D26 Y5 A6
R1 MB_TXER U12 D7 V19 NC
(1)
Y6 A10
R2 MB_TXD1 U13 GND V20 D29 Y7 A13
R3 MB_TXEN U14 D16 W1 MB_MDC Y8 A16
R4 VDDIO U15 VDDIO W2 NC
R17 VDDIO U16 D22 W3 NC
(1)
(1)
Y9 A20/BA1
Y10 A23
R18 SDA10 U17 GND W4 MB_LINK Y11 D0
R19 CAS U18 D27 W5 A5 Y12 D4
R20 WE U19 NC
(1)
W6 A9 Y13 D8
T1 MB_TXD2 U20 D30 W7 A12 Y14 D11
T2 MB_TXCLK V1 MB_RXD3 W8 A15 Y15 D13
T3 MB_RXD1 V2 MB_RXDV W9 A19/BA0 Y16 D15
T4 MB_RXER V3 NC
(1)
W10 A21 Y17 D18
T17 D28 V4 A0 W11 D1 Y18 D21
T18 D31 V5 A4 W12 D5 Y19 D25
T19 SDCK V6 A7 W13 D9 Y20 NC
(1)
Note: 1. NC Balls should be left unconnected.
6
AT75C221 Summary
6033CS–INTAP–05/04
AT75C221 Summary
Figure 2.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
256-ball Package Orientation (Top View)
1
2
3
4
5
6
7
8
9
1011121314151617181920
6033CS–INTAP–05/04
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