ATMEL AT750B User Manual
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Features
•
Advanced, High-Speed Programmable Logic Device-Superset of 22V10
– Improved Performance - 7.5 ns tPD, 95 MHz External Operation
– Enhanced Logic Flexibility
– Backward Compatible with ATV750/L Software and Hardware
•
New Flip-Flop Features
– D- or T-Type
– Product Term or Direct Input Pin Clocking
•
High-Speed Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
Device ICC, Stand-By
ATV750B 125 mA
High-Speed
UV-Erasable
ATV750BL 15 mA
•
Highest Density Programmable Logic Available in a 24-Pin Package
•
Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-Flops
•
Enhanced Output Logic Flexibility
– All 20 Flip-Flops Feed Back Internally
– 10 Flip-Flops are Also Available as Outputs
•
Full Military, Commercial and Industrial Temperature Ranges
Logic Diagram
Description
The ATV750Bs are twice as powerful as mos t other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into mo re usable g ates. High-s peed logic and unifor m, predict able delays
guarantee fast in-system performance.
Programmable
Logic Device
ATV750B
Pin Configurations
Pin Name Function
CLK Clock
IN Logic Inputs
I/O Bidirectional Buffers
* No Internal Connection
V
CC
+5V Supply
(continued)
DIP/SOIC PLCC/LCC
Rev. 0301D–05/98
T op Vie w
1
Each of the ATV750B’s 22 logic pi ns can be us ed as an
input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each fl ip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms avai lable. A va riable format is used to assign between four to eight product terms
per sum term. There are two sum terms per output, provi ding added flexibility. Much more logic can be replaced by
this device than by any other 24-pin PLD. Wi th 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Abosute Maximum Rating*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
Integrated UV Erase Dose..............................7258 W•sec/cm
(1)
(1)
(1)
2
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking.
Each output has i ts o wn ena ble p roduct term. One produc t
term provides a com mon synchron ous preset for a ll flipflops. Registe r prel oad fun ctions are pr ovided t o simp lify
testing. All registers automatically reset upon power up.
The ATV750BL is a low power device with speeds as fast
as 15 ns. The ATV750BL pr ovides the optimu m low power
PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing battery-powered operation.
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d
functional oper ation of the device at these o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .
Note: 1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maximum output pin v ol tage is V
may o versh oot to +7.0V f or pulse s of less than 20
ns.
+ 0.75V DC which
CC
Logic Options
Combinatorial Output Registered Output
Combined T erms Separate Terms
Combined T erms Separate Terms
2
ATV750B
Clock MUX
Output Options
CLOCK
PRODUCT
TERM
CKi
CLK
PIN
ATV750B
CKMUX
TO
LOGIC
CELL
SELECT
DC and AC Operating Conditions
Operating Temperature (Case) 0°C - 70°C 0°C - 70°C -40°C - 85°C -55°C - 125°C
V
Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%
CC
Note: 1. See ordering information for valid speed and temperature combination.
(1)
Commercial
-7, -10, -15
Commercial
-25 Industrial Military
3
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
LI
I
LO
I
CC
(1)
I
OS
Input Load Current VIN = -0.1V to VCC + 1V 10 µA
Output Leakage
Current
= -0.1V to VCC + 0.1V 10 µA
V
OUT
Com. 125 180 mA
B-7, -10
Ind.,Mil. 125 190 mA
Po wer Supply
Current, Standby
CC
V
= MAX,
IN
Outputs Open
B-15, -25
Com. 125 180 mA
Ind.,Mil. 125 190 mA
V
= MAX,
Com. 15 30 mA
BL-15
Ind.,Mil. 15 30 mA
Output Short
Circuit Current
= 0.5V -120 mA
V
OUT
V
IL
V
IH
V
OL
V
OH
Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V
Input High Voltage 2.0 V
= 16 mA Com.,Ind. 0.5 V
I
Output Low
Voltage
Output High
Voltage
VIN = VIH or VIL,
V
= MIN
CC
VIN = VIH or VIL,
= MIN
V
CC
OL
I
= 12 mA Mil. 0.5 V
OL
I
= 24 mA Com. 0.8 V
OL
IOH = -100 µAV
I
= -4.0 mA 2.4 V
OH
- 0.3 V
CC
+ 0.75 V
CC
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and
Output Test Load
Measurement Levels
tR, tF < 3 ns (10% to 90%)
4
ATV750B
ATV750B
AC Waveforms, Product Term Clock
(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock
(1)
-7 -10 B/BL-15 B/BL-25
Symbol Parameter
t
PD
t
EA
t
ER
t
CO
t
CF
t
S
t
SF
t
H
t
P
t
W
Input or Feedback to
Non-Registered Outpu t
7.5 10 15 25 ns
Input to Output Enable 7.5 10 15 25 ns
Input to Output Disable 7.5 10 15 25 ns
Clock to Output 3 7.5 4 10 5 12 6 20 ns
Clock to Feedback 1 5 4 7.5 5 9 5 10 ns
Input Setup Time 3 4 8/12 14 ns
Feedback Setup Time 3 4 7 7 ns
Hold Time 1 2 5/7 5/7 ns
Clock Period 7 11 14 17 ns
Clock Width 3.5 5.5 7 8.5 ns
External Feedback 1/(tS+tCO) 95 71 50/41 29 MHz
UnitsMin Max Min Max Min Max Min Max
F
MAX
t
AW
t
AR
t
AP
t
SP
Internal Feedback 1/(t
No Feedback 1/(t
) 142 90 71 58 MHz
P
) 125 86 62 58 MHz
SF+tCF
Asynchronous Reset Width 5 10 15 20 ns
Asynchronous Reset
Recovery Time
Asynchronous Reset to
Registered Output Reset
Setup Time, Synchronous Preset 4 7 8 15 ns
Note: 1. See ordering information for valid part numbers.
31015 20 ns
812 1525ns
5
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