ATMEL AT6003-4QI, AT6003-4QC, AT6003-4JI, AT6003-4JC, AT6003-4AI Datasheet
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Features
High Performance
•
System Speeds > 100 MHz
Flip-Flop Toggle Rates > 250 MHz
1.2 ns/1.5 ns Input Delay
3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
•
Thousands of Registers
•
Cache Logic® Design
•
Complete/Partial In-System Reconfiguration
No Loss of Data or Machine State
Adaptive Hardware
Low Voltage and Standard Voltage Operation
•
5.0 (V
3.3 (V
Automatic Component Generators
•
Reusable Custom Hard Macro Functions
Very Low Power Consumption
•
Standby Current of 500 µA/ 200 µA
Typical Operating Current of 15 to 170 mA
Programmable Clock Options
•
Independently Controlled Column Clocks
Independently Controlled Column Resets
Clock Skew Less Than 1 ns Across Chip
Independently Configurable I/O (PCI Compatible)
•
TTL/CMOS Input Thresholds
Open Collector/Tri-state Outputs
Programmable Slew-Rate Control
I/O Drive of 16 mA (combinable to 64 mA)
Easy Migration to Atmel Gate Arrays for High Volume Production
•
= 4.75V to 5.25V)
CC
= 3.0V to 3.6V)
CC
AT6000/LV Series
Coprocessor
Field
Programmable
Gate Arrays
Description
AT6000 Series SRAM-Based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic®, which provides the
user with the ability to implement adaptive hardware and perform hardware acceleration.
The patented AT6000 S eries architecture employs a symmetrical grid of small yet
powerful cells connected to a fl exible busing network. Independently controlled clocks
and resets gover n every column of cells. T he ar ray is su rrounded by programmable
I/O.
(continued)
AT6000 Series Field Programmable Gate Arrays
Device AT6002 AT6003 AT6005 AT6010
Usable Gates 6,000 9,000 15,000 30,000
Cells 1,024 1,600 3,136 6, 400
Registers (maximum) 1,024 1,600 3,136 6, 400
I/O (maximum) 96 120 108 204
Typ. Operating Current (mA) 15-30 25-45 40-80 85-170
Cell Rows x Columns 32 x 32 40 x 40 56 x 56 80 x 80
AT6000 and AT6000LV Series
0264E
2-3
Description
(Continued)
Devices range in size from 4,000 to 30,000 usable gates,
and 1024 t o 6400 registe rs. Pin locations ar e consistent
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
AT600 0 Series F PGAs utili ze a re liable 0. 6 µm singlepoly, double-metal CMOS process and are 100% factorytested.
Atmel’s PC- and workstation-based Integrated Development System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small s ize leads t o arrays with large numbers o f cel ls,
greatly multiplying the functionali ty in each cel l. A simple,
high-speed busing networ k provides fast, efficient communication over medium and long distances.
Figure 1.
Symmetrical Array Surrounded by I/O
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array of identical cells (Fig ure 1). The array is continuous
and completely unint errupt ed from one edge to the other,
except for bus
2).
In addition to logic and storage, cells can also be used as
wires to connect functions together over short distances
and are useful for routing in tight spaces.
repeaters
spaced every eight cells (Figure
The Busing Network
There are two kinds of buses: local and express (see Figures 2 and 3).
Local buses are the link between the array of cells and the
busing network. There are two local buses— North-South
1 and 2 (NS1 and NS2)— for every column of cells, and
two local buses— East-West 1 and 2 (EW1 and EW2)—
for every row of cells. In a sector (an 8 x 8 array of cells
encl osed by rep eaters) e ach local bus is conne cted to
every cell in its column or row, thus providing every cell in
(continued)
2-4
AT6000/LV Series
Figure 2. Busing Network (one sector)
AT6000/LV Series
CELL
REPEATER
Figure 3. Cell-to-Cell and Bus-to-Bus Connections
2-5
Descr i pti on
(Continued)
the array with read/write access to two North-South and
two East-West buses.
Each cell, in addition, provides the ability to route a signal
on a 90° turn between the NS1 bus and EW1 bus and
between the NS2 bus and EW2 bus.
Express buses a re not connec ted directly t o cells, and
thus provide higher speeds. They are the fastest way to
cover long, straight-line distances within the array.
Each express bus is pa ired with a local bus, so there are
two ex press buses for eve ry colum n and two ex press
buses for every row of cells.
Conne ctive units, called r epeaters, spaced e very eight
cells, divide each bus, both local and express, into segments spanning eight cells. Repeaters are aligned in rows
and columns thereby partitioning the array into 8 x 8 sectors of cells. Each repeater is associated with a local/express pair, and on each side of the repeater are connections to a local-bus segment and an express-bus segment.
The repeater can be prog rammed to provide an y one of
twenty-one connecting functions. These functions are
symmetric with respect to both the two repeater sides and
the two types of buses.
Among the functions provided are the ability to:
• Isolate bus segments from one another
• Connect two local-bus segments
• Connect two express-bus segments
• Implement a local/express transfer
In all of these cases, each connect ion pr ovid es signal regene ration and is thu s unidi rectio nal. For bidi rect ional
connections, the basic repeater function for t he N S2 and
EW2 repeaters is augmented with a special programmable conne ction allowing bidirectiona l communication between local-bus segments. This option is primarily used to
implement long, tri-state buses.
Figure 4. Cell Structure
The Cell Structure
The Atmel cell (Figure 4) i s simple and small and yet can
be pr ogrammed to perform all the logic an d wiring functions needed to implement any digital circuit. Its four sides
are functionally identical, so each cell is completely symmetrical.
Read/write access to the four local buses— NS1, EW1,
NS2 and EW2— is controlled, in part, by four bidirectional
pass gates co nnected directly to the buses. To read a local bus, the pass gate for that bus is turned on and the
three-input multiplexer is set accordingly. To write to a local bus, the pass gate for that bus and the pass gate for
the associated tri-state driver are both turned on. The twoinput multiplexer supplying the control signal to the drivers
permits either: (1) active drive, or (2) dynamic tri-stating
controlled by the B input. Turning between L
or between L
NS2
and L
is accomplished by turning on
EW2
the two associated pass gates. The operations of reading,
writing and tur ning are subject to the restriction that e ach
bus can be involved in no more than a single operation.
In addition to the fo ur local-bu s connections, a cell receives two inputs and provides t wo outputs to each of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B.” There is an A input and a B input from each neighboring cell and an A output and a B out put driving all four
nei ghbor s. Be twee n cell s, a n A ou tput is alway s connected to an A input and a B output to a B input.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers.
Cell flexibility is enhanced by allowing each multiplexer to
select also the logical constant “1.” The two multiplexer
outputs enter the two upstream AND gates.
Downstream from these two AND gates are an ExclusiveOR (XOR) gate, a register, an AND gate, an inve rter a nd
two four-input multiplexers producing the A and B outputs.
These multiplexers are co ntroll ed in tandem (unli ke the A
and B input multiplexers) and determine the function of the
cell.
• I n State 0— correspond ing to the “0" inputs of the mul-
tiplexers— the output of the left-hand upstream AND
gate is connected to the cel l’s A output, and the out put
of the right-hand upstream AND gate is connected t o
the cell’s B output.
• I n State 1— correspond ing to the “1" inputs of the mul-
tiplexers— the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
• I n State 2— correspond ing to the “2" inputs of the mul-
tiplexers— the XOR of the outputs from the two upstream AND gates is provided to the cell’s A output,
and L
NS1
(continued)
EW1
2-6
AT6000/LV Series
AT6000/LV Series
Figure 5a. Comb ina torial Ph y s ical Sta te s
L
i
A, L
o
A
L
i
A, L
o
L
i
A, L
o
L
i
A, L
o
BB
BABBA
B
B
B
BA
B
A, L
A, L
A, L
A, L
L
o
L
i
o
L
o
o
A
i
BB
A, L
o
L
i
B
A, L
o
BB A
L
A, L
i
o
i
B
L
BA
B
A, L
B
i
B
o
A, L
A
A, L
A, L
A, L
L
i
o
L
i
o
L
i
o
L
i
o
Figure 5b. Register States
A
A
L
i
B
BA
B
A, L
A
A, L
A, L
A, L
o
L
o
L
1BA0
B
B
i
B
o
BA
L
i
B
i
o
B
Figure 5c. Physical Constants
"0" "0"
A, L
o
B
"0" "1"
o
"1" "0"
B
A, L
B
o
Figure 6a. Two -Input AND Feeding XOR
A
BL
i
A
Figure 6b. Cell Configuration (A•L) XOR B
"1" "1"
A, L
o
BA, L
D
Q
A, L
o
A
L
D
Q
A, L
A
D
Q
A, L
"0"
i
o
B
o
B
B
B
D
Q
A, L
o
L
i
D
Q
A, L
D
Q
A, L
B
BA
L
i
D
Q
A, L
A, L
o
BA
B
o
A, L
B
o
L
i
D
Q
o
BA
L
i
D
Q
B
o
D
Q
A, L
o
1
D
Q
A, L
B
B
L
i
0
o
2-7
Description
(Continued)
while the NAND of these two outputs is provided to the
cell’s B output.
In State 3— corresponding to the “3" inputs of the mul-
•
tiplexers— the XOR function of State 2 is provided t o
the D input of a D-type flip-flop, the Q output of which is
connected to t he cell’s A o utput. Clock and asyn chronous reset signals are supplied externally as described
later. The AND of the out puts f rom the two upstream
AND gates is provided to the cel l’s B output.
Logic St ate s
The Atmel cell implements a rich and powerful set of logic
functions, stemming from 44 logical cell states which permutate into 72 physical states. Some states use both A
and B inputs. Other states are created by selecting the “1"
input on either or both of the input multiplexers.
Ther e are 28 com binator ial primitive s created fr om the
cell’s tri-state capabilities and the 20 physical states represented in the Figure 5a. Five logical primitives are derived
from the physical constants shown in Figure 5c. More
complex functions are creat ed by using cells in combination.
A two-input AND feeding an XOR (Figure 6a) is produced
using a single cell (Figure 6b). A two-to- one multiplexer
selects the logical constant “0" and feeds it to the righthand AND gate. The AN D gate acts as a feed-through,
letting the B input pass through to t he XOR. The three-toone multiplexer on the right side select s the local-bus input, L
and L
put of the AND gate fee ds int o the XOR, producing the
logic state (A•L) XOR B.
Figure 7.
, and passes it to the left-hand AND gate. The A
NS1
signals are the inputs to the AND gate. The out-
NS1
Column Clock and Column Reset
GLOBAL
CLOCK
EXPRESS
BUS
EXPRESS
BUS
GLOBAL
RESET
"1"
CELL
CELL
CELL
CELL
"1"
A
D
Q
D
Q
D
Q
D
Q
A
D
E
D
I
C
A
T
E
D
R
B
O
U
U
R
T
I
I
E
N
D
G
GLOBAL
CLOCK
EXPRESS
BUS
EXPRESS
BUS
GLOBAL
RESET
Clock Di str ibu tio n
Along the to p edge of the array is logic for d istributing
clock signals to the D flip-flop in each logic cell (Figure 7).
The distributi on net work is organized by column and per mits columns of cel ls to be independently clocked. At the
head of each column is a user-configurable multiplexer
providing the clock signal for that column. I t has four inputs:
Global clock supplied through the CLOCK pin
•
Express bus adjacent to the di stribution logic
•
“A” output of the cell at the head of the column
•
Logical constant “1" to conserve power (no clock)
•
Through the global clock, the network pr ovides low-skew
distribution of an externally supplied clock to any or al l of
the columns of the array. The global clock pin is also connected directly to the array via the A input of the upper left
and right corner cells (AW on the left, and AN on t he right).
The express bus is useful in distributing a secondary clock
to multiple columns when the global clock line is used as
a prim ary clock. The A output of a cell is useful in providing
a clock signal to a single column. The constant “1" is used
to reduce power dissipation in columns using no registers.
Asynchronous Reset
Along the bottom edge of the array is logic for asynchronously resetting the D flip-flops i n the logic cell s (Figure 7).
Like the clock network, the asynchronous reset network is
or ganized by column and per mits col umns to be independently reset. At the bottom of each column is a userconfigurable multiplexer providing the reset signal for that
column. It has four inputs:
Global asynchronous reset supplied through the
•
RESET pin
Express bus adjacent to the di stribution logic
•
“A” output of the cell at the fo ot of the column
•
Logical constant “1"to conserve power
•
The asynchronous reset logic uses these f our inputs in the
same way that the clock distribution logic does. Through
the global asynchronous reset, any or all columns can be
reset by an ext ernally supplied signal. The global asynchronous reset pi n is also connected directly to t he ar r ay
via the A input of the lower left and right corne r cells (AS
on the left, and AE on the right) . The e x press bus can be
used to distribute a seconda ry reset to m ultiple columns
when the gl obal r eset line is used as a primary reset, the
A output of a cell can also provide an asynchronous reset
signal to a single column, and the constant “1" is used by
columns with registers r equi ring no reset. All r egister s are
reset during power-up.
(continued)
2-8
AT6000/LV Series
AT6000/LV Series
Description
(Continued)
Input/Output
The Atme l architecture pr ovides a flexi ble interface between the logic array, t he configuration cont rol logic and
the I/O pins.
Two adjacent cells— an “exit” and an “entrance” cell— on
the perimeter of the logic array are associated with each
I/O p in .
There are two types of I/Os: A-type (Figure 8a) and B-type
(Figure 8b). For A-type I/Os, the edge-facing A output of
an exit cell is connected to an output driver, and the edgefacing A input of the adj acent entrance cell i s connected to
an input buffer . The output of t he output driver and t he
input of the input buffer are connected to a common pin.
B-type I/Os are the same as A -type I/Os, but use the B
inputs and outputs of their respective entrance and exit
cells. A- and B-type I/ Os alter nate around the array.
Control of the I/O logic is provided by user- confi gurable
me mo ry b it s .
TTL/CMOS Inputs
A user-configurable bit det erm ines the threshold level—
TTL or CMOS— of t he input buffer.
Open Collector/Tri-state Outputs
A user-configurable bit which enables or disables the active pull-up of the output device.
Slew Rate Control
A user- configurabl e bit controls th e slew rat e— fast or
slow— of the output buffer . A slow slew rate, which reduces noise and ground bounce, is recommended for out-
puts that are not speed-critical. Fast and slow slew rates
have the sam e DC-curr ent sinki ng capabil it ies, but th e
rate at whi ch each allows the output devices to reach full
drive differs.
Pull-up
A user-configurable bit controls the pul l-up t ransistor i n the
I/O pin. It’s primary functi on is to provide a logical “1" t o
unused input pins. When on, it is approximately equivalent
to a 25K resistor to VCC.
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static - - always on
or always off - - or dynamically controlled by a signal generated i n the array. Four options ar e available from the
array: (1) the control is l ow and always dr iving; (2) the control is high and n ever d riving; (3) the control i s connect ed
to a vertical local bus associated with the output cell; or (4)
the control is connected to a horizontal local bus associated with the output cell. On power-up, the user I/Os are
configured as inputs with pull-up resistors.
In addition to the functionality provided by the I/O logic, the
entrance and exit cell s pr ovide the abil ity t o r egist er bot h
inputs and outputs. Also, t hese perimeter cells (u nlike interior cells) are conn ected directly to express buses: t he
edge-facing A and B outputs of the entrance cell are connected to express buses , as are the edge-facing A and B
inputs of the exit cell. These buse s are per pendicular to
the edge, and provide a rapid means of bringing I /O signals to and from the array interior and the opposite ed ge
of the chip.
Figure 8a. A-Type I/O Logic
Figure 8b. B-Type I/O Logic
2-9
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