ATMEL AT49LV8192T-20TI, AT49LV8192T-20TC, AT49LV8192T-20RI, AT49LV8192T-20RC, AT49LV8192T-15TI Datasheet

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Features

•

Low Voltage Operation

–2.7V Read – 5V Program/Erase

•

Fast Read Access Time - 120 ns

•

Internal Erase/Program Control

•

Sector Architecture

– One 8K Words (16K bytes) Boot Block with Programming Lockout – Two 8K Words (16K bytes) Parameter Blocks – One 488K Words (976K bytes) Main Memory Array Block

•

Fast Sector Erase Time - 10 seconds

•

Word-By-Word Programming - 30 µs/Word

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low Power Dissipation

– 25 mA Active Current –50 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

Description

The AT49BV8192 a nd A T49LV8 192 a re 3 -volt, 8-m egabit Fl ash Memori es org aniz ed as 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, t he d ev ices of fer acc es s tim es to 120 ns with power di ss ipati on of just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50

(continued)

Pin Configurations

Pin Name Function

A0 - A18 Addresses CE

Chip Enable

8-Megabit (512K x 16) CMOS Flash Memory

AT49BV8192 AT49BV8192T AT49LV8192 AT49LV8192T

OE WE

Output Enable Write Enable

RESET Reset

I/O0 - I/O15

Program/Erase Power Supply

Data Inputs/Outputs

NC No Connect

TSOP Top View

Type 1

A15 A13

A11

RESET

VPP

A17

A6 A4

A14 A12 A10

A18

A7 A5 A3 A1

16 18

19 I/O8

SOIC (SOP)

VPP

1 2

A18 A17

8 9

NC I/O15

I/O14

I/O13 I/O12 VCC I/O3

I/O2 I/O1 I/O0

GND A0

A16 GND

I/O7 I/O6 I/O5 I/O4

I/O11 I/O10 I/O9

OE CE

3217

GND

OE I/O0 I/O8

I/O1 I/O9 I/O2

I/O10

I/O3

I/O11

15 16 17 18 19 20 21 22

RESET

A10

A11

A12

A13

A14

A15

A16

GND

32 31

I/O15

I/O7

I/O14

I/O6

I/O1327 I/O5

I/O1225 I/O4

VCC23

0978B-A–11/97

The device contains a u se r-e nabl ed “ boo t b lock ” pr ote ct ion feature. Two versions of the feature are available: the AT49BV/LV8192 locates the boot block at lowest or der addresses (“bottom boot ”); the AT49 BV/LV 8192T locate s it at highest order addresses (“top boot”)

To allow for simple in-system reprogrammability, the AT49BV/LV8192 does not require high input voltages for programming. Reading data out of the device i s similar to reading from an E PROM ; it h as stan dard CE

, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV8192 is perfor med by first erasing a block of data and then programming on a word-by-word basis.

The device is erased by executing the erase command sequence; the device internally controls the erase operation. The memory is di vided into three bl ocks for erase operations. There are two 8K word parameter block sections and one sector consisting of the boot block and the

Block Diagram

V V

GND

RESET

ADDRESS

INPUTS

CC PP

CONTROL

LOGIC

Y DECODER

X DECODER

AT49BV/LV8192 AT49BV/LV8192T

DATA INPUTS/OUTPUTS

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES Y-GATING

MAIN MEMORY (488K WORDS)

PARAMETER

BLOCK 2

8K WORDS

PARAMETER

BLOCK 1

8K WORDS

BOOT BLOCK

8K WORDS

main memory array block. T he AT49BV/LV8192 is programmed on a word-by-word basis.

The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot bl ock cannot be cha nged when input levels of 3.6 volts or less are used. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming lock o ut featur e to pro vide data i ntegrity. The boot sector is des igned to contain us er secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed.

During a chip erase, sector erase, or word programming, the V

pin must be at 5V ± 10%.

DATA INPUTS/OUTPUTS

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

7FFFF 7FFFF

06000

05FFF 04000

03FFF

02000

01FFF 00000 00000

Y-GATING

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

8K WORDS

PARAMETER

BLOCK 2

8K WORDS

MAIN MEMORY (488K WORDS)

7E000

7DFFF 7C000

7BFFF

7A000

79FFF

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs . The outputs ar e put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Comma nd Definitions ta ble (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low

The AT49BV/LV8192 is access ed l ike an E PRO M .

and OE are low and WE is high, th e data sto red

or OE is high. This dual-line

When the device is first pow-

AT49BV/LV8192(T)

pulse on the WE tively) and OE edge of CE latched by the first rising edge of CE

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard microprocessor write timings are used. The ad dress loca tions used in the command sequences are not affected by entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is provided to eas e some sys-

is at a l ogic high le ve l, t he device is in its sta nda rd ope ra tin g mo de. A lo w level on the RESET

input halts the pre sent d evice o perati on and puts the outputs of the de vice in a hig h impeda nce sta te. When a high level is reas serted on the RESE T

pin, the device returns to the Read or Standby mo de, dependi ng upon the state of the control inputs. By applying a 12V ± 0.5V input

AT49BV/LV8192(T)

signal to the RESET grammed even if the boot block program lockout feature has been enabled (see Boot Block Pro gramming Loc kout Override section).

ERASURE:

be erased. The erased state of memory bits is a logical “1”. The entire devi ce can be e rased by using the Chip Erase command or indiv idual sect ors can be er ased by us ing the Sector Erase commands.

CHIP ERASE:

time by using the 6-byte chip erase software code. After the chip erase h as b een i ni tia ted, th e dev ice wi ll i nte rn all y ti me the erase operation so that no external clocks are required. The maximum time to erease the chip is t

If the boot block lockout ha s b een ena bled, th e Chip Era se will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, th e d ev ice will return to the r ea d or s tand by mode.

SECTOR ERASE:

the device is organized into three sectors that can be individually erased. There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array blo ck. The Secto r Erase comm and is a six bus cycle operation. The sector address is latched on the falling WE input command is latched at the rising edge of WE sector erase starts after the rising edge of WE cycle. The erase oper ation is internal ly controlled; it will automatically time to c omple tion. W hen the b oot block programming lockout featur e is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). Once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued.

WORD PROGRAMMING:

erased, it is programmed (to a logical “0”) on a word-byword basis. Programming is accomplished via the internal device command register and is a 4 bus cycle operation. The device will autom ati ca ll y ge nerate the required inter nal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING L OCKOUT:

has one designated block that has a programming lockout feature. This feature prevents programmi ng of data in the designated block once the feature has been enabled. The

Before a word can be reprogrammed, it must

pin the boot block array can be repro-

The entire device can be erased at one

As an alternative to a full chip erase,

edge of the sixth cycle while the 30H data

. The

of the si xth

Once a memory block is

cycle time. The DATA poll ing feat ure may

The device

size of the block is 8K words . This bl ock, re ferre d to as the boot block, can contain secure code that is used to bring up the system. Enablin g the l ockout fe ature will allow t he boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’ s u sa ge a s a write protected region is optional to the user. The address range of the 49BV/LV8192 boot block is 00000H to 01FFFH while the address range of the 49BV/LV8192T is 7E000H to 7FFFFH.

Once the feature is enabl ed, the da ta in the bo ot block c an no longer be erased or programmed when input levels of

5.5V or less are u sed. Dat a in the m ain mem ory bloc k can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H wil l s how i f pr ogram mi ng the b oot block is locked out. If the data on I/O0 is low, the boot bl oc k c an be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the bl ock ca nnot be programmed. The software product identification exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boot block programming lockout by ta king the RES ET entire chip eras e, s ecto r era se or wor d pr ogramm ing oper ation. When the RESET the boot block programming lockout feature is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the c omple ment of t he load ed data on I/O7 . Once the program cycle has been completed, true data is valid on all output s and the next c ycle ma y begin . Duri ng a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA polling may begin at any time during the program cycle.

The AT49BV/LV8192 features DATA

pin to 12 volts during the

pin is brought back to T TL levels

The product identif ication

A software

TOGGLE BIT:

In addition to DATA

polling the AT49BV/LV8192 provides another method for determining the end of a program or erase cycle. Dur ing a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examini ng the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs to the AT49BV/LV8192 in the followin g ways: (a) V

is below 1.8V (typical), th e program func tion is inhib-

sense: if

ited. (b) V

sense level, the device will automatically time out 10

power on delay: once VCC has reached the

ms (typical) before pr ogramm ing. (c) Prog ram inhib it: hold ing any one of OE

low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program

cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, th e address inp uts and con trol inputs (OE

, and WE) may be driven from 0 to 5.5V without

CE adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V

+ 0.6V.

AT49BV/LV8192(T)

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