ATMEL AT49LV1614AT-70TI, AT49LV1614AT-70CI, AT49LV1614A-70TI, AT49LV1614A-70CI, AT49BV1614AT-90TI Datasheet

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Features

• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

• AccessTime–70ns

• Sector Erase Architecture

– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout – Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

• Fast Word Program Time – 20 µs

• Fast Sector Erase Time – 300 ms

• Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word and Seven 32K Word Sectors Memory Plane B: Twenty-four 32K Word Sectors

• Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

• Low-power Operation

–30mAActive – 10 µA Standby

• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

• VPP Pin for Accelerated Program/Erase Operations

• RESET Input for Device Initialization

• Sector Lockdown Support

• TSOP and CBGA Package Options

• Top or Bottom Boot Block Configuration Available

• 128-bit Protection Register

16-megabit (1Mx16/2Mx8) 3-volt Only Flash Memory

AT49BV1604A AT49BV1604AT

Description

The AT49BV/LV16X4A(T) is a 2.65- to 3.3-volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for erase operations. The device is offered in 48-lead TSOP and 48-ball CBGA packages. The device has CE contention. This device can be read or reprogrammed using a single 2.65V power supply, making it ideally suited for in-system programming.

and OE control signals to avoid any bus

Pin Configurations

Pin Name Function

A0 - A19 Addresses

RESET

RDY/BUSY

VPP Power Supply for Accelerated Program/Erase Operations

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1) I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

BYTE

NC No Connect

VCCQ Output Power Supply

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Selects Byte or Word Mode

AT49BV1614A AT49LV1614A AT49BV1614AT AT49LV1614AT

Rev. 1411F–FLASH–03/02

A15 A14 A13 A12 A11 A10

RESET

VPP

A19 A18 A17

TSOP Top View

CBGA Top View (Ball Down)

1 2 3 4 5 6 7

11 12 13 14

15 16 17 18

A16

VCCQ

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49BV1604A(T)

234567

A11

A13

A14

A15

A16

VCCQ

GND

A10

A12

I/O14

I/O15

I/O7

I/O5

I/O6

I/O13

VPP

RST

I/O11

I/O12

I/O4

A18

I/O2

I/O3

VCC

A19

A17

I/O8

I/O9

I/O10

I/O0

I/O1

GND

A15 A14 A13 A12 A11 A10

A19

RESET

VPP*

NC*

RDY/BUSY

A18 A17

TSOP Top View

Type 1

1 2 3 4 5 6 7

9 10

11 12 13 14 15 16 17 18

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49BV/LV1614A(T)

CBGA Top View

A17

I/O0

I/O8

I/O9

I/O1

VSS

3456

RDY/BUSY

NC*

A18

I/O2

I/O10

I/O11

I/O3

RESET

VPP*

A19

I/O5

I/O12

VCC

I/O4

A10

A11

I/O7

I/O14

I/O13

I/O6

I/O15/A-1

A13

A12

A14

A15

A16

BYTE

VSS

Note: *For the AT49BV/LV1614A(T), either pin 13 or pin 14 (TSOP package) or ball B3 or ball C4 (CBGA package) can be connected

to V

or both pins can be unconnected. Accelerated program/erase operations are only achieved if a voltage of 5V ± 0.5 V or

12V ± 0.5V is applied to pin 13 (TSOP package) or ball C4 (CBGA package).

AT49BV1604A(T)/1614A(T)

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AT49BV1604A(T)/1614A(T)

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see Sector Lockdown section).

The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend feature. This feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. There is no reason to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an erase cycle is detected by the Ready/Busy

The VPP pin provides faster program/erase times. With V erase operations are accelerated.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering down the device, or by pulsing the RESET it back to V

. Erase and Erase Suspend/Resume commands will not work while in this mode;

if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.

When using the AT49BV1604A(T) pinout configuration, the device always operates in the word mode. In the AT49BV/LV1614A(T) configuration, the BYTE device data I/O pins operate in the byte or word configuration. If the BYTE “1”, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE

If the BYTE

pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.

pin, Data Polling or by the toggle bit.

at 5.0V or 12.0V, the program and

pin low for a minimum of 500 ns and then bringing

pin controls whether the

pin is set at logic

and OE.

and OE. The data I/O pins I/O8 - I/O14 are tri-

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Block Diagram

I/O0 - I/O15/A-1

A0 - A19

INPUT

BUFFER

ADDRESS

LATCH

Y-DECODER

X-DECODER

OUTPUT BUFFER

OUTPUT

IDENTIFIER

MULTIPLEXER

COMPARATOR

PLANE B

SECTORS

STATUS

DATA

Y-GATING

INPUT

BUFFER

DATA

COMMAND REGISTER

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

CE WE OE RESET BYTE

RDY/BUSY

VPP

VCC GND

PLANE A SECTORS

AT49BV1604A(T)/1614A(T)

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AT49BV1604A(T)/1614A(T)

Device Operation

READ: The AT49BV/LV16X4A(T) is accessed like an EPROM. When CE and OE are low and

is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE

or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE

or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE CE

or WE. Standard microprocessor write timings are used. The address locations used in the

or WE, whichever occurs last. The data is latched by the first rising edge of

command sequences are not affected by entering the command sequences.

RESET: A RESET a logic high level, the device is in its standard operating mode. A low level on the RESET

input pin is provided to ease some system applications. When RESET is at

input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET

pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE the 30H data input command is latched on the rising edge of WE the rising edge of WE

of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a section is t

edge of the sixth cycle while

. The sector erase starts after

. When the sec-

SEC

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 µs.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”;onlyerase operations can convert “0”sto“1”s. Programming is completed after the specified t time. The Data

Polling feature or the Toggle Bit feature may be used to indicate the end of a

cycle

program cycle.

VPP PIN: The circuitry of the AT49BV/LV16X4A(T) is designed so that the device can be programmed or erased from the V than or equal to the VCC pin, the device selects the V

power supply or from the VPP input pin. When VPPis less

supply for programming and erase

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operations. When the VPP pin is greater than the VCCsupply, the device will select the V

input as the power supply for programming and erase operations. The device will allow for some variations between the V

input and the VCCpower supply in its selection of VCCor V

for program or erase operations. If the VPP pin is within 0.3V of VCCfor 2.65V < VCC<3.3V, then the program or erase operations will use V the V

signal is used to accelerate program and erase operations, the VPPmust be in the 5V

± 0.5V or 12V ± 0.5V range to ensure proper operation. The V

and disregard the VPPinput signal. When

pin can be left unconnected.

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector’s usage as a write protected region is optional to the user.

At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: TheEraseSuspendcommandallowsthesystemto interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual-plane architecture, there is no need to use the Erase Suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address (determined by A18 and A19). The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see “Operating Modes” on page 12 (for hardware operation) or “Software Product Identification Entry/Exit” on page 20. The manufacturer and device codes are the same for both modes.

AT49BV1604A(T)/1614A(T)

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AT49BV1604A(T)/1614A(T)

128-BIT PROTECTION REGISTER: The AT49BV/LV16X4A(T) contains a 128-bit register that

can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition table on page 8. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Protection Register Addressing Table” on page 9 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After reading the protection register, the Product ID Exit command must be given prior to performing any other operation.

DATA

POLLING: The AT49BV/LV16X4A(T) features Data Polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data time during the program cycle. Please see “Status Bit Table” on page 21 for more details.

Polling may begin at any

TOGGLE BIT: In addition to Data

Polling, the AT49BV/LV16X4A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle bit that is available on I/O6. While a sector is erase suspended, a read or a program operation from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on page 21 for more details.

RDY/BUSY

another method of detecting the end of a program or erase operation. RDY/BUSY

: For the AT49BV/LV1614A(T), an open-drain Ready/Busy output pin provides

is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY

line.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the AT49BV/LV16X4A(T) in the following ways: (a) V is below 1.8V (typical), the program function is inhibited. (b) VCCpower-on delay: once V

sense: if V

has reached the VCCsense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE gram cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE

low, CE high or WE high inhibits pro-

or CE inputs will not

initiate a program cycle.

INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and control inputs (OE operation of the device. The I/O lines can only be driven from 0 to V

OUTPUT LEVELS: For the AT49BV1604A(T), output high levels (V

0.2V (not V

put levels, V

,CEand WE) may be driven from 0 to 5.5V without adversely affecting the

+0.6V.

) are equal to V

). For 2.65V - 3.3V output levels, V

must be regulated to 2.0V ± 10%, while VCCmust be regulated to 2.65V - 3.0V

CCQ

must be tied to VCC. For 1.8V - 2.2V out-

CCQ

(for minimum power).

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OUT

(1)

2nd Bus

Cycle

(2)

55 555 80 555 AA AAA 55 555 10

3rd Bus

Cycle

4th Bus

Cycle

OUT

5th Bus

Cycle

(7)

6th Bus

Cycle

(3)(4)

CommandDefinitioninHex

1st Bus

Command Sequence

Read 1 Addr D

Chip Erase 6 555 AA AAA

Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA

Byte/Word Program 4 555 AA AAA 55 555 A0 Addr D

Enter Single Pulse Program Mode

Single Pulse Byte/Word Program

Sector Lockdown 6 555 AA AAA 55 555 80 555 AA AAA 55 SA

Erase Suspend 1 XXX B0

Erase Resume 1 PA

Product ID Entry 3 555 AA AAA 55 555 90

Product ID Exit

Program Protection Register

Lock Protection Register - Block B

Status of Block B Protection

(6)

Bus

Cycles

6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0

1AddrD

3 555 AA AAA 55 555 F0

1 XXX F0

4 555 AA AAA 55 555 C0 Addr D

4 555 AA AAA 55 555 C0 080 X0

4 555 AA AAA 55 555 90 80 D

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

(5)

Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’tCare.

The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’tCare in the word mode. Address A19 through A11 and A-1 are Don’t Care in the byte mode.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 10 and 11 for details).

4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled.

5. PA is the plane address (A19-A18).

6. Either one of the Product ID Exit commands can be used.

7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

Voltage on OE

and V

with Respect to Ground ...................................-0.6V to +13.0V

AT49BV1604A(T)/1614A(T)

+0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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