ATMEL AT49LV080-20RI, AT49LV080-20RC, AT49LV080-20CI, AT49LV080-20CC, AT49LV080-15TI Datasheet
...
8-Megabit
(1M x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
AT49BV080
AT49BV080T
AT49LV080
AT49LV080T
Features
•
Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
•
Fast Read Access Time - 120 ns
•
Internal Program Control and Timer
•
16K bytes Boot Block With Lockout
•
Fast Erase Cycle Time - 10 se co nd s
•
Byte-By-Byte Programming - 30 µs/Byte Typical
•
Hardware Data Protection
•
DATA Polling For End Of Program Detection
•
Low Power Dissipation
- 25 mA Active Current
- 50 µA CMOS Standby Current
•
Typical 10,000 Write Cycles
•
Small Packaging
- 8 x 14 mm CBGA
Pin Configurations
Pin Name Function
A0 - A19 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET Reset
RDY/
BUSY Ready/Busy Output
I/O0 - I/O7 Data Inputs/Outputs
The AT49BV/LV080 are 3-volt-only in-system Flash Memory devices. Their 8 megabits of memory are organized as 1,024,576 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 120
ns with po wer dissipation of just 90 mW over the commercial temper ature range.
When the device is deselected, the CMOS standby current is less than 50 µA.
The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49BV/LV080 locates the boot block at lowest order
addresses ("bottom boot"); the AT49BVLV080T locates it at highest order addresses
("top boot").
Description
(continued)
TSOP Top View
Type 1
0812A–8/97
A
B
C
D
E
F
1
234567
A5
A4
A6
A3
A2
A1
A8
A7
A9
I/O1
A0
I/O0
A11
A10
RST
NC
I/O3
I/O2
NC
VCC
CE
VCC
GND
GND
A12
A13
A14
I/O4
I/O6
I/O5
A15
NC
A16
I/O7
OE
RY/BY
A17
A18
A19
NC
NC
WE
CBGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
GND
VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE
OE
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
SOIC
Device Operation
READ:
The AT49BV/LV080 is accessed like an EPROM.
When
CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
CE or OE is high. This dualline control gives designers flexibility in preventing bus
contention.
ERASURE:
Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “ 1”. The entire device can
be erased at one time by using a 6-byte software code.
The software chip erase code consists of 6-byte load commands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enable d, the data in the boot sector will not be
erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the in-
ternal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table).
The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling
edge of
WE or CE, whichever occurs last, and the data
latched on the rising edge of
WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cy-
cle time. The
DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the featur e has been
enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected r egion is optional to the user. The address
range of the AT49BV/LV080 boot block is 00000H to
03FFFH while the address range of the AT49BV/LV080T
boot block is FC000H to FFFFFH.
To activate the lockout feature, a series of six program
commands to specific addresses with s pecific data must
To allow for simple in-system reprogrammability, the
AT49BV/LV080 does not require high input voltages for
programming. 3-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading fr om an EPROM.
Reprogramming the AT49BV/LV080 is performed by erasing the entire 8 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can
be optionally detected by the
DATA polling feature. Once
the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block sec tion includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure
code, and when the feature is enabled, the boot sector is
permanently protected from being reprogrammed.
Description (Continued)
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(1008K BYTES)
OE
WE
CE
ADDRESS
INPUTS
V
CC
GND
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
03FFFH
00000H
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(1008K BYTES)
FC000H
00000H
AT49BV/LV080TAT49BV/LV080
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
FFFFFH FFFFFH
Block Diagram
2
AT49BV/LV080
be performed. Please refer to the Command Definitions
table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identification exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming
lockout by taking the
RESET pin to 12 + 0.5 volts. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the
RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as A tmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49BV /LV080 features
DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin.
DATA
polling may begin at any time during the program cycle.
TOGGLE BIT:
In addition to
DATA polling, the
AT49BV/LV080 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 tog gling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
RDY/
BUSY:
An open drain READY/
BUSY output pin provides another method of detecting the end of a program or
erase operation. RDY/
BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection allows for OR - tying of several devices to the same
RDY/
BUSY line.
RESET:
A
RESET input pin is provided to ease some
system applications. When
RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the
RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
If the
RESET pin makes a high to low transition during a
program or erase operation, the operation may not be successfully completed, and the operation will have to be repeated after a high level is applied to the
RESET pin.
When a high level is reasserted on the
RESET pin, the
device returns to the read or standby mode, depending
upon the state of the control inputs. By applying a 12V
+
0.5V input signal to the
RESET pin the boot block array
can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming
Lockout Override section).
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49BV/LV080 in the following ways: (a) V
CC
sense: if
V
CC
is below 1.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of
OE low, CE
high or
WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the
WE or CE inputs
will not initiate a program cycle.
Device Operation (Continued)
AT49BV/LV080
3
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read
1AddrD
OUT
Chip Erase
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Byte
Program
4 5555 AA 2AAA 55 5555 A0 Addr D
IN
Boot Block
Lockout
(1)
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID
Entry
3 5555 AA 2AAA 55 5555 90
Product ID
Exit
(2)
3 5555 AA 2AAA 55 5555 F0
Product ID
Exit
(2)
1 XXXX F0
Notes: 1. The 16K byte boot sector has the addre s s range 00000H to 03FFFH for the AT49BV/ LV080 and FC000H to FFFFFH for the
AT49BV/LV080T.
2. Either one of the Product ID Exit commands can be used.
Temperature Under Bias.................-55°C to +125°C
Storage Temperature......................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on
OE
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con di t i on s be yo nd those indicated in the operational sections of this specific ation is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
4
AT49BV/LV080
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