ATMEL AT49LV040T-20VI, AT49LV040T-20VC, AT49LV040T-20TI, AT49LV040T-20TC, AT49LV040T-20JI Datasheet

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Features

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Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)

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Fast Read Access Time - 120 ns

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Internal Program Control and Timer

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16K bytes Boot Block With Lockout

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Fast Chip Erase Cycle Time - 10 seconds

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Byte-by-Byte Programming - 30 µs/Byte Typical

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Hardware Data Protection

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DAT A Polling For End Of Program Detection

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Low Power Dissipation

– 25 mA Active Current –50 µA CMOS Standby Current

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Typical 10,000 Write Cycles

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Small Pac ka g ing

– 8 x 8 mm CBGA – 8 x 14 mm V-TSOP

Description

The AT49BV/LV040 are 3-volt-only, 4-megabit Flash memories organized as 524,288 words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 120 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available: the AT49BV/LV04 0 locates th e boot block at lowest orde r addresses (“bottom b oot”); th e AT49B V/LV0 40T loc ates it a t highe st or der ad dresse s (“top boot”).

4-Megabit (512K x 8) Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV040 AT49BV040T AT49LV040

™

Pin Configurations

Pin Name Function

A0 - A18 Addresses CE OE WE I/O0 - I/O7 Data Inputs/Outputs

Chip Enable Output Enable Write Enab le

PLCC Top View

(continued)

CBGA Top View

234567

GND

I/O6

VCC

I/O2

A17

I/O7

I/O4

A10 A14 A16 A15

NC A13 A11 A12

D E F

I/O5

NC NC NC NC NC

I/O3

A18

NC A7

I/O0 I/O1

A6 A4 A5

GND

CE A0 A3 A1 A2

V - TSOP Top View (8 x 14 mm) or

T - TSOP Top View (8 x 20 mm)

AT49LV040T AT49BV/LV040

0679AX-A–9/97

To allow for simple in-system reprogrammability, the AT49BV/LV040 does not require high input voltages for programming. Three-volt-only commands determine the read and prog rammin g operat ion of th e device . Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV040 is performed by erasing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be

optionally detected by the DATA

polling feature. Once the

end of a byte program cyc le has been detected, a new

Block Diagram

DATA INPUTS/OUTPUTS

GND

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

BLOCK (16K BYTES)

access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is design ed to contai n user secur e code, and when the featur e is en abled , the b oot s ector i s perma nently protected from being reprogrammed.

AT49BV/LV040TAT49BV/LV040

I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(496K BYTES)

OPTIONAL BOOT

7FFFFH 7FFFFH

03FFFH

00000H

DATA INPUTS/OUTPUTS

I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT

BUFFERS Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(496K BYTES)

7C000H

00000H

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE line control gives designers flexibility in preventing bus contention.

ERASURE:

512K bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by usi ng a 6-byte sof tware code. The software chip erase code consists of 6-byte load commands to specific ad dress locatio ns with a specif ic data pattern (please refer to the Chip Erase Cycle Waveforms).

After the softwar e chip erase has been in iti ate d, the de vi c e will internally time the erase operation so that no external clocks are required. The maximu m time neede d to erase the whole chip is t been enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING:

the device is programme d (to a logica l “0”) on a by te-bybyte basis. Please note tha t a data “0” cannot be programmed back to a “1”; only erase operations can convert

The AT49BV/LV040 is accessed like an EPROM.

and OE are low and WE is high, the data stored

or OE is high. This dual-

Before a byte can be reprogrammed, the

. If the boot block lockout feature has

Once the memory array is erased,

“0”s to “1”s. Pr ogramm ing i s ac compli shed via th e int ernal device command register and is a 4 bus c ycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE latched on the rising edge of WE first. Programming is completed after the specified t

or CE, whichever occurs last, and the data

or CE, whichever occurs

cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the fea ture has bee n enabled . The size of the block i s 16K bytes. This blo ck, ref erre d to as t he boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is update d. This feature does no t have to b e activated; the boot block 's us age as a write pr otec te d regi on is optional to the user. The address range of the AT49BV/LV040 boot block is 00000H to 03FFFH while the address range of the AT49BV/LV040T boot block is 7C000H to 7FFFFH.

AT49BV/LV040

Once the feature is enabled , the data i n the boot bl ock can no longer be erased or programmed. Data i n the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is l ocked o ut. Wh en the device is in the so ftware product iden tification mode (see Soft ware Product Identification Entry and Exit sections) a read from address location 00002H will sho w if program ming th e boot bloc k is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product i dentification code should be used to return to standard operation.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation.

The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

The product identification

A software

DAT A POLLING:

ing to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the comp lem ent of the loaded data on I/O 7. O n ce the program cycle has been completed, true data is valid on all outputs and the next c ycle m ay be gin. DATA may begin at any time during the program cycle.

TOGGLE BIT:

AT49BV/LV040 provides another method for determining the end of a program or erase cycle. During a program or erase operation, succ es s ive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the AT49BV/LV040 in the following ways : (a) V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE inhibits program cycl es . (c) Noi s e fi lte r: pul s es of l es s than 15 ns (typical) on the WE gram cycle.

INPUT LEVELS:

power supply, th e address inpu ts and con trol inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the devic e. The I/O lines can only be driven from 0 to VCC + 0.6V.

The AT49BV/LV040 features DATA

In addition to DATA

Hardware features

sense: if VCC is below 1. 8V

low, CE high or WE high

or CE inputs will not initiate a pro-

While operating with a 2.7V to 3.6V

polling the

poll-

polling

Command Definition (in Hex)

1st Bus

Command Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D Boot Block Lockout Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit Product ID Exit

Notes: 1. The 16K byte boot sector has the addres s ran ge 0000 0H to 03FFF H f or the AT49BV/LV040 and 7C000H to 7FFFFH for the

(2) (2)

AT49BV/L V040T.

2. Either one of the Product ID exit commands can be used.

(1)

Bus

Cycles

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0 1 XXXX F0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature Under Bias................................-55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground............................-0.6V to V

Voltage on OE

with Respect to Ground..................................-0.6V to + 13.5V

AT49BV/LV040

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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