ATMEL AT49LV020-90JC, AT49LV020-70VI, AT49LV020-70VC, AT49LV020-70TI, AT49LV020-70TC Datasheet

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Features

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Single Supply Voltage, Range 2.7V to 3.6V

•

Single Supply for Read and Write

•

Fast Read Access Time - 70 ns

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Internal Program Control and Timer

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8K bytes Boot Block With Lockout

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Fast Erase Cycle Time - 10 seconds

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Byte By Byte Programming - 30

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Hardware Data Protection

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DAT A Polling For End Of Program Detection

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Low Power Dissipation

– 25 mA Active Current

µµµµ

–50

A CMOS Standby Current

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Typical 10,000 Write Cycles

µµµµ

s/Byte typical

2-Megabit (256K x 8)

Description

The AT49BV020 and the AT49LV020 are 3-volt-only, 2 megabit Flash memories organized as 262,144 words of 8 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the comm ercial temperatur e range. Wh en the device is des elected, the CMOS standby current is less than 50 µA.

To allow for simple in-system reprog ramma bil it y, the AT49B V/L V0 20 does not requi r e high input voltages for programming. Three-volt-only commands determine the read and programming ope ratio n o f th e d evi ce. Reading data out of th e de vi c e i s si mi lar t o reading from an EPROM. Reprogramming the AT49BV/LV020 is performed by erasing the entire 2 megabits of memory and then programming on a byte by byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

polling feature. Once the end of a byte program cycle

(continued)

Pin Configuration

Pin Name Function

A0 - A17 Addresses CE OE Output En able WE

Chip Enable

Write Enable

Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV020 AT49LV020

™

I/O0 - I/O7 Data Inputs/Outputs NC No Connect

VSOP Top View (8 x 14mm) or

TSOP Top View (8 x 20mm)

Type 1

PLCC Top View

Rev. 0678C–03/98

The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is desig ned to contai n user secure code,

Block Diagram

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs . The outputs ar e put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

ERASURE:

bytes memory array (or 248K bytes if the boot block featured is used) must be erased. The eras ed state of the memory bits is a logica l “1”. The entire device c an be erased at one time by using a 6-byte software code. The software chi p erase code c onsists of 6-b yte load co mmands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been ini tiated , the devi ce will internally time the eras e operatio n so that no ex ternal clocks are required. The maximum time needed to erase the whole chip is t been enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING:

erased, the device is programmed (to a logical “0”) on a byte-by-byte bas is. Please note th at a data “0” ca nnot be programmed ba ck to a “1 ”; only er ase op eratio ns can co nvert “0”s to “1” s. Programming is accompl ished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE latched on the rising edge of WE first. Programming is completed after the specified t

The AT49BV/LV0 20 is acces sed like an EPROM.

and OE are low and WE is high, the data stored

or OE is high. This dual-line

Before a byte can be reprogrammed, the 256K

. If the boot block lockout feature has

Once the memory array is

or CE, whichever occurs last, and the data

or CE, whichever occurs

cycle

and when the featur e is en abled , the b oot s ector i s perma nently protected from being reprogrammed.

time. The DATA the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

has one designated block that has a programming lockout feature. This feature prevents programmin g of data in the designated block once the feature has been enabled. The size of the bloc k is 8K by tes. This bloc k, refe rred to as the boot block, can contain secure code that is used to bring up the system. Enablin g the l ockout fe ature will allow t he boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot blo ck' s usage as a wr ite protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH.

Once the feature is enabl ed, the da ta in the bo ot block c an no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activ ate th e loc k out fe ature, a series of six program commands to spec ific addresses wi th specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOC K LOCKOUT DET ECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H wil l s how i f pr ogram mi ng the b oot block is locked out. If the data on I/O0 is low, the boot bl ock c an be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It

polling f ea t ur e ma y al so b e u se d to i n di ca te

The device

A software

The product identification

AT49BV020

may be accessed by hardware or software operation. The hardware oper ation mode can be used by an exte rnal programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING :

The AT49BV/LV020 features DATA

polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the c ompleme nt of the load ed data on I/O7 . Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA

polling

may begin at any time during the program cycle.

TOGGLE BIT:

In addition to DATA

polling the AT49BV/LV020 provides another method for determining the end of a program or erase cycle. Dur ing a program or

device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the togg le bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs to the AT49BV/LV020 in the following ways: (a) V

sense: if VCC is below 1.8V

(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE

low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not i ni t ia t e a pro-

gram cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, th e address inp uts and con trol inputs (OE

and WE) may be driven from 0 to 5.5V without

CE adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V

+ 0.6V.

erase operation, successive attempts to read data from the

Command Definition (In Hex)

1st Bus

Command Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Bus

Cycles

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Da ta Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D Boot Block

Lockout Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit Product ID Exit

Notes: 1. The 8K byte boot sector has the address range of 00000H to 01FFFH.

(1)

(2)

2. Either one of the Product ID exit commands can be used.

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0 1 XXXX F0

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature.....................................-65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d functional oper ation of the de vice at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect de vice reliability .

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