ATMEL AT49LV008-11TI, AT49LV008-11TC, AT49LV008-12TI, AT49LV008-12TC, AT49BV008-15TI Datasheet

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Features

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Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)

•

Fast Read Access Time - 110 ns

•

Internal Program Control and Timer

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16K bytes Boot Block With Lockout

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Fast Erase Cycle Time - 10 seconds

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Byte-By-Byte Programming - 30

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Hardware Data Protection

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DAT A Polling For End Of Program Detection

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Low Power Dissipation

– 25 mA Active Current

µµµµ

–50

A CMOS Standby Current

•

Typical 10,000 Write Cycles

µµµµ

s/Byte Typical

8-Megabit (1M x 8)

Description

The AT49BV/LV008 is a 3-volt-only in-system Flash Memory device. Its 8 megabits of memory is organized as 1,024,576 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 110 ns with power diss ipation of j ust 9 0 mW over the comm ercial temp erat ure range. Whe n the device is deselected, the CMOS standby current is less than 50 µA.

(continued)

Pin Configurations

Pin Name Function

A0 - A19 Addresses CE OE WE Write Enable RESET RDY/BUSY I/O0 - I/O7 Data Inputs/Outputs NC No Connect

Chip Enable Output Enable

Reset Ready/Busy Output

TSOP Top VIew

Type 1

3-volt Only Flash Memory

AT49BV008 AT49LV008

AT49BV/LV008 8-Megabit 1M x 8 3-volt Only

A16 A15 A14 A13 A12 A11

RESET

RDY/BUSY

A18

1 2 3 4 5 6 7

10 11

12 13 14

A17

GND

A19

A10

I/O7

I/O6

I/O5

I/O4

VCC

I/O3

I/O2

I/O1

I/O0

GND

Rev. 1043A–03/98

To allow for simple in-system reprogrammability, the AT49BV/LV008 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the devic e. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV008 is performed by erasing the entire 8 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA

polling feature . On ce th e end of

Block Diagram

GND

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles

The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the featur e is en abled, the bo ot sec tor is per manently protected from being reprogrammed.

DATA INPUTS/OUTPUTS

I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT

BUFFERS Y-GATING

MAIN MEMORY

(1008K BYTES)

OPTIONAL BOOT

BLOCK (16K BYTES)

FFFFFH

03FFFH

00000H

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

ERASURE:

1024K bytes memor y array (or 1008K bytes i f the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specifi c address locatio ns with a specif ic data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software c hi p e rase h as b een i niti ate d, the d evi c e will internally time the er ase operation so that no e xternal clocks are required. The maximum time needed to erase the whole chip is t been enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING:

erased, the device is programme d (to a logical “0”) on a byte-by-byte ba sis. Please n ote t hat a d ata “0” cannot be

The AT49BV/LV008 is accessed like an EPROM.

and OE are low and WE is high, the data stored

or OE is high. This dual-line

Before a byte can be reprogrammed, the

. If the boot block lockout feature has

Once the memory array is

programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatic ally gen erate the required internal program pulses.

The program cyc le has address es latched on the falling edge of WE latched on the rising edge of WE first. Programming is completed after the specified t time. The DATA

or CE, whichever occurs last, and the data

or CE, whichever occurs

cycle

polling feature may also be us ed to indi-

cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block that has a programming lockout feature. This feature prevents programming of data in th e designated block once the feature has been enabled. The size of the block i s 16K b ytes. This bl ock, re ferred to as t he boot block, can contain secure code that is used to bring up the system. Enablin g the l ockou t feature w ill al low the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’ s u sag e as a wr i te pro t ected r eg io n is optional to the user. The address range of the AT49BV/LV008 boot block is 00000H to 03FFFH.

AT49BV/LV008

To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product ident ification mode (s ee Software Produ ct Identification Entry and Exit sections) a read from address location 00002H will s how if pro gramm ing the bo ot block is locked out. If the da ta o n I/O 0 is lo w, th e bo ot b loc k c an b e programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boo t block prog rammin g lockout by taking the RESET tected boot block data can be altered through a chip erase, or byte programming. When the RESET to TTL levels, the boot block programming lockout feature is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see O peratin g Modes (for har dware operatio n) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

ing to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the nex t cycle ma y beg in. DATA may begin at any time during the program cycle.

pin to 12V ± 0.5V. B y doin g this, pr o-

The product identification

The AT49BV/LV008 features DATA

A software

pin is brought back

poll-

polling

TOGGLE BIT:

AT49BV/LV008 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Exami ning the to ggle bit may begin at any time during a program cycle.

RDY/BUSY

vides another method of detectin g the end of a progr am or erase oper ation . RDY/B USY the internal program and erase cycles and is released at the completion of the cycle. The open drain connection allows for OR - tying of severa l devices to the same RDY/BUSY

RESET:

tem applications. When RESET device is in its standard operating mod e. A low lev el on th e RESET outputs of the device in a high impedance state, and reduces the cu rrent draw n by th e part to a mi nimu m. I f th e RESET or erase operation, the operation may not be successfully completed and the oper ation wi ll have to be r epeated af ter a high level is applied to the RESET is reasserted on the RESET read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET even if the boot block lockout fea ture has been enab led (see Boot Block Programming Lockout Override section).

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the AT49BV/LV008 in the following ways: (a) V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE gram cycle.

A RESET

input halts the pr esent dev ice op eration, puts th e

pin makes a high to low transition during a program

pin, the boot block array can be reprogrammed

In addition to DATA

An open drain READY/BUSY

is actively pulled low during

line.

input pin is prov ided to eas e so me s ys-

is at a logic high level, the

pin. When a high level

pin, the device returns to the

sense: if VCC is below 1.8V

low, CE high or WE high

or CE inputs will not initiate a pro-

polling, the

output pin pro-

Hardware features

Command Definition (in Hex)

1st Bus

Command Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D Boot Block Lockout Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit Product ID Exit

Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH.

2. Either one of the Product ID Exit commands can be used.

(2)

Bus

Cycles

(1)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0 1 XXXX F0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature.....................................-65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d functional oper ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect de vice reliability .

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49BV/LV008

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