ATMEL AT49BV001, AT49LV001, AT49BV001N, AT49LV001N, AT49BV001T User Manual

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Features

•

Single Supply for Read and Write: 2.7V to 3.6 (BV), 3.0 to 3.6V (LV)

•

Fast Read Access Time - 70 ns

•

Internal Program Control and Timer

•

Sector Architecture

– One 16K Byte Boot Block with Programming Lockout – Two 8K Byte Parameter Blocks – Two Main Memory Blocks (32K, 64K) Bytes

•

Fast Erase Cycle Time - 10 seconds

•

Byte By Byte Programming - 30

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low Power Dissipation

µµµµ

s/Byte Typical

– 25 mA Active Current

µµµµ

–50

A CMOS Standby Current

•

Typical 10,000 Write Cycles

Description

The AT49BV/LV001(N)(T) is a 3-volt-only in-system reprogrammable Flash Memory. Its 1 megabit of memor y is orga nized as 13 1,072 wor ds by 8 bits . Manufact ured wit h Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power di ssipation of just 90 mW over the commer cial tempe rature ra nge. When the device is deselected, the CMOS standby current is less than 50 µA. For the

(continued)

Pin Configurations

DIP Top View

1-Megabit (128K x 8) Single 2.7-Volt

Battery-Voltage

Flash Memory

AT49BV001 AT49LV001

™

Pin Name Function

A0 - A16 Addresses CE OE

Chip Enable

Output Enable WE Write Enable RESET

RESET I/O0 - I/O7 Data Inputs/Outputs DC Don’t Connect NC No Connect

VSOP Top View (8 x 14mm) or

*RESET

A16 A15 A12

I/O0 I/O1 I/O2

GND

A7 A6 A5 A4 A3 A2 A1 A0

TSOP Top View (8 x 20mm)

I/O0

PLCC Top View

A12

A15

A16

RESET*

VCCWENC

432

323130

14151617181920

I/O1

I/O2

I/O3

I/O4

I/O5

GND

29 28 27 26 25 24 23 22 21

I/O6

A14 A13 A8 A9 A11 OE A10 CE I/O7

A11

A13 A14 NC

VCC

*RESET

A16 A15 A12

1 2

4 5 6 7 8 9 10 11 12 13

Type 1

*Note: This pin is a DC on the AT49BV001N(T) and AT49LV001N(T).

VCC WE NC

A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3

AT49BV001N AT49LV001N AT49BV001T AT49LV001T AT49BV001NT AT49LV001NT

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

Rev. 1110A–07/98

AT49BV/LV001N T pin 1 for the DI P and PLCC pa ckages and pin 9 for the TSOP package are don’t connect pins.

To allow for simple in-system reprogrammability, the AT49BV/LV001(N)(T) does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the devic e. Reading data out of the device is similar to reading from an EPROM; it has standard CE

, OE, and WE inputs to av oid bus contention. Reprogramming the AT49BV/LV001(N)(T) is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA

polling feature. Once the end of a byte program cycle h as be en dete cted, a new a ccess for a read or program can begin. The typi cal num ber of progr am and erase cycles is in excess of 10,000 cycles.

Block Diagram

DATA INPUTS/OUTPUTS

GND

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

The device is erased by execu ting the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sect ions and two main memory blocks.

The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K byte boot block se ct ion inc lu des a repro gr am min g lock out feature to pr ov ide data in tegr i ty. Th e bo ot s ec tor is designed to contai n user secu re code, and whe n the feature is enabled, the boot sector is protected from being reprogrammed.

In the AT49BV/LV0 01N(T), once th e boot block programming lockout feature is enabled, the contents of the boot block are perm anent and cannot be ch anged. In the AT49BV/LV001(T), once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less.

AT49BV/LV001(N)

I/O7 - I/O0

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

1FFFF

10000 0FFFF

08000 07FFF

06000 05FFF

04000 03FFF

00000

AT49BV/LV001(N)T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

BOOT BLOCK

(16K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

1FFFF

1C000 1BFFF

1A000 19FFF

18000 17FFF

10000 0FFFF

00000

AT49BV/LV001(N)(T)

Device Operation

READ:

EPROM. When CE data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE high. This dual-line con tr ol gi v es d esign er s fl ex ibi lit y in pr eventing bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE tively) and OE edge of CE latched by the first rising edge of CE microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences.

RESET:

tem application s. When RE SET device is in its standa rd oper at ing mod e. A low l ev el on the RESET the outputs of the device in a high impedance state. If the RESET or erase operation, the operation may not be successfully completed and the op eration wi ll have to be repeated af ter a high level is applied to the RESET is reasserted on the RESET read or standby mode, depending upon the state of the control inputs. By ap plying a 12 V ± 0 .5V in put si gnal t o th e RESET even if the boot block lock out feature has be en enabled (see Boot Bl ock Prog rammi ng Locko ut Ov erride s ection ). The RESET feature is not available on the AT49BV/LV001N(T).

ERASURE:

memory block or parameter block which contains the byte must be erased. The erased state of th e memory bits is a logical “1”. The entir e device c an be erased at one time by using a 6 byte software code. The software chip erase code consists of 6 byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software c hi p e rase h as b een i niti ate d, the d evi c e will internally time the er ase operation so that no e xternal clocks are required. The maximum time needed to erase the whole chip is t been enabled, the data in the boot sector will not be erased.

The AT49BV/LV 001(N)(T) is ac cessed like a n

and OE are low and WE is high, th e

or OE is

When the device is firs t pow-

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard

A RESET

input halts the prese nt device oper ation and puts

pin makes a high to low transition during a program

pin, the boot block array can be reprogrammed

Before a byte can be reprogram med, the main

input pin is provided to ease some sys-

is at a logic high level, the

pin. When a high level

pin, the device returns to the

. If the boot block lockout feature has

AT49BV/LV001(N)(T)

CHIP ERASE:

the Chip Erase function will erase Parameter Block 1, Parameter Block 2, M ain Me mory B lock 1, a nd Mai n Memory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any c omm and during chi p eras e will be ignored.

SECTOR ERASE

device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections can be independently erased and reprogrammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogra mme d, th e other block should be erased and r eprogrammed be fore the first block is again erased. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE input command is latched at the ris ing edge of WE sector erase starts after the rising edge of WE cycle. The erase op eration is in ternally contr olled; it wil l automatically time to completion.

BYTE PROGRAMMING:

erased, the device is programmed (to a logical “0”) on a byte-by-byte ba sis. Pl ease n ote tha t a data “0” c annot b e programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatic ally gen erate the required internal program pulses.

The program cyc le has address es latched on the falling edge of WE latched on the rising edge of WE first. Programming is completed after the specified t time. The DATA cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

has one designated block that has a programming lockout feature. This feature prevents programming of data in th e designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enablin g the l ockou t feature w ill al low the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’ s u sag e as a wr i te pro t ected r eg io n is optional to the user. The address range of the boot block is 00000 to 03FFF for the AT49BV/LV001(N) while the

If the boot block lockout has been enabled,

: As an alternative to a full chip erase, the

edge of the sixth cycle while the 30H data

. The

of the sixth

Once the memory array is

or CE, whichever occurs last, and the data

or CE, whichever occurs

cycle

polling feature may also be us ed to indi-

The device

address range of the boot block is 1C000 to 1FFFF for the AT49BV/LV001(N )T.

Once the feature is enabled, the data in th e boot blo ck ca n no longer be erased or programmed with input voltage level of 5.5V or less. Data in the ma in memory bl ock can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product ident ification mode (s ee Software Produ ct Identification Entry and Exit sections) a read from address location 00002H will s how if pro gramm ing the bo ot block is locked out for the AT49BV/LV001(N ) and a read from address 1C002H will show if programming the boot block is locked out for the AT49BV/LV001(N)T. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boo t block prog rammin g lockout by taking the RESET erase, sector erase or byte programming operation. When the RESET programming lockout feature is again active. This feature is not available on the AT49BV/LV001N(T).

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It

pin is brought back to TTL levels the boot block

pin to 12 volts during the entire chip

The product identification

A software

may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see O perat ing Mode s (for ha rdware operat ion) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

polling to indicate the end of a program cycle. During

DATA a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

TOGGLE BIT:

AT49BV/LV001(N)(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read . Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the AT49BV/LV001(N)(T) in the following ways: (a) V

is below 1.8V (typic al), the pr ogra m function i s inhib-

if V

ited. (b) Program inhi bit: holding a ny one of OE high or WE high inhibits progr am cycles. (c) No ise filter: pulses of less than 15 ns (typical) on the WE will not initiate a program cycle.

The AT49BV/LV001(N)(T) features

In addition to DATA

polling the

Hardware features

sense:

low, CE

or CE inputs

AT49BV/LV001(N)(T)

Cycle

(1)

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

(4)

Command Definition (in Hex)

1st Bus

Command Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D Boot Block Lockout Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit Product ID Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)

2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV001(N) and

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses:

(3)

1C000H to 1FFFFH for the AT49BV/LV001(N)T.

For the AT49BV/LV001(N): SA = 10000 to 1FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 04000 to 05FFF for PARAMETER BLOCK 1 SA = 06000 to 07FFF for PARAMETER BLOCK 2 SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2

Bus

Cycles

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0 1 XXXX F0

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

For the AT49BV/LV001(N)T: SA = 1C000 to 1FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 1A000 to 1BFFF for PARAMETER BLOCK 1 SA = 18000 to 19FFF for PARAMETER BLOCK 2 SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Ab solute Maxi-

mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC and AC Operating Range

AT49LV001(N)(T)-70 AT49BV/LV001(N)(T)-90 AT49BV/LV001(N)(T)-12

Operating Temperature (Case)

Power Supply 3.0V - 3.6V 2.7V - 3.6V/3.0V - 3.6V 2.7V - 3.6V/3.0V - 3.6V

Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C

Operating Modes

Mode CE OE WE RESET

Read V Program/Erase

(2)

Standby/Write Inhibit V

Program Inhibit X X V Program Inhibit X V Output Disable X V

IH (1)

XV Reset X X X V Product Identification

Hardware

Software

(5)

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms. = 12.0V ± 0.5V.

3. V

4. Manufacturer Code: 1FH, Device Code: 05H - AT49BV/LV001(N), 04H - AT49BV/LV001(N)T.

5. See details under Software Product Identification Entry/Exit.

6. This pin is not available on the AT49BV/LV001N(T).

(6)

A1 - A16 = VIL, A9 = VH,

A0 = VIL, A1 - A16=V A0 = VIH, A1 - A16=V

Ai D Ai D

X High Z

(3)

A0 = V

(3)

A0 = V

I/O

OUT

High Z

Manufacturer Code

Device Code

(4)

Manufacturer Code Device Code

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

SB1

SB2

(1)

Input Load Current VIN = 0V to V Output Leakage Current V VCC Standby Current CMOS CE = V VCC Standby Current TTL CE = 2.0V to V V

Active Current f = 5 MHz; I

Input Low Voltage 0.6 V Input High Voltage 2.0 V Output Low Voltage IOL = 2.1 mA .45 V Output High Voltage IOH = -400 µA2.4V

Note: 1. In the erase mode, ICC is 50 mA.

AT49BV/LV001(N)(T)

= 0V to V

I/O

- 0.3V to V

OUT

= 0 mA 25 mA

10 10 50

3mA

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