ATMEL AT49LL080 User Manual

Features

• Conforms to Intel LPC Interface Specification 1.0

• 8M Bits of Flash Memory for Platform Code/Data Storage

– Automated Byte-program and Sector-erase Operations

• Two Configurable Interfaces

– Low Pin Count (LPC) Interface for In-System Operation – Address/Address Multiplexed (A/A Mux) Interface for Programming during

Manufacturing

• Low Pin Count Hardware Interface Mode

– 5-signal Communication Interface Supporting x8 Reads and Writes – Read and Write Protection for Each Sector Using Software-controlled Registers – Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other

Sectors – Five General-purpose Inputs, GPIs, for Platform Design Flexibility – Operates with 33 MHz PCI Clock and 3.3V I/O

• Address/Address Multiplexed (A/A Mux) Interface

– 11-pin Multiplexed Addre ss and 8-pin Data Interface – Supports Fast On-board or Out-of-system Programming

• Power Supply Specifications

: 3.3V ± 0.3V

–V

: 3.3V and 12V for Fast Programming

• Industry-standard Package

– 40-lead TSOP or 32-lead PLCC

Description

8-megabit Low-pin Count Flash Memory

AT49LL080

The AT49LL080 is a Flash m em or y device de signe d to i nterface wit h the LPC bus for PC Applications. A feature of the AT49LL080 is the nonvolatile memory core. The high-performance memory is arranged in sixteen sectors (see page 11).

The AT49LL080 supports two hardware interfaces: Low Pin Count (LPC) for in-system operation and Address/Ad dr es s M ult ipl exed (A/A Mux) for programming during manufacturing. The IC (Interface Configuration) pin of the device provides the control between the interfaces. The interface mode nee ds to be selected prio r to power-up or before return from reset (RST

or INIT low to high transition).

Pin Configu ra tion

TSOP, Type I

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

[ ] Designates A/A Mux Mode

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

GNDa [GNDa] VCCa [VCCa] LFRAME [WE] INIT [OE] RFU [RY/BY] RFU [I/O7] RFU [I/O6] RFU [I/O5] RFU [I/O4] VCC [VCC] GND [GND] GND [GND] LAD3 [I/O3] LAD2 [I/O2] LAD1 [I/O1] LAD0 [I/O0] NC [A0] ID1 [A1] ID2 [A2] ID3 [A3]

GPI2 [A8] 432

[A7] GPI1 [A6] GPI0

[I/O0] LAD0

5 6 7

[A5] WP

[A4] TBL

[A3] ID3

[A2] ID2

[A1] ID1

[A0] NC

14151617181920

[I/O1] LAD1

[ ] Designates A/A Mux Mode

PLCC

GPI3 [A9]

RST [RST]

VPP [VPP] 1

[I/O2] LAD2

[I/O3] LAD3

[GND] GND

VCC [VCC]

CLK [R/C]

GPI4 [A10]

323130

29 28 27 26 25 24 23 22 21

[I/O4] RFU

[I/O5] RFU

[I/O6] RFU

IC (VIL) [IC(VIH)] CE [NC] NC NC VCC [VCC] INIT [OE] LFRAME [WE] RFU [RY/BY] RFU [I/O7]

[IC (V

(NC) CE

)] IC (VIL)

[NC] NC [NC] NC [NC] NC [NC] NC

[A10] GPI4

[NC] NC

[R/C] CLK [VCC] VCC [VPP] VPP [RST] RST

[NC] NC

[NC] NC [A9] GPI3 [A8] GPI2 [A7] GPI1 [A6] GPI0

[A5] WP

[A4] TBL

Rev. 3273C–FLASH–5/03

An internal Command User Interface (CUI) serves as the control center between the two device interfac es (LP C and A /A M ux) an d inte rnal operat ion o f t he no nvola tile memor y. A valid command sequence written to the CUI initiates device automation.

Specifically designe d for 3V systems , the AT49LL 080 supports read operation s at 3.3V and sector erase and program operations at 3.3V and 12V V

. The 12V VPP option ren-

ders the fastest pro gram pe rformanc e whic h will incre ase fact ory thro ughput, b ut is not recommended for standard in-system LPC operation in the platform. Internal V

detec-

tion circuitry automatically configures the device for sector erase and program operations. Note that, while current for 12V programming will be drawn from V programming board s oluti ons sho uld d esign suc h that V

, and should assume that full programming current may be drawn from either pin.

as V

draws from the same supply

, 3.3V

Low Pin Count Interface The Low Pin Count (LPC) interface is designed to work with the I/O Controller Hub (ICH)

during platform operation . The LPC interfac e consis ts primar ily of a five-signa l co mmunica tion inte rface use d to

control the operation of the device in a system environment. The buffers for this interface are PCI compliant. To ensure the effective delivery of security and manageability features, the LPC interface is th e only way to ge t access to the full feature set of the device. The LPC in terface i s equ ipped t o oper ate at 3 3 MHz, synchronous with th e PCI bus.

Address/Address Multiplexed Interface

Block Diagram

The A/A Mux interface is designed as a programming interface for OEMs to use during motherboard manufacturing or component pre-programming.

The A/A Mux refers to the mul tiplex ed ro w and co lumn a ddres ses in t his i nterfa ce. This approach is required so that the device can be tested and programmed quickly with automated test equipm ent (A TE) and PROM prog ramm ers in the OEM’ s manu facturin g flow. This interface also allows the device to have an efficient programming i nterface with potentially l arge futu re den siti es, whi le st ill fitti ng into a 32- pin pa ckag e. Only basic reads, programming, and erase of the nonvolatile memory sectors can be performed through the A/A Mux interface. In this mode LPC features, security features and registers are unavailable. A row/column (R/C

) pin determines which set of addresses “rows

or columns” are latched.

TBL

GPI (4:0)

ID (3:1)

LAD (3:0)

LFRAME

CLK INIT

R/C

RY/BY

A10 - A0

I/O7 - I/O0

LPC

INTERFACE

A/A MUX

INTERFACE

FLASH

ARRAY

CONTROL

LOGIC

RST IC

AT49LL080

3273C–FLASH–5/03

AT49LL080

Pin Description Table 1 details the usage of each of the device pins. Most of the pins have dual function-

ality, with functions in bo th the Firmware Hub and A/A Mux interfaces. A/A Mux functionality for pins is shown in bold in the description box for that pin. All pins are designed to be compliant with voltage of V

Table 1. Pin Description

Interface

Symbol Type

IC INPUT X X INTERFACE CONFIGURATION PIN: This pin determines which interface is

RST INPUT X X INTERFACE RESET: Valid for both A/A Mux and LPC interface operations.

INIT

CLK INPUT X 33 MHz CLOCK for LPC INTERF ACE: This input is the s am e a s t he PC I clo ck

INPUT X PROCESSOR RESET: This i s a s ec ond res et pi n for in-system use. This pin is

Name and FunctionLPC A/A Mux

operational. This pin is held high to enable the A/A Mux interface. This pin is held low to enab le the LPC i nterf ace. This pin m ust be s et at pow er-up o r bef ore return from reset and not changed during device operation. This pin is pulled down with an internal resistor, with values between 20 and 100 kΩ. With IC high (A/A Mux mode), this pin will exhibit a leakage current of approximately 200 µA. This pin may be floated, which will select LPC mode.

When driven l ow, RST power transitions, resets internal automation, and tri-states pins LAD[3:0] (in LPC interface mode). RST high enables normal operation. When exiting from reset, the device defaults to read array mode.

internally combined with the RST operation is exhibited. This signal is designed to be connected to the chipset INIT signal (Max voltage depends on the processor. Do not use 3.3V.)

A/A Mux = OE

and adheres to the PCI specification. A/A Mux = R/C

inhibits write operations to pro vide data pr otection during

+ 0.3V max, unless otherwise noted.

pin. If this pin or RST is driven low, identical

LAD[3:0] I/O X ADDRESS AND DATA: These pins provide LPC control signals, as well as

addresses and command Inputs/Outputs Data.

A/A Mux = I/O[3:0]

LFRAME INPUT X FRAME: This pin indicates the start of a data transfer operation; also used to

abort an LPC cycle in progress. A/A Mux = WE

ID[3:1] INPUT X IDENTIFICATION INPUTS: These three pins are part of the mechanism that

allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:1] = 000, and it is recommended that all subsequent devices should use a sequential up-count strapping (i.e., 001, 010, 011, etc.). These pins are pulled down with internal resistors, with values between 20 and 100 kΩ when in LPC mode. Any ID pins that are pulled high will exhibit a leakage current of approximately 200 µA. Any pins intended to be low may be left to float. In a single LPC system, all may be left floating.

A/A Mux = A[3:0]

INPUT X When CE is low, the device is enabled. This pin is pulled down with an

internal resistor and can exhibi t a leaka ge curr ent of approximately 10 µA. Since this pin is internally pulled down and thus can be left unconnected, the AT49LL080 is compatible with systems that do not use a CE power, the device is placed in a low-power standby mode when CE

signal. To reduce

is high.

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Table 1. Pin Description (Continued)

Interface

Symbol Type

GPI[4:0] INPUT X GENERAL PURPOSE INPUTS: These individual inpu ts can be used for

TBL INPUT X TOP SECTOR LOCK: When low, prevents programming or sector erase to the

WP INPUT X WRITE-PROTECT: When low, prevents programming or sector erase to all but

A0 - A10 INPUT X LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during read

I/O0 - I/O7 I/O X DATA INPUT/OUTPUTS: These pins receive data and commands during write

Name and FunctionLPC A/A Mux

additional board flexibility. The state of these pins can be read through LPC registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain at the same level until the end of the read cycle. They may only be used for 3.3V signals. Unused GPI pins must not be floated.

A/A Mux = A[10:6]

highest addressable sector (15), regardless of the state of the lock registers

high disables hardware write protection for the top sector, though register-

TBL based protection still applies. The status of TBL

does not affect the status of

sector-locking registers.

A/A Mux = A4

the highest addressable sectors (0 - 14), regardless of the state of the corresponding lock registers. WP-high dis ables hardware write protection fo r these sectors, though register-based protection still applies. The status of TBL does not affect the status of sector-locking registers.

A/A Mux = A5

and write operations. Addresses are internally latched during a write cycle. For the A/A Mux interf ace these addresses are latch ed by R/C and share the same pins as the high-order address inputs.

cycles and transmit data during memory array and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are

disabled. Data is internally latched during a writ e cycle. OE R/C

INPUT X OUTPUT ENABLE: Gates the device’s outputs during a read cycle. INPUT X ROW-COLUMN ADDRESS SELECT: For the A/A Mux interface, this pin

determines whether the address pins are pointing to the row addresses,

A0 - A10, or to the column addresses, A11 - A19. WE

INPUT X WRITE ENABLE: Controls writes to the arra y s ec tors. Addresses and data are

latched on the rising edge of the WE V

SUPPLY X X SECTOR ERASE/PROGRAM POWER SUPPLY: For erasing array sectors or

programming data 0V <

VPP < 3.6V or 12V for faster erase and programming operations. The VPP pi n can be left unconnected. Sector er ase or prog ram with an invalid V not be attempted. V

(see DC Characteristics) produces spurious results and should

may only be held at 12V for 80 hours over the lifetime of

the device.

SUPPLY X X DEVICE POWER SUPPLY: Internal detection automatically configures the

device for optimized read performance. Do no float any power pins. With V V

, all write attempts to the flash memory are inhibited. Device operations at

LKO

invalid V

voltages (see DC Characteristics) produce spurious results and

should not be attempted.

GND SUPPLY X X GROUND: Do not float any ground pins. V

CCa

SUPPLY X X ANALOG POWER SUPPL Y: This supply should share the s ame sy stem su pply

as V

AT49LL080

pulse.

≤

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Table 1. Pin Description (Continued)

Interface

AT49LL080

Symbol Type

GNDa SUPPLY X X ANALOG GROUND: Should be tied to same plane as GND. RFU X RESERVED FOR FUTURE USE: These pins are reserved for future

NC X X NO CONNECT: Pin may be driven or floated. If it is driven, the voltage levels

RY/BY OUTPUT X READY/BUSY: Valid only in A/A Mux Mode. This output pin is a reflection of bit

Low Pin Count Interface (LPC)

Table 2 lists the seven required signals used for the LPC interface.

Table 2. LPC Required Signal List

Signal

LAD[3:0] I/O I/O Multiplexed command, address and data LFRAME

Name and FunctionLPC A/A Mux

generations of this product and should be connected accordingly. These pins may be left disconnected or driven. If they are driven, the voltage levels should meet VIH and VIL requirements.

A/A Mux = I/O[7:4]

should meet VIH and VIL.

7 in the status register. This pin is used to determine sector erase or program completion.

Direction

DescriptionPeripheral Master

I O Indicates start of a new cycle, termination of broken

cycle.

RST

CLK I I Clock: Same 33 MHz clock as PCI clock on the master.

I I Reset: Same as PCI Reset on the master. The master

does not need this sig nal if i t alread y has PCIR ST interface.

Same clock phase with typical PCI skew. The master does not need this signal if it alre ady has PC ICLK on it s interface.

on its

LAD[3:0]: The LAD[3:0] signal lines communicate address, control, and data information over the LPC bus between a master and a peripheral. The information communicated ar e: star t, stop (ab ort a cycl e), trans fer type (memory , I/O, DMA ), transfer direction (read/write), addr ess, data, wait states, DMA channel , and bus master grant.

LFRAME

: LFRAME is used by the master to indicate the start of cycles and the termina-

tion of cycles due to an abort or time-out condition. This signal is to be used be by peripherals to know when to monitor the bus for a cycle.

The LFRAME

signal is used as a general notification that the LAD[3:0] lines contain information relativ e to the s tart or s top of a c ycle, and that pe ripheral s mus t monito r the bus to determine whether the cycle is intended for them. The benefit to p eripherals of LFRAME

When peripherals sample LF RAME

is, it allows them to enter lower power states internally.

active, they are to immediately stop driving the

LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. RESET: RST or INIT at VIL initiates a device reset. In read mode, RST o r INIT low

deselects the memory, place s outp ut driv er s in a high-im ped anc e st ate, and turn s off al l

3273C–FLASH–5/03

internal circuits. RST or INIT must be held low for time t

(A/A Mux and LPC opera-

PLPH

tion). The LPC resets to read array mode upon return from reset, and all sectors are set to default (locked) status regardless of their locked state prior to reset.

Driving RST default (write-locked ) condition . A rese t time (t

switching high until outputs are valid. Likewise, the device has a wake time (t

INIT

or INIT low resets the device, whic h rese ts the sec to r lock r egiste rs to the ir

A/A Mux) is require d from RST or

PHQV

PHRH

A/A Mux) from RST or INIT high until writ es to the CU I are r ecogni zed. A reset la tency will occur if a reset procedure is performed during a programming or erase operation.

During sector er ase or progr am, d riving RST or INIT low will abort the operation underway, in addition to causing a reset latency. Memory contents being altered are no longer valid, since the data may be partially erased or programmed.

It is important to assert RST

or INIT during system reset. When the system comes out of reset, it will expect to read from the memory array of the device. If a system reset occurs with no LPC reset (this will be hardware dependent), it is possible that proper CPU initialization will not occur (the LPC memory may be providing status information instead of memory array data).

CYCLE TYPES: There are two types of cycles that ar e supported by the AT49LL080: LPC Memory Read and LPC Memory Write.

Device Operation READ: Read operations consist of START, CYCTYPE + DIR, ADDRESS, TAR, SYNC

and data fields as shown in Figure 1 and described in Table 5. The different fields are described below. Commands using the read mode include the following functions: reading memory from t he arra y, reading the ident ifier code s, readi ng the lo ck bit r egisters and reading the GPI registers. Memory information, identifier codes, or the GPI registers can be read independent of the V from reset mode, the device automatically resets to read array mode.

voltage. Upon initial device power-up or after exit

READ CYCLE, SINGLE BY TE: For read cycles, af ter the add ress is tran sferred, th e master drives a TAR field to give ownership of the bus to the LPC. After the second clock of the TAR phase the LPC assumes the bus and begins driving SYNC values. When it is ready, it drives the low nibble, then the high nibble of data, followed by a TAR field to give control back to the master.

Figure 1 shows a device that requires three SYNC clocks to access data. Since the access time can begin once the address phase has been completed, the two clocks of the TAR phase can be considered as part of the access time of the part. For example, a device with a 120 ns access time could assert “0101b” for clocks 1 and 2 of the SYNC phase and “0000b” for the last clock of the SYNC phase. This would be equival ent to five clocks worth of access time if the device started that access at the conclusion of the preamble phase. Once SYNC is achieved, the device then returns the data in two clocks and gives ownership of the bus back to the master with a TAR phase.

AT49LL080

3273C–FLASH–5/03

AT49LL080

START: This one-clock field indicates the start of a cycle. It is valid on the last clock that

LFRAME LAD3 - LAD0 must be 0000b to indicate the start of a LPC cycle.

Table 3. CYCTYPE + DIR Fields

LAD[3:0] Indication

010xb LPC Memory Read 011xb LPC Memory Write

CYCTYPES + DIR: This one-clock field is used to indicate the type of cycle and direction of transfer. Bits 3 - 2 must be “01b” for a memory cycle. Bit 1 indicates the type of transfer: “0” for read operation, “1” for write operation. DIR field indication of transfer: “0” for read, “1” for write. Bit 0 is res erved. “010 xb” indica tes a memor y read cy cle; whil e “011xb” indicates a memory write cycle.

MADDR (MEMORY ADDRESS): This is an eight-clock field, which gives a 32-bit memory address. LPC sup ports th e 32-bit ad dress prot ocol. Th e address is transf erred wit h the most significant nibble first. For the AT49LL080, address bit 23 directs Reads and Writes to memory locations (A are device ID strapping bits, and A19 - A0 are decoded as memory addresses.

is sampled low. On the rising edge of CLK with LFRAME low, the contents of

= 1) or to register access locations (A23 = 0). A22 - A

TURN-AROUND (TAR): This field is two clocks wide, and is driven by the mast er when it is turning control over to the LPC, (for example, to read data), and is driven by the LPC when it is turning contro l back ov er to th e master. On the f irst clo ck of th is two-cloc kwide field, the master or LP C driv es the LAD [3:0] lines to “ 1111b” . On the se cond c lock of this field, the master or peripheral tri-states the LAD[3:0] lines.

SYNC: This field is used to add wait state s. It can be sever al clo cks in len gth . On targ et or DMA cycles, this fi eld is driv en by the LPC. If the LPC needs to ass ert wait sta tes, it does so by driving “0101b” (short SYNC) on LAD[3:0] until it is ready. When ready, it will drive “0000b”. Valid values for this field are shown in Table 4.

Table 4. Valid SYNC Values

Bits[3:0] Indication

0000 Ready: SYNC achieved with no error. 0101 Short Wait: Part indicating wait states.

3273C–FLASH–5/03

Figure 1. LPC Read Waveforms

1 2 3 4 5 6 7 8 9 10111213141516171819

CLK

LFRAME

CYCTYPE

LAD[3:0]

START

+ DIR

Table 5. LPC Read Cycle

Clock Cycle Field Name

ADDR TAR SYNC(3) TARDATA

(1)

Field Contents

LAD[3:0]

Direction Comments

1 START 0000b IN LFRAME

Only the last start field (before LFRAME

must be activ e (l o w ) for the part to respond.

transitioning high) should be recog nized. T he START field contents indicate an LPC memory read cycle.

2 CYCTYPE

+ DIR

010xb IN Cycle Type: Indicates the type of cycle. Bits 3:2 must

be 01 for a memory cycle. DIR: Bit 1 indicates the direction of the transfer (0 for

read). Bit 0 is reserved.

3 - 10 ADDR YYYY IN These eight clock cycles make up the 32-bit memory

address. YYYY is one nibble of the entire address. Addresses are tra nsferred most signifi can t ni b ble first.

11 T AR0 1111b IN

then float

In this clock cycle, the master (ICH) has driven the bus to all 1s and then floats the bus, prior to the next clock cycle. This is the first part of the bus “turnaround cycle”.

12 TAR1 1111b (float) Float then OUT The LPC takes control of the bus during this cycle.

During the next clock cycle, it will be driving “sync data”.

13 - 14 WSYNC 0101b (WAIT) OUT The LPC outputs the value 0101, a wait-sync

(WSYNC, a.k.a. “short-sync”), for two clock cycles. This value indicates to the master (ICH) that data is not yet available from the part. This number of waitsyncs is a function of the device’s access time.

15 RSYNC 0000b (READY) OUT During this clock cycle, the LPC will generate a

“ready-sync” (RSYNC) indicating that the least significant nibble of the least significant byte will be avail able during the next cloc k cy cl e.

16 DATA YYYY OUT YYYY is the least significant nibble of the least

significant data byte.

17 DATA YYYY OUT YYYY is the most significant nibble of the least

significant data byte.

18 TAR0 1111b OUT

then float

19 TAR1 1111b (float) Float then

The LPC Flash memory drives LAD0 - LAD3 to 1111b to indicate a turnaround cycle.

The LPC Flash memory floats its outputs, the master (ICH) takes control of LAD3 - LAD0.

Note: 1. Field contents are valid on the rising edge of the present clock cycle.

AT49LL080

3273C–FLASH–5/03

WRITE: Write operations consist of START , CYCTYPE + DIR, ADDRESS, data, TAR and SYNC fields as shown in Figure 2 and described in Table 6.

WRITE CYCLES: For write cycle s, after the address is transferred , the maste r writes the low nibble, then the high nibble of data. After that the master drives a TAR field to give ownership of the bus to the LPC. After the s ec ond cloc k of th e T A R ph ase, the target device assumes the bus and begins driving SYNC values. A TAR field to give control back to the master follows this.

Figure 2. LPC Single-byte Write Waveforms

1234567891011121314151617

CLK

LFRAME

LAD[3:0]

START

CYCTYPE

+ DIR

MADDR TAR TARSYNC

Table 6. LPC Write Cycle

Field

(1)

Clock Cycle Field Name

Contents

LAD[3:0]

AT49LL080

DATA

LAD[3:0]

Direction Comments

1 START 0000b IN LFRAME

last start field (before LFRAME

must be active (low) for the part to respond. Only the

transitioning high) should be recognized. The START field contents indicate an LPC memory write cycle.

2 CYCTYPE

+ DIR

011xb IN Cycle Type: Indicates the type of cycle. Bits 3:2 must be 01 for a

memory cycle. DIR: Bit 1 indicates the dir ect ion of the transfer (1 f o r write). Bit 0

is reserved.

3 - 10 ADDR YYYY IN These eight clock cycles make up the 32-bit memory address.

YYYY is one nibble of the entire address. Addresses are transferred most significant nibble first.

11 DATA YYYY IN This field is the least signifi can t nib ble of the data byte. Th is data

is either the data to be programmed into the Flash memory or any valid Flash command.

12 DATA YYYY IN This field is the most significant nibble of the data byte. 13 TAR0 1111b IN

then float

In this clock cycle, the master (ICH) has driven the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle”.

14 TAR1 1111b (float) Float then

OUT

The LPC takes control of the bus during this cycle. During the next clock cycle it will be driving t he “sync” data.

15 RSYNC 0000b OUT The LPC outputs the values 0000, indicating that it has received

data or a Fl ash command.

16 TAR0 1111b OUT

then Float

The LPC Flash memory drives LAD0 - LA D3 to 1111 b to indi cate a turnaround cycle.

17 TAR1 1111b (float) Float thenINThe LPC Flash memory floats its outputs , th e mast er (ICH) tak es

control of LAD3 - LAD0.

Note: 1. Field contents are valid on the rising edge of the present clock cycle.

3273C–FLASH–5/03

OUTPUT DISABLE: When the LPC is not selected through a LPC read or write cycle,

the LPC interface outputs (LAD[3:0 ]) are disabled and will be plac ed in a high -impedance state.

Bus Abort The Bus Abort operation can be used to immedi ately abo rt the cur rent bus operat ion. A

Bus Abort occurs when LFRA ME ory will tri-state the Input/Output Communication pins, LAD3 - LAD0 and the LPC state machine will reset. During a write cycle, there is the possibility that an internal Flash write or erase operation is in progress (or has just been initiated). If the LFRAME asserted during thi s time frame , the inter nal oper ation will not abort. T he s oftware m ust send an explicit Flash command to terminate or suspend the operation. The internal LPC state machi ne will not init iate a Flas h writ e or erase operat ion unti l it has r eceive d the last nibble from the chipset. This means that LFRAME cycle 12 (Table 6) and no internal Flash operation will be attempted.

HARDWARE WRITE-PROTECT PINS TBL AND WP: Two pins are available with the LPC to provide hardware write-protect capabilities.

The Top Sector Loc k (TBL ) pin is a signa l, when h eld low (acti ve), pr events pr ogram or sector erase operations in the top s ector of the device (sector 15) where critical code can be stored. When TBL The write-protect (WP the top sector. WP of the top sector.

The TBL and WP pins mus t b e s et t o th e de si red protection state prio r to s tar ti ng a program or erase operation since they are sampled at the beginning of the operation. Changing the state of TBL unpredictable results.

operates independently from TBL and does not affect the lock status

is high, hardware write protection of the top sector is disabled.

) pin serves the same function for all the remaining sectors except

is driven Low, VIL, during the bus operation; the m em-

can be asserted as late as

or WP during a program or erase operation may cause

If the state of TBL or WP changes during a program suspend or erase suspend state, the changes to the device’ s locking status do no t take place immedi ately. The suspended operation may be resumed to successfully complete the program or erase operation. The new lock status will tak e place after the program or erase ope ration completes.

These pins function in combination with the register-based sector locking (to be explained later). The se pins, when ac tive, will writ e-protect the ap propriate s ector(s), regardless of the associated sector locking registers. (For example, when TBL writing to the top sector is prevented, regardless of the state of the Write Lock bit for the top sector’s locking regis ter. In such a case, clearing the write-p rotect bit in the reg ister will have no functional effect, even though the register may indicate that the sector is no longer locked. The register may still be set to read-lock the sector, if desired.)

is active,

AT49LL080

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