ATMEL AT49LV010-12TI, AT49LV010-12TC, AT49LV010-12JI, AT49LV010-12JC, AT49HLV010-90TI Datasheet

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Features

• Single Supply Voltage, Range 2.7V to 3.6V

• Single Supply for Read and Write

• Fast Read Access Time - 55 ns

• Internal Program Control and Timer

• 8K bytes Boot Block With Lockout

• Fast Erase Cycle Time - 10 seconds

• Byte By Byte Programming - 30 µs/Byte typical

• Hardware Data Protection

• DAT A Polling For End Of Program Detection

• Low Power Dissipation

– 25 mA Active Current –50 µA CMOS Standby Current

• Typical 10,000 Write Cycles

AT49(H)BV/(H)LV01

1-Megabit (128K x 8)

Description

The AT49(H)BV010 and the AT49(H)LV010 are 3-volt-only, 1-megabit Flash memories organized as 131,072 words of 8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 µA.

To allow for simple in-system reprogrammability, the AT49(H)BV/(H)LV010 does not require high input voltages for programming. Three-volt-only comm ands determine the read and programming operation o f th e dev ic e. Re adi ng da ta out of the de vi ce i s similar to reading from an EPROM. Reprogramming the AT49(H)BV/(H)LV010 is performed by erasing the entire 1 megabit of memory and then programming on a byte by byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be op tional ly detec ted by th e DATA

polling feature. On ce the e nd of a byte progr am cycl e has be en dete cted, a new acce ss for a read or pr ogram can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

(continued)

Pin Configurations

Pin Name Function

A0 - A16 Addresses CE OE WE Write Enable

Chip Enable Output En able

Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV010 AT49HBV010 AT49LV010 AT49HLV010

™

I/O0 - I/O7 Data Inputs/Outputs NC No Connect

PLCC Top View

A12

A15

A16NCVCCWEA17

432

323130

14151617181920

I/O1

I/O2

I/O3

I/O4

I/O5

GND

29 28 27 26 25 24 23 22 21

I/O6

A14 A13 A8 A9 A11 OE A10 CE I/O7

I/O0

A11

A13 A14

VCC

A16 A15 A12

TSOP Top View

Type 1

1 2

4 5 6

7 8 9

10 11 12 13

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

0677B-A–9/97

The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is desig ned to contai n user secure code,

Block Diagram

VCC

GND

and when the featur e is en abled , the b oot s ector i s perma nently protected from being reprogrammed.

DATA INPUTS/OUTPUTS

I/O0 - I/O7

ADDRESS

INPUTS

OE, CE AND WE

LOGIC

Y DECODER

X DECODER

Device Operation

READ:

EPROM. When CE data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE high. This dual-line control gives designers flexibility in preventing bus contention.

ERASURE:

bytes memory array (or 120K bytes if the boot block featured is used ) must be era sed. The eras ed state of the memory bits is a logical “1”. The entire device can be erased at one time by us ing a 6-byte s oftware code. T he software chi p erase code c onsists of 6-b yte load co mmands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been ini tiated , the devi ce will internally time the eras e operatio n so that no ex ternal clocks are required . The ma ximum tim e needed to erase the whole chip is t been enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING:

erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed ba ck to a “1 ”; only er ase op eratio ns can co nvert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer t o the Com mand Definitions tabl e). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE latched on the rising edge of WE first. Programming is comp leted after the specifie d t cycle time. The DATA polling fe ature ma y also be us ed to indicate the end of a program cycle.

The AT49(H)BV/(H)LV010 is accessed like an

and OE are low an d WE is high, the

or OE is

Before a byte can be reprogrammed, the 128K

. If the boot block lockout feature has

Once the memory array is

or CE, whichever occurs last, and the data

or CE, whichever occurs

DATA LATCH

INPUT/OUTPUT

BUFFERS Y-GATING

MAIN MEMORY

(120K BYTES)

OPTIONAL BOOT

BLOCK (8K BYTES)

BOOT BLOCK PROGRAMMING LOCKOUT:

01FFF

00000

The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the fe ature has be en enable d. The size of the block is 8 K bytes. Thi s block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This fe ature do es not have to be activated; the boot block’ s u sa ge a s a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH.

Once the feature is enabl ed, the da ta in the bo ot block c an no longer be erased or programmed. Data i n the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to spec ific addresses wi th specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOC K LOCKOUT DET ECTION:

A software method is available to determine if programming of the boot block section is l ocked out. W hen the device is in the sof tware product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H wil l s how i f pr ogram mi ng the b oot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product i dentification code should be used to return to standard operation.

PRODUCT IDENTIFICATION:

The product identif ication mode identifies the device and manufac turer as Atmel. It may be accessed by hardwar e or softwar e operatio n. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

AT49(H)BV/(H)LV010

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

polling to indicate the end of a program cycle. Dur-

DATA

The AT49(H)BV/(H)LV010 features

ing a program cycle an attem pted read o f the last by te loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin.

polling may begin at any time during the pr ogram

DATA cycle.

TOGGLE BIT:

In addition to DATA

polling the AT49(H)BV/(H)LV 010 prov ides a nother meth od for determining the en d of a prog ram or e ras e cy cle . D uring a p rogram or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Exam ining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTI ON:

Hardware features protect against inadvertent programs to the AT49(H)BV/(H)LV010 in the following ways : (a) V sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) P r ogram inhibit: holding an y o ne o f O E

high or WE high inhibits program cycles. (c) Noise filter:

CE Pulses of le ss than 15 ns (ty pic al) on the WE

or CE inputs

will not initiate a program cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, th e address inp uts and con trol inputs (OE

and WE) may be driven from 0 to 5.5V without

CE adversely affecting the operation of the devic e. The I/O lines can only be driven from 0 to V

+ 0.6V.

Command Definition (in Hex)

Command Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Bus

Cycles

1st Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

low,

Byte Program

Boot Block Lockout

Product ID Entry

Product ID Exit

Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.

(1)

(2)

2. Either one of the Product ID exit commands can be used.

4 5555 AA 2AAA 55 5555 A0 Addr D

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 90

3 5555 AA 2AAA 55 5555 F0

1 XXXX F0

Absolute Maximum Ratings*

Temperature Under Bias......................-55°C to +125°C

Storage Temperature........ ...... ....... ...... .-65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground.........................-0.6V to +6.25V

All Output Voltages

with Respect to Ground...................-0.6V to V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This is a stress ra ting onl y and functional oper ati on of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or exten ded periods may af fect de vice reliability.

Voltage on OE

with Respect to Ground.........................-0.6V to +13.5V

DC and AC Operating Range

Operating Temperature (Case)

Power Supply

Com. Ind. AT49LV010 AT49BV010

AT49HL V

010-55

0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C

-40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C

3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V N/A N/A 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V

AT49HBV/

HLV010-70

AT49HBV/

HLV010-90

AT49BV/

LV010-12 AT49BV010-15

Operating Modes

Mode CE OE WE Ai I/O

Read V Program

(2)

Standby/Write Inhibit V

Program Inhibit X X V Program Inhibit X V Output Disable X V Product Identification

Hardware V

Software

(5)

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 1FH, Device Code: 17H.

5. See details under Software Product Identification Entry/Exit.

(1)

Ai D Ai D

XXHigh Z

X XHigh Z

A1 - A16 = VIL, A9 = VH,

A0 = V

A1 - A16 = VIL, A9 = VH,

A0 = V

A0 = VIL, A1 - A16 = V A0 = VIH, A1 - A16 = V

(3)

OUT

Manufacturer Code

Device Code

(4)

Manufacturer Code Device Code

(4)

DC Characteristics

Symbol Parameter Condition Min M ax Units

SB1

SB2

(1)

Note: 1. In the erase m ode, ICC is 50 mA.

Input Load Current VIN = 0V to V Output Leakage Current V VCC Standby Current CMOS CE = V

= 0V to V

I/O

- 0.3V to V VCC Standby Current TTL CE = 2.0V to V V

Active Current f = 5 MHz; I

OUT

= 0 mA 25 mA

10 µA 10 µA 50 µA

1mA

Input Low Voltage 0.6 V Input High Voltage 2.0 V Output Low Voltage IOL = 2.1 mA 0.45 V Output High Voltage IOH = -100 µA; VCC = 3.0V 2.4 V

AT49(H)BV/(H)LV010

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