ATMEL AT49HF010-90TI, AT49HF010-90TC, AT49HF010-90PI, AT49HF010-45JC, AT49HF010-12TI Datasheet
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AT49F010/HF010
1-Megabit
(128K x 8)
5-volt Only
CMOS Flash
Memory
AT49F010
AT49HF010
Features
•
Single Voltage Operation
- 5V Read
- 5V Reprogramming
•
Fast Read Access Time - 45 ns
•
Internal Program Control and Timer
•
8K bytes Boot Block With Lockout
•
Fast Erase Cycle Time - 10 seco nd s
•
Byte By Byte Programming - 10 µs/Byte
•
Hardware Data Protection
•
DATA Polling For End Of Program Detection
•
Low Power Dissipation
- 30 mA Active Current
- 100 µA CMOS Standby Current
•
Typical 10,000 Write Cycles
Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
The AT49F010/HF010 are 5-volt-only in-system programmable and erasable Flash
Memories. Their 1-megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45 ns (HF version) with a power dissipation of just 165 mW over the
commercial temperature range. When the device is deselected, the CMOS standby
current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F010/HF010 does not require high input voltages for programming. Five-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the AT49F010/HF010 is performed by erasing the entire 1 megabit of memory and then programming on a byte
by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle
can be optionally detected by the
DATA polling feature. Once the end of a byte pro-
Description
(continued)
DIP Top View
TSOP Top View
Type 1
PLCC Top View
0852AX–5/97
Device Operation
READ:
The AT49 F010/HF010 is accessed lik e an
EPROM. When
CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put
in the high impedance state whenever
CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
ERASURE:
Before a byte can be reprogrammed, the
128K bytes memory array (or 120K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1". The entire device can be
erased at one time by using a 6-byte software code. The
chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please
refer to the Chip Erase Cycle Waveforms).
After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is t
EC
. If the bo ot block lockout feat ure has
been enable d, the data in the boot sector will not be
erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0") on a
byte-by-byte basis. Please note that a data ”0" cannot be
programmed back to a “1"; only erase operations can convert ”0"s to “1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table).
The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling
edge of
WE or CE, whichever occurs last, and the data
latched on the rising edge of
WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cy-
Block Diagram
gram cycle has been detected, a new access for a read or
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity.
The boot sector is designed to contain user s ecure code,
cle time. The
DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device has one designated block that has a programming
lockout fea ture. This feature prev ents programming of
data in the designated block once the featur e has been
enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular
programming method. To activate the lockout feature, a
series of six program commands to specific addresses
with specific data must be performed. Please refer to the
Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identification code should be used to return to standard operation.
2
AT49F010/HF010
Temperature Under Bias.................-55°C to +125°C
Storage Temperature......................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con di t i on s be yo nd those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as A tmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49F010/HF010 features
DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin.
DATA
polling may begin at any time during the program cycle.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read
1AddrD
OUT
Chip Erase
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Byte
Program
4 5555 AA 2AAA 55 5555 A0 Addr D
IN
Boot Block
Lockout
(1)
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID
Entry
3 5555 AA 2AAA 55 5555 90
Product ID
Exit
(2)
3 5555 AA 2AAA 55 5555 F0
Product ID
Exit
(2)
1 XXXX F0
Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
TOGGLE BIT:
In addition to
DATA polling the
AT49F010/HF010 provides another method for determining the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the device will result in I/O6 tog gling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49F010/HF010 in the following ways: (a) V
CC
sense: if
V
CC
is below 3.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of
OE low, CE
high or
WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the
WE or CE inputs
will not initiate a program cycle.
AT49F010/HF010
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