ATMEL AT49F8192-90RI, AT49F8192-90RC, AT49F8192-12TI, AT49F8192-12TC, AT49F8192-12RI Datasheet

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Features

•

Single Voltage Operation

– 5V Read – 5V Reprogramming

•

Fast Read Access Time - 90 ns

•

Internal Erase/Program Control

•

Sector Architecture

– One 8K Words (16K bytes) Boot Block with Programming Lockout – Two 8K Words (16K bytes) Parameter Blocks – One 488K Words (976K bytes) Main Memory Array Block

•

Fast Sector Erase Time - 10 seconds

•

Word-By-Word Programming - 50 µs/Word

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low Power Dissipation

– 50 mA Active Current – 300 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

8-Megabit (512K x 16) 5-volt Only CMOS Flash

Description

The AT49F8192 is a 5-volt-only, 8 megabit Flash Memory organized as 512K words of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 90 ns with pow er dissipati on of just 275 mW. Wh en deselected, the CMOS standby current is less than 300 µA.

Pin Configurations

Pin Name Function

A0 - A18 Addresses CE OE WE Write Enable RESET I/O0 - I/O15 Data Inputs/Outputs NC No Connect

Chip Enable Output Enable

Reset

SOIC (SOP)

TSOP Top View

Type 1

Memory

AT49F8192 AT49F8192T

0588D-A–10/97

The device contains a u se r-e nabl ed “boot block” protection feature. Two versions of the feature are available: the AT49F8192 locates the boot block at lowest ord er addresses (“bottom boot”); the AT49F8192T locates it at highest order addresses (“top boot”).

To allow for simple in-system reprogrammability, the AT49F8192 does not require high input voltages for programming. Five-v olt-only com mands dete rmine the read and programming operation of the device. Reading data out of the de vice is simila r to read ing from an EPRO M; it has standard CE

, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F8192 is performed by first erasing a block of data and then programming on a wordby-word basis.

The device is erased by executing the erase command sequence; the device internally controls the erase opera-

Block Diagram

GND

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

DATA INPUTS/OUTPUTS

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES Y-GATING

MAIN MEMORY (488K WORDS)

PARAMETER

BLOCK 2

8K WORDS

PARAMETER

BLOCK 1

8K WORDS

BOOT BLOCK

8K WORDS

tion. The memory is div ided into three blo cks for erase operations. There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array block. The AT49F819 2 is p rogrammed on a word-by-word basis. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. Once the boot block pr ogramming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 5.5 volts or less are used. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming lock o ut featur e to pro vide data i ntegrity. The boot sector is des igned to contain us er secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.

AT49F8192 AT49F8192T

DATA INPUTS/OUTPUTS

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

7FFFF 7FFFF

06000

05FFF 04000

03FFF

02000

01FFF 00000 00000

Y-GATING

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

8K WORDS

PARAMETER

BLOCK 2

8K WORDS

MAIN MEMORY (488K WORDS)

7E000

7DFFF 7C000

7BFFF

7A000

79FFF

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs . The outputs ar e put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Comma nd Definitions ta ble (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE tively) and OE

The AT49F8192 is accessed like an EPROM .

and OE are low and WE is high, the da ta stor ed

or OE is high. This dual-line

When the device is first pow-

or CE input with CE or WE low ( respec-

high. The addre ss is latche d on the fall ing

AT49F8192/8192T

edge of CE latched by the first rising edge of CE

or WE, whichever occurs last. The data is

or WE. Standard microprocessor write timings are used. The ad dress loca tions used in the command sequences are not affected by entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is provided to eas e some sys-

is at a l ogic high le ve l, t he device is in its sta nda rd ope ra tin g mo de. A lo w level on the RESET

input halts the pre sent d evice o perati on and puts the outputs of the de vice in a hig h impeda nce sta te. When a high level is reas serted on the RESE T

pin, the device returns to the Read or Standby mo de, dependi ng upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RE SE T

pin the boot block array can be repro grammed even if the boot block program lockout feature has been enabled (see Boot Block Pro gramming Loc kout Override section).

AT49F8192/8192T

ERASURE:

be erased. The erased s tate of the memory bits i s a log ic al “1”. The entire device can be erased at one time by using a 6-byte software code.

After the software chip erase has been ini tiated , the devi ce will internally time the eras e operatio n so that no ex ternal clocks are required. The maximum time needed to erase the whole chip is t

CHIP ERASE:

the Chip Erase function is disabled; sector erases for the parameter blocks a nd ma in me mory b lock will s till op erate . After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored.

SECTOR ERASE:

the device is organized into three sectors that can be individually erased. There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array blo ck. The Secto r Erase comm and is a six bus cycle operation. The sector address is latched on the falling WE input command is latched at the rising edge of WE sector erase starts after the rising edge of WE cycle. The erase oper ation is internal ly controlled; it will automatically time to c omple tion. W hen the b oot block programming lockout featur e is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). Once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued.

WORD PROGRAMMING:

erased, it is programmed (to a logical “0”) on a word-byword basis. Programming is accomplished via the internal device command register and is a 4 bus cycle operation. The device will autom ati ca ll y ge nerate the required int ernal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle time. The DATA also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

has one designated block that has a programming lockout feature. This feature prevents programmi ng of data in the designated block once the feature has been enabled. The size of the block is 8K wo rds. This bl ock, referr ed to as the boot block, ca n conta in se cure code th at is used to brin g up the system. Enablin g the l ockout fe ature will all ow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot blo ck' s usage as a wr it e protected region is

Before a word can be reprogrammed, it must

If the boot block lockout has bee n en abl ed ,

As an alternative to a full chip erase,

edge of the sixth cycle while the 30H data

. The

of the si xth

Once a memory block is

polling feature may

The device

optional to the user. The address range of the 48F8192 boot block is 00000H to 01FFFH while the address range of the 49F8192T is 7E000H to 7FFFFH.

Once the feature is enabl ed, the da ta in the bo ot block c an no longer be erased or programmed when input levels of

5.5V or less are u sed. Dat a in the m ain mem ory bloc k can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H wil l s how i f pr ogram mi ng the b oot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the bl ock ca nnot be programmed. The software product identification exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boot block programming lockout by ta king the RES ET entire chip eras e, s ecto r era se or wor d pr ogramm ing oper ation. When the RESET the boot block programming lockout feature is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

to indicate the end of a pr ogram cy cle. Duri ng a progr am cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been comp leted, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation , an atte mpt to rea d the devi ce will g ive a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA may begin at any time during the program cycle.

TOGGLE BIT:

provides another method for determining the end of a program or erase cycle. During a pro gram or er ase opera tion, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data

The AT49F8192 features DATA

In addition to DATA

pin to 12 volts during the

pin is brought back to T TL levels

The product identif ication

polling the AT49F8 192

A software

polling

will be read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs to the AT49F8192 in the following ways: (a) V (typical), the prog ram func tion is inhi bited. (b) V on delay: once V

has reached the VCC sense level, the

Command Definition (in Hex)

Command

Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector

Erase Word

Program Boot Block

Lockout Product ID

Entry Product ID

Exit Product ID

Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows:

(2)

(3)

2. The 8K word boot sector has the address range

3. Either one of the Product ID Exit commands can be

4. SA = sector addresses:

Bus

Cycles

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

4 5555 AA 2AAA 55 5555 A0 Addr D

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 90

3 5555 AA 2AAA 55 5555 F0

1xxxxF0

I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex)

00000H to 01FFFH for the AT49F8192 and 7E000H to 7FFFFH for the AT49F8192T.

used.

For the AT49F8192 SA = 03XXX for PARAMETER BLOCK 1 SA = 05XXX for PARAMETER BLOCK 2 SA = 7FXXX for MAIN MEMORY ARRAY

sense: if VCC is below 3.8V

power

(1)

1st Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

device will au tomaticall y time out 10 ms (typical ) before programming. (c) Program inhibit: holding any one of OE low, CE high or W E high inhib its prog ram cy cles. ( d) Noise filter: pulses of les s than 15 ns (typ ical) on the W E inputs will not initiate a program cycle.

3rd Bus

Cycle

4th Bus

Cycle

For the AT49F8192T SA = 7DXXX for PARAMETER BLOCK 1 SA = 7BXXX for PARAMETER BLOCK 2 SA = 79XXX for MAIN MEMORY ARRAY

5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block w ill e rase toget her (f orm the s ame s ector eras e command). Once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued.

5th Bus

Cycle

6th Bus

Cycle

(4)(5)

or CE

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.........................-0.6V to VCC to +0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F8192/8192T

*NOTICE: Stresses beyong those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d functional oper ation of the device at thes e o r any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect de vice reliability .

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