ATMEL AT49F4096-12TI, AT49F4096-12TC, AT49F4096-12RI, AT49F4096-12RC, AT49F4096-90TI Datasheet
...
4 Megabit
(256K x 16)
5-volt Only
CMOS Flash
Memory
Preliminary
Features
(continued)
AT49F4096
Single Voltage Ope rati on
•
- 5V Read
- 5V Reprogramming
Fast Read Access Time - 90 ns
•
Internal Erase/Program Control
•
Sector Architecture
•
- One 8K Words (16K bytes) Boot Blo ck wi th Prog ram mi ng Loc ko ut
- Two 8K Words (16K bytes) Parameter Blocks
- One 232K Words (464K bytes) Main Memory Array Blo ck
Fast Sector Erase Time - 10 secon ds
•
Word-By-Word Program mi ng - 50 µ s /Word
•
Hardware Data Protection
•
DATA Polling For End Of Program Detec tio n
•
Low Power Dissipation
•
- 50 mA Active Current
- 300 µA CMOS Standby Current
Typical 10,0 00 Write Cycl es
•
Description
The AT49F4096 is a 5-volt-only, 4 megabit Flash Memory organized as 256K words
of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology,
the device offers access times to 90 ns with power dissipation of just 275 mW. When
deselected, the CMOS standby current is less than 300 µA.
AT49F4096
Pin Configurations
Pin Name Function
A0 - A17 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
RESET Reset
I/O0 - I/O15
NC No Connect
Data
Inputs/Outputs
TSOP Top View
Type 1
SOIC (SOP)
0569C
4-219
(continued)
Description (Continued)
To allow for simple in-system reprogrammability, the
AT49F4096 does not require high input voltages for programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM; it
has standard
tion. Reprogramming the AT49F4096 is performed by first
erasing a block of data and then programming on a wordby-word basis.
The device is erased by executing the erase command
sequence; the device internally controls the erase operation. The memory is divided into three blocks for erase operations. There are two 8K word par ameter block sections
and one sector consisting of the boot block and the main
CE, OE, and WE inputs to avoid bus conten-
Block Diagram
memory array block. The AT49F4096 is programmed on a
word-by-word basis.
The device has the capability to protect the data in the
boot block; this feature is en abled by a command sequence. Once the boot block programming lockout feature
is enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The typic al
number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a reprogramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
Device Operation
READ: The AT49F4096 is accessed like an EPROM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying
a low pulse on the
(respectively) and
falling edge of
is latched by the first rising edge of
microprocessor write timings are used. The address locations used in the command sequences are not affec ted by
entering the command sequences.
WE or CE input with CE or WE low
OE high. The address is latched on the
CE or WE, whichever occurs last. The data
CE or OE is high. This dual-
CE or WE. Standard
RESET: A RESET input pin is provided to ease some
system applications. When
the device is in its standard operating mode. A low level on
RESET input halts the present device operation and
the
puts the outputs of the device in a high impedance state.
When a high level is reasserted on the
device returns to the Read or Standby mode, depending
upon the state of the control inputs. By applying a 12V ±
0.5V input signal to the
can be reprogrammed even if the boot block program loc kout feature has been enabled (see Boot Block Programming Lockout Override section).
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of the memory bits is a logical
“1”. The entire device can be erased at one time by using
a 6-byte software code.
After the software chip erase has been initiated, the devic e
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
.
RESET is at a logic high level,
RESET pin, the
RESET pin the boot block array
4-220 AT49F4096
(continued)
Device Operation (Continued)
CHIP ERASE: If the boot block lockout has been en-
abled, the Chip Erase function is disabled; sector erases
for the parameter blocks and main memory block will still
operate. After the full chip erase the device will return back
to read mode. Any command during chip erase will be ignored.
SECTOR ERASE: As an alternative to a full chip erase,
the device is organized into three sectors that can be individually erased. There are two 8K word parameter block
sections and one sector consisting of the boot block and
the main memory array block. The Sector Erase command
is a six bus cycle operation. The sector addr ess is latc hed
on the falling
data input command is latched at the rising edge of
The sector erase starts after the rising edge of
sixth cycle. The erase operation is internally controlled; it
will automatically time to completion. When the boot block
programming lockout feature is not enabled, the boot
block and the main memory block will erase together (from
the same sector erase command). Once the boot region
has been protected, only the main memory array sector
will erase when its sector erase command is issued.
WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a word-byword basis. Programming is accomplished via the inter nal
device command register and is a 4 bus cycle operation.
The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset
happens during programming, the data at the location being programmed will be corrupted. Please note that a data
“0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed
after the specified t
ture may also be used to indicate the end of a program
cycle.
BOOT BLOCK PR OGRAMMING LOCKOUT: The device has one designated block that has a programming
lockout fea ture. This feature p revents programming of
data in the designated block once the feature has been
enabled. The size of the block is 8K words. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block ca n
WE edge of the sixth cycle while the 30H
WE.
WE of the
cycle time. The DATA polling fea-
BP
AT49F4096
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must
be performed. Please refer to the Command Definitions
table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been enabled and the block
cannot be programmed. The software product identification exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming
lockout by taking the
protected boot block data can be altered through a chip
erase, sector erase or word programming. When the
SET pin is brought back to TTL levels the boot block programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or softwar e oper ation. T he
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F4096 features
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the
program cycle has been completed, true data is valid on
all outputs and the next cycle may begin. During a chi p or
sector erase operation, an attempt to read the device will
give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device.
polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to
AT49F4096 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
RESET pin to 12 volts. By doing this
RE-
DATA polling
DATA
DATA p o l li n g t he
4-221
Device Operation (Continued)
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F4096 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay: once V
has reached th e VCC sense level,
CC
sense: if VCC is below 3.8V
CC
CC
power
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of
OE low, CE high or WE high inhibits program cycles. (d)
Noise filter: pulses of less than 15 ns (typical) on the
CE inputs will not initiate a program cycle.
or
WE
Command Definition (in Hex)
Command
Sequence
Read
Chip Erase
Sector
Erase
Word
Program
Boot Block
Lockout
Product ID
Entry
Product ID
(3)
Exit
Product ID
(3)
Exit
Notes: 1. The DATA FORMAT in each bus cycle is as follows:
2. The 8K word boot sector has the address range
3. Either one of the Product ID Exit commands can
4. SA = sector add resses:
Bus
Cycles
1AddrD
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA
4 5555 AA 2AAA 55 5555 A0 Addr D
(2)
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
3 5555 AA 2AAA 55 5555 90
3 5555 AA 2AAA 55 5555 F0
1xxxxF0
I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
00000H to 01FFFH.
be used.
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY
1st Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
OUT
(1)
2nd Bus
Cycle
3rd Bus
Cycle
5. When the boot block programming lockout feature
is not enabled, the boot block and the main memory block
will erase together (from the same sect or era se command).
Once the boot region has been protected, only the main
memory array sector wil l erase when its secto r erase
command is issued.
4th Bus
Cycle
5th Bus
Cycle
IN
6th Bus
Cycle
(4, 5)
30
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
4-222 AT49F4096
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
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