ATMEL AT49F1614-90TC, AT49F1614-90CI, AT49F1614-90CC, AT49F1614-70TI, AT49F1614-70TC Datasheet

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Features

•

4.5V to 5.5V Read/Write

•

Access Time - 70 ns

•

Sector Erase Architecture

– Thirty 32K Word (64K byte) Sectors with Individual Write Lockout – Eight 4K Word (8K byte) Sectors with Individual Write Lockout – Two 16K Word (32K byte) Sectors with Individual Write Lockout

•

Fast Word Program Time - 10

•

Fast Sector Erase Time - 200 ms

•

Dual Plane Organization, Permitting Concurrent Read while Prog ram/E ra se

– Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors – Memory Plane B: Twenty-Four 32K Word Sectors

•

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

•

Low Power Operation

– 40 mA Active

µµµµ

–10

A Standby

•

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

•

RESET Input for Device Initialization

•

Sector Program Unlock Command

•

TSOP, CBGA, and

•

Top or Bottom Boot Block Configuration Available

µµµµ

BGA Package Options

µµµµ

Description

The AT49F16X4(T) is a 5. 0 volt 16-megabi t Flash memory org anized as 1,048,57 6 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0

- I/O15; the x 8 da ta ap pear s on I /O0 - I /O7. The m emory is divi ded into 40 b locks for erase operations. The device i s offered in 48-pin TSO P and 48-ball µBGA packages. The device has CE can be read or reprogrammed using a single 5.0V power supply, mak ing it ideally suited for in-system programming.

, and OE control signals to avoid any bus contention. This device

(continued)

Pin Configurations

16-Megabit (1M x 16/2M x 8) 5-volt Only Flash Memory

AT49F1604 AT49F1604T AT49F1614 AT49F1614T Adv ance Information

AT49BV16X4(T)

Pin Name Function

A0 - A19 Addresses CE OE WE Write Enable RESET RDY/BUSY I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

BYTE NC No Connect DC Don’t Connect

Chip Enable Output En able

Reset READY/BUSY Out put

I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

AT49BV1604

Rev. 0977B–06/98

TSOP Top View

1 2 3 4 5 6

GFEDCB

VSS

I/O1

I/O3

I/O4

I/O6

VSS

I/O9

I/O11

VCC

I/O13

I/O15

/A-1

I/O8

I/O10

I/O12

I/O14

BYTE

I/O0

I/O2

I/O5

I/O7

A16

A19

A11

A15

A18

A10

A14

A17

RESET

A12

RDY/BUSY

A13

B C D

234567

A13

A14

A15

A16

VCC

GND

A11

A10

A12

I/O14

I/O15

I/O7

I/O5

I/O6

I/O13

RST

I/O11

I/O12

I/O4

A18

I/O2

I/O3

VCC

A19

A17

I/O8

I/O9

I/O10

I/O0

I/O1

GND

Type 1

A15 A14 A13 A12 A11 A10

A8 NC NC

RESET

A19 A18 A17

RESET

RDY/BUSY

A15 A14 A13 A12 A11 A10

A19

A18 A17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

A16

VCC

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49F1604(T)

BGA Top View (Ball Down)

TSOP T op View

Type 1

1 2 3 4 5 6 7

9 10

11 12 13

15 16 17 18

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49F1614(T)

CBGA Top View

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any se ctor. Once the d ata protection for a given sector is enabled, the data in that sector cannot be changed us ing input levels between ground and V

The device is segmented into two memory planes. Reads

from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by no t requiri ng the syst em to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it

AT49F16X4(T)

contains an Erase Suspend feature. This feature will put the Erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memo ry plane. There is no rea son to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an Erase cycle is det e cte d by t he Re ady / Bu sy

pin, Data polling, or by

the toggle bit. A six byte command (bypass unlock) sequence to remove

the requirement of entering the three byte prog ram sequence is offered to further improve programming time. After entering the six byte code, only single pulse s on the write control lines are required for writing into the device. This mode (single pulse byte/word program) is exited by

AT49F16X4(T)

powering down the device, or by pulsing the RESET low and then bringing it back to V

. Erase and Erase Sus-

pend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six byte code reside in the software of the final produ ct b ut only exist in external programming code.

The BYTE operate in the byte or word configuration. If the BYTE

pin controls whethe r the device data I/O pins

pin is

Block Diagram

I/O0 - I/O15/A-1

OUTPUT BUFFER

IDENTIFIER

A0 - A19

INPUT

BUFFER

ADDRESS

LATCH

Y-DECODER

X-DECODER

OUTPUT

MULTIPLEXER

STATUS

DATA

COMPARATOR

Y-GATING

PLANE B

SECTORS

set at logic “1”, the device is in word configuration, I/O0I/O15 are active and controlled by CE

If the BYTE

pin is set at logic “0”, the devi ce is in byte con-

and OE.

figuration, and only data I/O pins I/O0-I/O7 are active and controlled by CE

and OE. The data I/O pins I/O8-I/O14 are tri-stated, and the I/O1 5 pi n is us ed a s an inp ut for the LSB (A-1) address function.

INPUT

BUFFER

DATA

COMMAND REGISTER

WRITE STATE

MACHINE

PROGRAM/ERASE VOLTAGE SWITCH

CE WE OE RESET BYTE

RDY/BUSY

VCC GND

PLANE A SECTORS

Device Operation

READ:

When CE at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions tabl e

The AT49F16X4(T) is accessed like an EPROM.

and OE are low and WE is high, the data stored

or OE is high. This dual-line

When the device is first pow-

(I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE tively) and OE edge of CE latched by the first rising edge of CE

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is prov ided to eas e so me s ys-

is at a logic high level, the device is in its standard operating mod e. A low lev el on th e RESET

input halts the prese nt device operat ion and puts

the outputs of the de vice in a hi gh imped ance stat e. When a high level is reasse rted on the RES ET

pin, the device returns to the Read or Standby mod e, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET

pin any sector can be reprogrammed even if the sector lockout feature has been enabled (see Sector Programming Lockout Override section).

ERASURE:

Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands.

CHIP ERASE:

The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockout has been enabled, the Chip Erase will not erase the data in the secto r th at ha s be en l oc ked; it wi ll erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into forty sectors (SA0 - SA39) that can be individually erased . The Secto r Erase comm and is a six bus cycle operation. The sector ad dress is latc hed on the falling WE command is latched on the rising edge of WE erase starts after the rising edge of WE

edge of the sixth cy cle whil e the 30H d ata inpu t

. The sector

of the sixth cycle. The erase operation is i nternally controlled; it will aut omatically time to completion. The maximum time to erase a section is t

. When the sector programming lockout feature

SEC

is not enabled, the sector will erase (from the same sector erase command). Once a sector has been protected, data in the protected s ectors cannot be changed unles s the RESET

pin is taken to 12V ± 0.5V. An atte mpt to erase a sector that has bee n protected wi ll result in the operatio n terminating in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a word-by- word basis. Programming i s ac co mpl ished via the intern al device command register and is a 4 -bus cycle operation. The dev ice will autom atically ge nerate the required internal program pulses.

Any commands written to the c hip during the em bedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle time. The DATA polling feature or the

toggle bit feature may be used to indicate the end of a program cycle.

SECTOR PROGRAMMING LOCKOUT:

Each sector has a programming lockout feature. This feature prevents programming of data in the des ignated sector s once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockout feature will all ow the boot c ode to stay i n the device while data in the rest of the device is upd ated. Thi s feat ure does not have to be activated; any sector’s usage as a write protected region is optional to the user.

Once the feature is enabled, the data in the protected sectors can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the remaining sectors can still be changed through the regular programming method. To activate the lo ck ou t fea tur e, a ser ies of s ix pr ogram commands to specific addresses with specific data must be performed. P lease refer to the Co mmand Defin itions table.

SECTOR PROGRAMMING LOCKOUT OVERRIDE:

The user can override the sector programming lockout by taking the RESET

pin to 12V ± 0.5V. By doing this prote cted da ta can be altered through a chip erase, sector era se or byte/word program ming. When the RESET

pin is brought back to TTL level s the secto r programm ing loc kout featu re is again active.

ERASE SUSPEND/ERASE RESUME:

The erase suspen d command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual plane architecture, there is no need to use the erase suspend feature while erasin g a sec tor when y ou want to r ead data from a sector in the other plane. After the erase suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane which contains the suspended s ector enter s the erase-s uspend-r ead mode. The system can then read data or program da ta to any other sector within the device. An address is not required during the erase suspend comm and. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the erase resume command. The erase resume command is a one bus cy cle co mma nd, whi c h d oes req ui re the p lan e address (determined by A18 and A19). The device also supports an erase suspend during a complete chip erase. While the chip erase is sus pended, the use r can read from any sector within the me mory that is protec ted. The command sequence for a chip erase suspen d and a sector erase suspend are the same.

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

AT49F16X4(T)

For details, see O peratin g Modes (for har dware operatio n) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

The AT49F16X4(T) features DATA

polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and th e next cyc le may be gin. Du ring a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device.

polling may begin at any time during the program

DATA cycle. Please see “Status Bit Table” for more details.

TOGGLE BIT:

In addition to DATA

polling the AT49F16X4(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

An additional to ggle bit is available on I/O2 whi ch can be used in conjunction with the toggle bit which is available on I/O6. While a sector is erase suspe nded, a read or a pro-

gram operation fr om t he suspended sector wi ll re su lt in th e I/O2 bit toggling. Please s ee “Status Bit Table” for more details.

RDY/BUSY

An open drain READY/BUSY

output pin provides another method of detectin g the end of a progr am or erase operation. RDY/BUSY

is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY

HARDWARE DATA PROTECTION:

line.

Hardware features protect against in adverten t pro grams to the A T49F16X4 (T) in the following ways: (a) V (typical), the program function is inhibited. (b) V delay: once V

has reached the VCC sense level, the

sense: if VCC is below 3.8V

power on

device will au tomaticall y time out 10 ms (typical) be fore programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inh ibits pr ogram cycle s. (d) No ise filter: pulses of les s than 15 ns (typ ical) on the W E

or CE

inputs will not initiate a program cycle.

INPUT LEVELS:

While operating with a 4.5V to 5.5V

power supply, th e address inpu ts and cont rol inputs (OE

, and WE) may be dr iven from 0 to 5.5V without

CE adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V

+ 0.6V.

Command Definition in (Hex)

(1)

1st Bus

Command Sequence

Bus

Cycles

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

(3)(4)

Bypass Unlock 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0 Single Pulse

Byte/Word Program Sector Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

1 Addr D

(3)(4)

Erase Suspend 1 xxxx B0 Erase Resume 1 PA

(5)

30 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit Product ID Exit

(2)

3 5555 AA 2AAA 55 5555 F0 1 xxxx F0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next four pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET

pin is taken to

12V ± 0.5V.

5. PA is the plane address (A19 - A18).

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F16X4(T)

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d functional oper ation of the device at these o r any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect de vice reliability .

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