ATMEL AT49F1025-90VI, AT49F1025-90VC, AT49F1025-90JI, AT49F1025-90JC, AT49F1025-70VI Datasheet

Features

Single Voltage Operation

•

– 5V Read
– 5V Reprogramming

Fast Read Access Time - 45 ns

•

Internal Program Control and Timer

•

8K word Boot Block With Lockout

•

Fast Erase Cycle Time - 10 seconds

•

Word By Word Programming - 10

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Small 10 x 14 mm VSOP Package

•

Typical 10,000 Write Cycles

•

µµµµ

s/Word Typical

1-Megabit
(64K x 16)

Description

The AT49F1024 and the AT49F1025 ar e 5-v olt -o nly in -sy stem Fla sh Mem or ies . The ir
1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45
ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA. The
only differenc e between th e AT49F1024 and the AT4 9F1025 is th e pinout. T he
AT49F1024 is pin compatable with the AT27C1024, and the AT49F1025 is pin com­patable with the AT29C1024.

Pin Configurations

Pin Name Function

A0 - A15 Addresses
CE
OE Output Enable
WE
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect

AT49F1025 VSOP Top View

A0
A1
A2
A3
A4
A5
A6
A7
A8

GND

A9
A10
A11
A12
A13
A14
A15

NC

WE

VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Chip Enable

Write Enable

Type 1

10 x 14 mm

10 x 14 mm

AT49F1024 VSOP Top View

Type 1

10 x 14 mm

1

A9

2

A10

3

A11

4

A12

5

A13

6

A14

7

A15

8

NC

9

WE

10

VCC

11

NC

12

CE

13

I/O15

14

I/O14

15

I/O13

16

I/O12

17

I/O11

18

I/O10

19

I/O9

20

I/O8

40

OE

39

I/O0

38

I/O1

37

I/O2

36

I/O3

35

I/O4

34

I/O5

33

I/O6

32

I/07

31

GND

30

I/O8

29

I/O9

28

I/O10

27

I/O11

26

I/O12

25

I/O13

24

I/O14

23

I/O15

22

NC

21

CE

I/O12
I/O11
I/O10

GND

PLCC Top View

I/O13

I/O14

I/O15CENCNCVCCWENC

65432
7
8
9
10

I/O9

11

I/O8

12
13

NC

14

I/O7

15

I/O6

16

I/O5

17

I/O4

1819202122232425262728

I/O3

I/O2

I/O1

I/O0

1

OE

DC

4443424140

A0A1A2A3A4

(continued)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A15

A14

39

A13

38

A12

37

A11

36

A10

35

A9

34

GND

33

NC

32

A8

31

A7

30

A6

29

A5

GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND

5-volt Only
Flash Memory

AT49F1024
AT49F1025

Rev. 0765D–09/98

1

To allow for simple in-system reprogrammability, the
AT49F1024/1025 does not requir e high input voltage s for
programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F1024 /1025 is performed by
erasing a block of da ta (entir e chip or ma in memo ry block)
and then programming on a word by word basis. The typi­cal word programming time is a fast 10 µs. The end of a
program cycle can be optionally detected by the DATA

poll-

Block Diagram

V

CC

GND

ing feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.

The optional 8K words boot block section in clude s a repro­gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the featur e is en abled, the bo ot sec tor is per ma­nently protected from being erased or reprogrammed.

DATA INPUTS/OUTPUTS

I/O15 - I/O0

16

OE

WE

CE

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

Device Operation

READ:

EPROM. When CE
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE
high. This dual-line con tr ol gi v es d esign er s fl ex ibi lit y in pr e­venting bus contention.

CHIP ERASE:

feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase com­mand (See command definitions table). If the boot bl ock
lockout function has been enabled, data in the boot section
will not be erased. Howe ver, data in the main mem or y se c­tion will be erased. After a chip erase, the device will return
to the read mode.

MAIN MEMORY ERASE:

erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latche d on the rising edge of

The AT49F1024/10 25 is accessed like an

and OE are low and WE is high, th e

or OE is

When the boot block programming lockout

As an alternative to the chip

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K WORDS)

OPTIONAL BOOT

BLOCK (8K WORDS)

. The main memory erase starts aft er the risi ng edge of

WE

of the sixth cycle. P lease see Main Mem ory Erase

WE

1FFFH

0000H

cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.

WORD PROGRAMMING:

Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con­vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatic ally gen erate the required internal
program pulses.

The program cyc le has address es latched on the falling
edge of WE
latched on the rising edge of WE
first. Programming is completed after the specified t
time. The DATA

or CE, whichever occurs last, and the data

or CE, whichever occurs

cycle

BP

polling feature may also be us ed to indi-

cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in th e
designated block once the feature has been enabled. The

2

AT49F1024/1025

AT49F1024/1025

size of the block is 8K words. Thi s blo ck, refe rred to as th e
boot block, can contain secure code that is used to bring up
the system. Enablin g the lo ckou t featur e will al low the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti­vated; the boot block’s us ag e as a wr i te protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.

Once the feature is enabled, the data in th e boot blo ck ca n
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro­gramming method and can be er ased using ei ther the chip
erase or the main memory block erase command. To acti­vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot
block section is locked out. When the device is in the soft­ware product ident ification mode (s ee Software Produ ct
Identification Entry and Exit sections) a read from address
location 0002H will show if programming the boot block is
locked out. If the da ta o n I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock­out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-

The product identificatio n

A software

grammer to identify the correct programming algorithm for
the Atmel product.

For details, see O perat ing Mode s (for ha rdware operat ion)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

polling to indicate the end of a program or erase cycle.
During a program cycle an attempted read of the last byte
loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true
data is valid on all output s and the nex t cycle ma y begin.

polling may begi n at any time during the pr ogram

DATA
cycle.

TOGGLE BIT:

AT49F1024/1025 provides anothe r method for determi ning
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog­gling and valid data will be read. Exami ning the to ggle bit
may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the
AT49F1024/1025 in the following ways: (a) V

is below 3.8V (typical), the program function is inhib-

V

CC

ited. (b) Program inhi bit: holding a ny one of OE
high or WE high inhibits progr am cycles. (c) No ise filter:
Pulses of less than 15 ns (typical) on the WE
will not initiate a program cycle.

The AT49F1024/1025 features DATA

In addition to DATA

polling the

Hardware features

sense: if

CC

low, CE

or CE inputs

3

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Main Memory Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 30
Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D
Boot Block Lockout
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

(3)

(3)

2. The 8K word boot sector has the address range 00000H to 1FFFH.

3. Either one of the Product ID Exit commands can be used.

Bus
Cycles

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0
1xxxxF0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

IN

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature Under Bias................................-55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the device at thes e o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

4

AT49F1024/1025