ATMEL AT49F1024A User Manual

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Features

• Single-voltage Operation

–5V Read – 5V Reprogramming

• Fast Read Access Time – 45 ns

• Internal Program Control and Timer

• 8K Word Boot Block with Lockout

• Fast Erase Cycle Time – 1.5 seconds

• Word-by-word Programming – 10 µs/Word Typical

• Hardware Data Protection

• Data Polling for End of Program Detection

• Small 10 x 14 mm VSOP Package

• Typical 10,000 Write Cycles

1-megabit (64K x 16)

Description

The AT49F1024A is a 5-volt-only in-system Flash memory organized as 65,536 words by 16 bits. Manufactured w ith Atmel ’s advance d nonvolatile CMO S techno logy, the devices offer access times to 45 ns with power dissipation of just 275 mW over the commercial temp erature range. Whe n the device is desele cted, the CMOS stand by current is less than 100 µA.

To allow for simple in-system reprogrammability, the AT49F1024A does not require

high-input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading da ta out of th e device is simila r to reading from an EPROM. Reprogramming the A T49F1024A is performed by erasing a block of data (entire chip or main memory block) and then programming on a word-byword basis. The typical word p rogramming t ime is a fast 10 µs. T he end of a program cycle can be optionally detected by the Data program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

Pin Configurations

Pin Name Function

A0 - A15 Addresses CE OE Output Enable WE I/O0 - I/O15 Data Inputs/Outputs NC No Connect

Chip Enable

Write Enable

Polling feature. Once the end of a byte

VSOP Top View

Type 1

10 x 14 mm

A10 A11 A12 A13 A14 A15

VCC

I/O15 I/O14 I/O13 I/O12 I/O11 I/O10

I/O9 I/O8

2 3 4 5 6 7 8

9 10 11

13 14 15 16 17 18 19 20

GND

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

5-volt Only Flash Memory

AT49F1024A

3415B–FLASH–12/03

Block Diagram

The optional 8K word boot block section includes a reprogramming write lockout feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.

DATA INPUTS/OUTPUTS

VCC

GND

I/O15 - I/O0

Device Operation

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K WORDS)

OPTIONAL BOOT

BLOCK (8K WORDS)

FFFFH

2000H 1FFFH

0000H

READ: The AT49F1024A is accessed like an EPROM. When CE and OE are low and

is high, the data stored at the memory location determined by the address pins is

WE asserted on the outputs. The ou tputs ar e put in the high impedan ce stat e whenev er CE or OE is high. This dual line control giv es designers flexibility in preventing bus contention.

CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the m ain memor y block will eras e together fr om the s ame Chip Er ase command (See Command Def initio ns tabl e). If the boot block lockout function has bee n enabled, data in the boot s ec tio n wil l not be er as ed. Howev er, d ata i n the mai n m emo ry section will be erased. After a chip erase, the device will return to the read mode.

MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation . The address (555H) is latche d on the fal li ng edg e o f the si xth c y cle wh il e th e 30 H da ta i np ut is latched on the rising edge of WE

of the sixth cycle. Please see main mem ory erase cycl e waveforms. The main

of WE

. The main memory erase starts after the risi ng edg e

memory erase operation is internally controlled; it will automatically time to completion. WORD PROGRAMMING: Once the memory array is erased, the device is programmed

(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via th e internal device command register a nd is a four-bus cycle operation (please refer to the Comma nd Defi ni tion s tab le). T he dev ice wi ll automa tical ly generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE occurs last, and the data latched on the rising edge of WE Programming is completed after the specified t

cycle time. The Data Polling feature

or CE, whichever occurs first.

or CE, whichever

may also be used to indicate the end of a program cycle.

AT49F1024A

3415B–FLASH–12/03

AT49F1024A

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block

that has a programming lockout feature. This feature prevents programming of data in the designated bl ock once th e feature has been enabl ed. The siz e of the block is 8K words. This block, referr ed to as the boot bloc k, can c onta in secur e co de tha t is use d to bring up the system. Enab ling the l ockout featu re will allo w the boot cod e to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write-protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH.

Once the feature is en abled, the dat a in th e boot b lock c an no l onger be eras ed or pr ogrammed. Data in the ma in memory blo ck can still be ch anged through the regular programming method an d c an be eras ed us in g e ith er th e Ch ip Er as e or th e M ai n M emory Block Eras e command. To activate the lockout featur e, a series of six pr ogram commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boo t block section is lock ed out. When the device is in the s oftware product identification mode (see Software Produc t Identification Entry and Exit sections), a read from address location 0002H will show if programming the boot block is locked out. If the data on I/O 0 is lo w, th e boot block can b e pro gramm ed; if the da ta on I/O0 is high, the prog ram lockout fea ture has been activated and the bl ock can not be programmed. The software product identification exit code should be used to return to standard operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atm el product.

For details, see Ope rating M odes ( for h ardware operatio n) or Software Prod uct Identi fication. The manufacturer and device code is the same for both modes.

POLLING: The AT49F1024A features Data Polling to indicate the end of a pro-

DAT A

gram or erase cycle. During a progra m cycle , an attem pted re ad of the l ast byte lo aded will result in the compleme nt of the loaded data on I/O7. O nce the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data Polling may begin at any time during the program cycle.

TOGGLE BIT: In addition to Data determining the end of a prog ram or erase cycl e. During a prog ram or erase oper ation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Exami ning the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F1024A in the following ways: (a) V (typical), the program function is inhibite d. (b) Program i nhibit: holdi ng any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

Polling, the AT49F1024A provides another method for

sense: if VCC is below 3.8V

3415B–FLASH–12/03

Command Definition (in Hex)

1st Bus

Command Sequence

Bus

Cycles

Read 1 Addr D

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

Chip Erase 6 555 AA AAA

2nd Bus

Cycle

(2)

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

55 555 80 555 AA AAA 55 555 10 Main Memory Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 555 30 Word Program 4 555 AA AAA 55 555 A0 Addr D Boot Block

Lockout

(3)

6 555 AA AAA 55 555 80 555 AA AAA 55 555 40

Product ID Entry 3 555 AA AAA 55 555 90 Product ID Exit Product ID Exit

(4)

3 555 AA AAA 55 555 F0 1xxxF0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A11 - A0 (Hex); A11 - A15 (Don’t Care).

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. The 8K word boot sector has the address range 0000H to 1FFFH.

4. Either one of the Product ID Exit commands can be used.

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This i s a stress r at ing onl y and functional operati on of the de vic e at these or an y other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F1024A

3415B–FLASH–12/03

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