ATMEL AT49F080T-90TI, AT49F080T-90TC, AT49F080T-90RI, AT49F080-12RC, AT49F080-12CI Datasheet

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Features

•

Single Voltage Operation

– 5V Read – 5V Reprogramming

•

Fast Read Access Time - 90 ns

•

Internal Program Control and Timer

•

16K bytes Boot Block With Lockout

•

Fast Erase Cycle Time - 10 seconds

•

Byte-By-Byte Programming - 10 µs/Byte Typical

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low Power Dissipation

– 50 mA Active Current – 100 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

Description

The AT49F080 is a 5-volt-only in-system Flash Memory device. Its 8-megabits of memory is organized as 1,024,576 words by 8-bits. Manufactured with Atmel’s advanced nonvolati le CMO S te ch nol ogy , the dev ice off er s acce ss ti me s to 90 ns wi th power dissipation of just 27 5 mW ove r the commer cial tem perat ure range . When the device is deselected, the CMOS standby current is less than 100 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available: the AT49F080 locates the boot block at lowest order addresses (“bottom b oot”) ; th e A T49F08 0T locates it at highest or de r addr e sses ( “top boot”).

8-Megabit (1M x 8) 5-volt Only Flash Memory

AT49F080 AT49F080T AT49F080/080T

0584B-A–8/97

Pin Configurations

Pin Name Function

A0 - A19 Addresses CE

Chip Enable OE Output Enable WE

Write Enable RESET

Reset RDY/BUSY Ready/Busy Outpu t I/O0 - I/O7 Data Inputs/Outputs NC No Connect

CBGA Top View

A B C D E F

234567

A5 A4 A6 A3 A2 A1

A8 A7 A9

I/O1

I/O0

A11 A10 RST

NC I/O3 I/O2

VCC

CE VCC GND GND

A12 A13 A14 I/O4 I/O6 I/O5

A15

NC A16 I/O7

RY/BY

A17 A18 A19

NC NC

(continued)

SOIC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

RESET

A11 A10

A9 A8 A7 A6 A5

A4 NC NC

I/O0 I/O1 I/O2

I/O3 GND GND

VCC CE A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE OE RDY/BUSY I/O7 I/O6 I/O5 I/O4 VCC

TSOP Top VIew

Type 1

A17

A16 A14

A15

A12

A13

A10

RESET

A11

VCC

I/O2

I/O3 I/O1

I/O0

VCC

I/O4 GND

GND

I/O6

I/O5

RDY/BUSY

I/O7

32 30

36 34

19 A2

2417

A19

A18

AT49F080/080T

To allow for simple in-system reprogrammability, the AT49F080 does not require high input voltages for programming. 5-volt-only commands determine the read and programming operat ion o f t he de vice . Rea ding data out of the device is simi lar to r eading f rom an EPROM . Repr ogramming the AT49F080 is performed by erasing the entire 8 megabits of memory and then programming on a byte-bybyte basis. The typical by te programm ing tim e is a fast 10 µs. The end of a p rogr am cy cle ca n be op tionally detected by the DATA

polling feature. Once the end of a byte pro-

gram cycle has be en dete cted, a n ew acce ss for a rea d or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles

The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is des igned t o contain us er secure code, and when the feature i s en abled, the b oot se ctor is per manently protected from being reprogrammed.

Block Diagram

Device Operation

READ:

The AT49F080 is accessed like an EPROM.

When CE

and OE are low and WE is high, the da ta stored at the memory location determined by the add ress pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE

or OE is high. This dualline control gives designers flexibility in preventing bus contention.

ERASURE:

Before a byte can be reprogrammed, the 1024K bytes memory array ( or 1008K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at on e time b y using a 6-byte s oftw are code . The software chip erase code consists of 6-byte load commands to specific addr ess locations wi th a specific data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been ini tiated , the devi ce will internally time the eras e operatio n so that no ex ternal clocks are required. The maximum time needed to era se the whole chip is t

. If the boot block lock out feat ure has been enabled, the data in the boot sector will not be erased.

BYTE PROGRAM MING:

Once the memory array is

erased, the device is programmed (to a logical “0 ”) on a

byte-by-byte basis. Please note that a data “0” cannot be programmed ba ck to a “1” ; only er ase oper ation s can con vert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions ta ble ). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE

or CE, whichever occurs last, and the data

latched on the rising edge of WE

or CE, whichever occurs

first. Programming is completed after the specified t

cycle time. The DATA polling feature may also be use d to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block onc e the featu re has been en abled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is update d. This fe ature do es not have to be activated; the boot block 's us age as a wr ite prote ct ed r e gio n i s

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(1008K BYTES)

ADDRESS

INPUTS

GND

DATA INPUTS/OUTPUTS

I/O7 - I/O0

03FFFH

00000H

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(1008K BYTES)

FC000H

00000H

AT49F080TAT49F080

DATA INPUTS/OUTPUTS

I/O7 - I/O0

FFFFFH FFFFFH

AT49F080/080T

optional to the user. The address range of the AT49F080 boot block is 00000H to 03FFFH while the address range of the AT49F080T boot block is FC000H to FFFFFH.

To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

A software method is available to determine if programming of the boot block section is l ocked ou t. Whe n the device is in the so ftware product iden tification mode (see Soft ware Product Identification Entry and Exit sections) a read from address location 00002H will show if program ming the boot bloc k is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identific ati on exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boot block programming

lockout by taking the RESET

pin to 12V ± 0.5V. By doing this, protected boot block data can be altered through a chip erase, or byte programming. When the RESET

pin is brought back to TTL levels, the boot block programming lockout feature is again active.

PRODUCT IDENTIFICATION:

The product identi fication mode identifies the device and manufactur er as Atmel. It may be accessed by ha rdware or softwar e operatio n. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

The AT49F080 features DATA

polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been com pleted, true data is valid on all outputs and the next cycle may begin. DATA

polling may

begin at any time during the program cycle.

TOGGLE BIT:

In addition to DATA

polling, the AT49 F080 provides another method for determining the end of a program or erase cycl e. Du ring a pr ogram o r er ase op era tion, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

RDY/BUSY

An open drain READY/BUSY

output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY

is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain

connection allows fo r OR - tyi ng of sever al device s to the same RDY/BUSY

line.

RESET:

A RESET

input pin is provided to ease some sys-

tem applications. When RESET

is at a logi c high lev el, th e device is in its sta nda rd ope rating mode. A low level on the RESET

input halts the present de vice opera tion and puts the outputs of the device in a high impedance state. If the RESET

pin makes a high to low transition during a program or erase operation, the operation may not be successful ly completed and the op eration wi ll have to be repeated after a high level is applied to the RESET

pin. When a high level

is reasserted on the RESET

pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET

pin, the boot block array can be reprogrammed even if the boot block lockout fea ture has been ena bled (see Boot Block Programming Lockout Override section).

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs to the AT49F080 in the following ways: (a) V

sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE

low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a pro-

gram cycle.

AT49F080/080T

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice. Th is is a stress rating only an d functional operati on of the de vi ce at these or an y other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or extended periods ma y affect d evice reliability .

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground............................-0.6V to V

+ 0.6V

V o ltage on OE

with Respect to Ground...................................-0.6V to +13.5V

Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F080 and FC000H to FFFFFH for the

AT49F080T.

2. Either one of the Product ID Exit commands can be used.

Command Definition (in Hex)

Command Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Byte Program 4 555 5 AA 2AAA 55 5555 A0 Addr D

Boot Block Lockout

(1)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit

(2)

3 555 5 AA 2AAA 55 5555 F0 Product ID Exit

(2)

1 XXXX F0

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