ATMEL AT49F040-70TI, AT49F040-70TC, AT49F040-70PI, AT49F040-70PC, AT49F040-70JI Datasheet

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Features

Single Voltage Operation

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– 5V Read – 5V Reprogramming

Fast Read Access Time - 70 ns

•

Internal Program Control and Timer

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16K bytes Boot Block With Lockout

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Fast Erase Cycle Time - 10 seconds

•

Byte By Byte Programming - 50 µs/Byte

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Hardware Data Protection

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DAT A Polling For End Of Program Detection

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Low Power Dissipation

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– 50 mA Active Current – 100 µA CMOS Standby Current

Typical 10,000 Write Cycles

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4-Megabit (512K x 8) 5-volt Only

Description

The AT49F040 is a 5-vol t-only in -syste m Flash Memor y. Its 4 mega bits of mem ory is organized as 524,288 words by 8 bits . Manufa ctured wi th Atme l’s a dvanced n onvolatile CMOS technology , the d evice of fers acc ess tim es to 7 0 ns wi th powe r dissipa tion of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available: the AT49F040 locates the boot block at lowest order addresses (“bottom b oot ”); t he A T 49F0 40T l ocate s i t a t hi ghe st or der a ddres se s (“to p boot”).

Pin Configurations

Pin Name Function

A0 - A18 Addresses CE OE WE Write Enable I/O0 - I/O7 Data Inputs/Outputs

Chip Enable Output Enable

DIP Top View

(continued)

CMOS Flash Memory

AT49F040 AT49F040T AT49F040/040T

AT49F040/040T

PLCC Top View

TSOP Top View

Type 1

Rev. 0998A-A–01/98

To allow for simple in-system reprogrammability, the AT49F040 does not require high input voltages for programming. Five-volt-onl y commands de termine the rea d and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F040 is performed b y erasing the entire 4 megabits of memory and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA

polling feature. Once the end of a

Block Diagram

DATA INPUTS/OUTPUTS

GND

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

BLOCK (16K BYTES)

byte program cycle h as be en dete cted, a new acces s for a read or program can begin. The typical num ber of prog ram and erase cycles is in excess of 10,000 cycles.

The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the featur e is en abled, the bo ot sec tor is per manently protected from being reprogrammed.

AT49F040TAT49F040

DATA INPUTS/OUTPUTS

I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT

BUFFERS Y-GATING

MAIN MEMORY

(496K BYTES)

OPTIONAL BOOT

7FFFFH 7FFFFH

03FFFH

00000H

I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT

BUFFERS Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(496K BYTES)

7C000H

00000H

Device Operation

READ:

CE memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

ERASURE:

512K bytes memory array (or 496K bytes if the boot block featured is used) mus t be erased. The erased stat e of the memory bits is a logical “1”. The entire device can b e erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specifi c address locatio ns with a specif ic data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software c hi p e rase h as b een i niti ate d, the d evi c e will internally time the er ase operation so that no e xternal clocks are required. The maximum time needed to erase the whole chip is t been enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING:

the device is pr ogramme d (to a logica l “0”) on a by te-bybyte basis. Please note that a data ”0" cannot be pro-

The AT49F040 is accessed like an EPROM. When

and OE are low and WE is hig h, the d ata sto red at the

or OE is high. This dual-line

Before a byte can be reprogrammed, the

. If the boot block lockout feature has

Once the memory array is erased,

grammed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register an d is a 4 bus c ycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.

The program cyc le has address es latched on the falling edge of WE latched on the rising edge of WE first. Programming is completed after the specified t time. The DATA

or CE, whichever occurs last, and the data

or CE, whichever occurs

cycle

polling feature may also be us ed to indi-

cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block that has a programming lockout feature. This feature prevents programming of data in th e designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enablin g the l ockou t feature w ill al low the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block 's us age as a write pr otec te d reg ion is optional to the user. The address range of the AT49F040

AT49F040/040T

boot block is 00000H to 03FFFH while t he address r ange of the AT49F040T boot block is 7C000H to 7FFFFH.

Once the feature is enabled, the data in th e boot blo ck ca n no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activa te the loc kout fea t ure, a se ries of six program commands to specific addresses with s pecific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product ident ification mode (s ee Software Produ ct Identification Entry and Exit sections) a read from address location 00002H will s how if pro gramm ing the bo ot block is locked out. If the da ta o n I/O 0 is lo w, th e bo ot b loc k c an b e programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see O peratin g Modes (for har dware operatio n) or Software Product Identification. The manufacturer and device code is the same for both modes.

The product identification

A software

DATA POLLING:

indicate the end of a pr ogram cycle. Dur ing a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA begin at any time during the program cycle.

TOGGLE BIT:

provides another method for determining the end of a program or erase cycle. During a prog ram or eras e operation , successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the AT49F040 in the following ways: (a) V ical), the program function is inhibited. (b) Program inhibit: holding any one of OE program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE cycle.

The AT49F040 features DATA

In addition to DATA

sense: i f VCC is below 3.8V (typ-

low, CE high or WE h igh inhi bits

or CE inputs will not initiate a program

polling the AT49 F040

Hardware features

polling to

polling may

Command Definition (in Hex)

Command Sequence

Read 1 Addr D Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D Boot Block Lockout Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit Product ID Exit

Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F040 and 7C000H to 7FFFFH for the

AT49F040T.

2. Either one of the Product ID exit commands can be used.

(1)

(2)

Bus

Cycles

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0 1 XXXX F0

1st Bus

Cycle

Addr Data Ad dr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature Under Bias................................-55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F040/040T

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device . This is a st ress rating only and functional operatio n of the dev ice at th ese or an y other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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