ATMEL AT49F040 User Manual
4 Megabit
(512K x 8)
5-volt Only
CMOS Flash
Memory
Preliminary
AT49F040
0359C
查询AT49F040-12JI供应商查询AT49F040-12JI供应商
Features
Single Voltage Ope rati on
•
- 5V Read
- 5V Reprogramming
Fast Read Access Ti me - 90 ns
•
Internal Program Control and Timer
•
16K bytes Boot Block With Lockout
•
Fast Erase Cycle Tim e - 10 se co nds
•
Byte By Byte Programming - 50 µs/Byte
•
Hardware Data Protection
•
DATA Polling For End Of Program De tec tio n
•
Low Power Dissipation
•
- 50 mA Active Current
- 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
•
Description
The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is
organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 90 ns with power dissipation
of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F040 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F040 is performed by erasing
the entire 4 megabits of memory and then programming on a byte by byte basis. The
byte programming time is a fast 50 µs. The end of a program cycle can be optionally
detected by the
detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
DATA polling feature. Once the end of a byte program cycle has been
(continued)
DIP Top View
Pin Configurations
AT49F040
Pin Name Function
A0 - A18 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
PLCC Top View
TSOP Top View
Type 1
4-209
Description (Continued)
The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure
Block Diagram
Device Operation
READ: The AT49F040 is accessed like an EPROM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control giv es designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the
512K bytes memory array (or 496K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1". The entire device can be
erased at one time by using a 6-byte software code. The
software chip eras e code consists of 6-byte load commands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the devic e
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
been enable d, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0") on a
byte-by-byte basis. Please note that a data ”0" cannot be
programmed back to a “1"; only erase operations can convert ”0"s to “1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table).
The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling
edge of
latched on the rising edge of
first. Programming is completed after the specified t
WE or CE, whichever occurs last, and the data
. If the boot block lockout feature has
EC
CE or OE is high. This dual-
WE or CE, whichever occurs
cy-
BP
code, and when the feature is enabled, the boot sector is
permanently protected from being reprogrammed.
cle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming
lockout fea ture. This feature p revents programming of
data in the designated block once the feature has been
enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address r ange
of the boot block is 00000H to 03FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular
programming method. To activate the lockout feature, a
series o f six program commands to specific addresses
with specific data must be performed. Please refer to the
Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identification code should be used to return to standard operation.
(continued)
4-210 AT49F040
Device Operation (Continued)
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F040 features
DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the
program cycle has been completed, true data is valid on
all outputs and the next cycle may begin.
DATA polling
may begin at any time during the program cycle.
Command Definition (in He x)
AT49F040
TOGGLE BIT: In addition to
provides another method for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at
any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F040 in
the following ways: (a) V
(typical), the program function is inhibited. (b) Program inhibit: holding any one of
hibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the
program cycle.
DATA polling the AT49F040
sense: if VCC is below 3.8V
CC
OE low, CE high or WE high in-
WE or CE inputs will not initiate a
Command
Sequence
Read
Chip Erase
Byte
Program
Boot Block
Lockout
Product ID
Entry
Product ID
(2)
Exit
Product ID
(2)
Exit
Note: 1. The 16K byte boot sector ha s the address range 00000H to 03FFFH .
2. Either one of the Product ID exit commands can be used.
(1)
Bus
Cycles
1AddrD
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
4 5555 AA 2AAA 55 5555 A0 Addr D
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
3 5555 AA 2AAA 55 5555 90
3 5555 AA 2AAA 55 5555 F0
1 XXXX F0
1st Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
OUT
2nd Bus
Cycle
3rd Bus
Cycle
Absolute Maximum Rat ings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
4th Bus
Cycle
5th Bus
Cycle
IN
6th Bus
Cycle
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
+ 0.6V
CC
Voltage on OE
with Respect to Ground .................. -0.6V to + 13.5V
*NOTICE: Stresses beyond those listed unde r “Absolu te Maxi-
mum Ratings” may cause permanent da ma ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
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