ATMEL AT49F008-90TI, AT49F008-90TC, AT49F008-15TI, AT49F008-15TC, AT49F008-12TC Datasheet

Features

•

Single Voltage Operation

– 5V Read
– 5V Reprogramming

•

Fast Read Access Time - 90 ns

•

Internal Program Control and Timer

•

16K bytes Boot Block With Lockout

•

Fast Erase Cycle Time - 10 seconds

•

Byte-By-Byte Programming - 10 µs/Byte Typical

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low Power Dissipation

– 50 mA Active Current
– 100 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

8-Megabit
(1M x 8)
5-volt Only

Description

The AT49F008 is a 5-volt-o nly in-sys tem Flash Me mory devi ce. Its 8- megabits of
memory is organized as 1,024,576 words by 8-bits. Manufactured with Atmel’s
advanced nonvol atile CMOS technology, the de vi ce of fer s ac ce ss t ime s to 90 ns wi th
power dissipatio n of just 27 5 mW ove r the co mmercia l temper atur e range . When the
device is deselected, the CMOS standby current is less than 100 µA.

(continued)

Pin Configurations

Pin Name Function

A0 - A19 Addresses
CE
OE
WE Write Enable
RESET
RDY/BUSY
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

Chip Enable
Output Enable

Reset
Ready/Busy Output

TSOP Top VIew

Type 1

Flash
Memory

AT49F008

A16
A15
A14
A13
A12
A11

RESET

RDY/BUSY

A18

1
2
3
4
5
6
7

A9

8

A8

9

WE

10
11

NC

12
13
14

A7

15

A6

16

A5

17

A4

18

A3

19

A2

20

A1

40

A17

39

GND

38

NC

37

A19

36

A10

35

I/O7

34

I/O6

33

I/O5

32

I/O4

31

VCC

30

VCC

29

NC

28

I/O3

27

I/O2

26

I/O1

25

I/O0

24

OE

23

GND

22

CE

21

A0

Rev. 0972A–03/98

1

To allow for simple in-system reprogrammability, the
AT49F008 does not require high input voltages for pro­gramming. 5-volt-only commands determine the read and
programming operation of the device. Reading data out of
the device is similar to reading from an EPROM. Repr o­gramming the AT49F008 is performed by erasing the entire
8 megabits of memory and then programming on a byte-by­byte basis. The typical byte programming time is a fast 10
µs. The end of a program cycle can be optionally detected
by the DATA

polling feature. Once the end of a byte pro-

Block Diagram

V

CC

GND

OE

WE

CE

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

gram cycle has been detected, a new access for a read or
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles

The optional 16K bytes boot block section includes a repro­gramming write lock out feature to provide data integrity.
The boot sector is design ed to contai n user secur e code,
and when the featur e is en abled , the b oot s ector i s perma ­nently protected from being reprogrammed.

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

DATA LATCH

INPUT/OUTPUT

BUFFERS
Y-GATING

MAIN MEMORY

(1008K BYTES)

OPTIONAL BOOT

BLOCK (16K BYTES)

FFFFFH

03FFFH

00000H

Device Operation

READ:

CE
memory location determined by the address pins is
asserted on the outputs . The outputs ar e put in the high
impedance state whenever CE
control gives designers flexibility in preventing bus conten­tion.

ERASURE:

1024K bytes memo ry array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chi p erase code c onsists of 6-b yte load co m­mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been ini tiated , the devi ce
will internally time the eras e operatio n so that no ex ternal
clocks are required. The maximum time needed to erase
the whole chip is t
been enabled, the data in the boot sector will not be
erased.

BYTE PROGRAMMING:

erased, the device is programmed (to a logical “0”) on a
byte-by-byte bas is. Please note th at a data “0” ca nnot be

The AT49F008 is accessed like an EPROM. When

and OE are low and WE is hi gh, the data st ored at the

or OE is high. This dual-line

Before a byte can be reprogrammed, the

. If the boot block lockout feature has

EC

Once the memory array is

programmed ba ck to a “1”; only era se oper ation s can con ­vert “0”s to “1 ”s. Programmi ng is accom plished via the
internal device command register and is a 4 bus cycle oper­ation (plea se refer to the Co mmand Defini tions ta ble). The
device will automatically generate the required internal pro­gram pulses.

The program cycle has addresses latched on the falling
edge of WE
latched on the rising edge of WE
first. Programming is completed after the specified t

or CE, whichever occurs last, and the data

or CE, whichever occurs

BP

cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device
has one designated block that has a programming lockout
feature. This feature prevents programmin g of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enablin g the l ocko ut feature will allow t he boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti­vated; the boot block’ s u sa ge a s a write protected region is
optional to the user. The address range of the AT49F008
boot block is 00000H to 03FFFH.

2

AT49F008

AT49F008

To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot
block section is locked out. When the device is in the soft­ware product iden tification mode (see Soft ware Produc t
Identification Entry and Exit sections) a read from address
location 00002H will sho w if progra mming th e boot blo ck is
locked out. If the d ata on I /O 0 i s low, the boo t bl oc k ca n be
programmed; if the data on I/O0 is high, the program lock­out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKO UT OV ERRIDE:

The user can override the boot block programming lockout
by taking the RESET
tected boot block data can be altered through a chip erase,
or byte programming. When the RESET
to TTL levels, the boot block programming lockout feature
is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware oper ation mode can be used by an exte rnal pro­grammer to identify the correct programming algorithm for
the Atmel product.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro­gram cycle has been com pleted, true data is valid on all
outputs and the next cycle may begin . DATA
begin at any time during the program cycle.

pin to 12V ± 0.5V. By doing this, pr o-

The product identification

The AT49F008 features DATA

A software

pin is brought back

polling to

polling may

TOGGLE BIT:

provides another method for determining the end of a pro­gram or erase cycle. During a pro gram or er ase opera tion,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.

RDY/BUSY

vides another method of detecting the end of a program or
erase operation. RDY/BUSY
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR - tying of sever al devices to the same
RDY/BUSY

RESET:

tem applications. When RESET
device is in its sta nda rd ope ra tin g mo de. A lo w level on the
RESET
outputs of the device in a high impedance state, and
reduces the curr ent draw n by the p art to a mi nimum . If the
RESET
or erase operation, the operation may not be successfully
completed and the oper ati on wil l ha ve t o be rep eated afte r
a high level is applied to the RESET
is reasserted on the RESET
read or standby mode, depending upon the state of the
control inputs. By applying a 12V ± 0.5V input signal to the
RESET
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the AT49F008 in
the following ways: (a) V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE
gram cycle.

input halts the presen t device opera tion, puts the

pin makes a high to low transition during a program

pin, the boot block array can be reprogrammed

In addition to DATA

:

An open drain READY/BUSY

line.

A RESET

input pin is provided to eas e some sys -

pin, the device returns to the

CC

or CE inputs will not i ni t ia t e a pro-

polling, the AT49F008

output pin pro-

is actively pulled low during

is at a l ogic high le ve l, t he

pin. When a high level

Hardware features

sense: if VCC is below 3.8V

low, CE high or WE high

3

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Bus

Cycles

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D

(2)
(2)

(1)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0
1 XXXX F0

Boot Block Lockout
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH.

2. Either one of the Product ID Exit commands can be used.

Absolute Maximum Ratings*

Temperature Under Bias................................-55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the device at thes e o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

IN

4

AT49F008