ATMEL AT49F002A, AT49F002AN, AT49F002AT, AT49F002ANT User Manual
Features
• Single-voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time – 55 ns
• Internal Program Control and Timer
• Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)
• Fast Erase Cycle Time – 4 Seconds
• Byte-by-Byte Programming – 20 µs/Byte Typical
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT49F002A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its
2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
55 ns with power dissipation of just 137 mW over the industrial temperature range.
2-megabit
(256K x 8)
5-volt Only
Flash Memory
AT49F002A
AT49F002AN
AT49F002AT
AT49F002ANT
When the device is deselected, the CMOS standby current is less than 100 µA. For
the AT49F002AN(T) pin 1 for the PLCC package and pin 9 for the TSOP package are
no connect pins.
To allow for simple in-system reprogrammability, the AT49F002A(N)(T) does not
require high input voltages for programming. Five-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE
contention. Reprogramming the AT49F002A(N)(T) is performed by erasing a block of
data and then programming on a byte-by-byte basis. The byte programming time is a
fast 20 µs. The end of a program cycle can be optionally detected by the DATA
feature. Once the end of a byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program and erase cycles is in
excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections,
four main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed.
, OE, and WE inputs to avoid bus
polling
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In the AT49F002A(N)(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49F002A(T), once the
boot block programming lockout feature is enabled, the contents of the boot block cannot be
changed with input voltage levels of 5.5 volts or less.
2. Pin Configurations
Pin Name Function
A0 - A17 Addresses
2.1 PLCC Top View
CE
Chip Enable
OE Output Enable
WE
RESET
Write Enable
RESET
I/O0 - I/O7 Data Inputs/Outputs
A12
A15
A16
RESET *
VCCWEA17
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
432
5
6
7
8
9
10
11
12
13
14151617181920
I/O1
I/O2
GND
1
I/O3
323130
I/O4
I/O5
29
28
27
26
25
24
23
22
21
I/O6
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
2.2 VSOP (8 x 14 mm) or TSOP Type 1 (8 x 20 mm) – Top View
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE
8
VCC
A16
A15
A12
9
10
11
12
13
A7
14
A6
15
A5
16
A4
* RESET
Note: *This pin is a NC on the AT49F002AN(T).
2
AT49F002A(N)(T)
OE
32
A10
31
CE
30
I/O7
29
I/O6
28
I/O5
27
I/O4
26
I/O3
25
GND
24
I/O2
23
I/O1
22
I/O0
21
A0
20
A1
19
A2
18
A3
17
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3. Block Diagram
AT49F002A(N)(T)
VCC
GND
WE
RESET
ADDRESS
INPUTS
AT49F002A(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE
CE
CONTROL
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
MAIN MEMORY
BLOCK 4
(64K BYTES)
MAIN MEMORY
BLOCK 3
(64K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
AT49F002A(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
BOOT BLOCK
(16K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 3
(64K BYTES)
MAIN MEMORY
BLOCK 4
(64K BYTES)
3FFFF
3C000
3BFFF
3A000
39FFF
38000
37FFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
4. Device Operation
4.1 Read
The AT49F002A(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE
control gives designers flexibility in preventing bus contention.
4.2 Command Sequences
When the device is first powered on, it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the
Command Definitions table. The command sequences are written by applying a low pulse on the
or CE input with CE or WE low (respectively) and OE high. The address is latched on the
WE
falling edge of CE
or WE. Standard microprocessor write timings are used. The address locations used in the
CE
command sequences are not affected by entering the command sequences.
or OE is high. This dual-line
or WE, whichever occurs last. The data is latched by the first rising edge of
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3
4.3 Reset
4.4 Erasure
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
present device operation and puts the outputs of the device in a high impedance state. If the
RESET
may not be successfully completed and the operation will have to be repeated after a high level
is applied to the RESET
returns to the read or standby mode, depending upon the state of the control inputs. By applying
a 12V ± 0.5V input signal to the RESET
the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available for the AT49F002AN(T).
Before a byte can be reprogrammed, the main memory block or parameter block which contains
the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device
can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please
refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip
is t
erased.
pin makes a high to low transition during a program or erase operation, the operation
pin. When a high level is reasserted on the RESET pin, the device
pin, the boot block array can be reprogrammed even if
. If the boot block lockout feature has been enabled, the data in the boot sector will not be
EC
input halts the
4.4.1 Chip Erase
4.4.2 Sector Erase
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter
Block 1, Parameter Block 2, Main Memory Block 1-4 but not the boot block. If the Boot Block
Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full
chip erase the device will return back to read mode. Any command during chip erase will be
ignored.
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and four main memory blocks. The 8Kbyte parameter block sections and the four main memory blocks can be independently erased
and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the falling WE
latched at the rising edge of WE
cycle. The erase operation is internally controlled; it will automatically time to completion.
edge of the sixth cycle while the 30H data input command is
. The sector erase starts after the rising edge of WE of the sixth
4
AT49F002A(N)(T)
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4.5 Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will
automatically generate the required internal program pulses.
AT49F002A(N)(T)
The program cycle has addresses latched on the falling edge of WE
last, and the data latched on the rising edge of WE
is completed after the specified t
indicate the end of a program cycle.
4.6 Boot Block Programming Lockout
The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size
of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 00000 to 03FFF for the AT49F002A(N) while the address range of the boot
block is 3C000 to 3FFFF for the AT49F002A(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed
with input voltage levels of 5.5V or less. Data in the main memory block can still be changed
through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the
Command Definitions table.
4.6.1 Boot Block Lockout Detection
A software method is available to determine if programming of the boot block section is locked
out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming
the boot block is locked out for the AT49F002A(N), and a read from address location 3C002H
will show if programming the boot block is locked out for AT49F002A(N)T. If the data on I/O0 is
low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature
has been activated and the block cannot be programmed. The software product identification
exit code should be used to return to standard operation.
or CE, whichever occurs
or CE, whichever occurs first. Programming
cycle time. The DATA polling feature may also be used to
BP
4.6.2 Boot Block Programming Lockout Override
The user can override the boot block programming lockout by taking the RESET
By doing this, protected boot block data can be altered through a chip erase, sector erase or
word programming. When the RESET
ming lockout feature is again active. This feature is not available on the AT49F002AN(T).
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pin to 12 volts.
pin is brought back to TTL levels the boot block program-
5
4.7 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.8 DATA Polling
The AT49F002A(N)(T) features DATA polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA
cycle.
4.9 Toggle Bit
In addition to DATA polling the AT49F002A(N)(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
polling may begin at any time during the program
4.10 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49F002A(N)(T) in the
following ways: (a) V
(b) Program inhibit: holding any one of OE
(c) Noise filter: pulses of less than 15 ns (typical) on the WE
gram cycle.
sense: if VCC is below 3.8V (typical), the program function is inhibited.
CC
low, CE high or WE high inhibits program cycles.
or CE inputs will not initiate a pro-
6
AT49F002A(N)(T)
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