Features
• Single-voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time – 55 ns
• Internal Program Control and Timer
• Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)
• Fast Erase Cycle Time – 4 Seconds
• Byte-by-Byte Programming – 20 µs/Byte Typical
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT49F002A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its
2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
55 ns with power dissipation of just 137 mW over the industrial temperature range.
2-megabit
(256K x 8)
5-volt Only
Flash Memory
AT49F002A
AT49F002AN
AT49F002AT
AT49F002ANT
When the device is deselected, the CMOS standby current is less than 100 µA. For
the AT49F002AN(T) pin 1 for the PLCC package and pin 9 for the TSOP package are
no connect pins.
To allow for simple in-system reprogrammability, the AT49F002A(N)(T) does not
require high input voltages for programming. Five-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE
contention. Reprogramming the AT49F002A(N)(T) is performed by erasing a block of
data and then programming on a byte-by-byte basis. The byte programming time is a
fast 20 µs. The end of a program cycle can be optionally detected by the DATA
feature. Once the end of a byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program and erase cycles is in
excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections,
four main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed.
, OE, and WE inputs to avoid bus
polling
3354F–FLASH–2/05
In the AT49F002A(N)(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49F002A(T), once the
boot block programming lockout feature is enabled, the contents of the boot block cannot be
changed with input voltage levels of 5.5 volts or less.
2. Pin Configurations
Pin Name Function
A0 - A17 Addresses
2.1 PLCC Top View
CE
Chip Enable
OE Output Enable
WE
RESET
Write Enable
RESET
I/O0 - I/O7 Data Inputs/Outputs
A12
A15
A16
RESET *
VCCWEA17
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
432
5
6
7
8
9
10
11
12
13
14151617181920
I/O1
I/O2
GND
1
I/O3
323130
I/O4
I/O5
29
28
27
26
25
24
23
22
21
I/O6
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
2.2 VSOP (8 x 14 mm) or TSOP Type 1 (8 x 20 mm) – Top View
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE
8
VCC
A16
A15
A12
9
10
11
12
13
A7
14
A6
15
A5
16
A4
* RESET
Note: *This pin is a NC on the AT49F002AN(T).
2
AT49F002A(N)(T)
OE
32
A10
31
CE
30
I/O7
29
I/O6
28
I/O5
27
I/O4
26
I/O3
25
GND
24
I/O2
23
I/O1
22
I/O0
21
A0
20
A1
19
A2
18
A3
17
3354F–FLASH–2/05
3. Block Diagram
AT49F002A(N)(T)
VCC
GND
WE
RESET
ADDRESS
INPUTS
AT49F002A(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE
CE
CONTROL
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
MAIN MEMORY
BLOCK 4
(64K BYTES)
MAIN MEMORY
BLOCK 3
(64K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
AT49F002A(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
BOOT BLOCK
(16K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 3
(64K BYTES)
MAIN MEMORY
BLOCK 4
(64K BYTES)
3FFFF
3C000
3BFFF
3A000
39FFF
38000
37FFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
4. Device Operation
4.1 Read
The AT49F002A(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE
control gives designers flexibility in preventing bus contention.
4.2 Command Sequences
When the device is first powered on, it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the
Command Definitions table. The command sequences are written by applying a low pulse on the
or CE input with CE or WE low (respectively) and OE high. The address is latched on the
WE
falling edge of CE
or WE. Standard microprocessor write timings are used. The address locations used in the
CE
command sequences are not affected by entering the command sequences.
or OE is high. This dual-line
or WE, whichever occurs last. The data is latched by the first rising edge of
3354F–FLASH–2/05
3
4.3 Reset
4.4 Erasure
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
present device operation and puts the outputs of the device in a high impedance state. If the
RESET
may not be successfully completed and the operation will have to be repeated after a high level
is applied to the RESET
returns to the read or standby mode, depending upon the state of the control inputs. By applying
a 12V ± 0.5V input signal to the RESET
the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available for the AT49F002AN(T).
Before a byte can be reprogrammed, the main memory block or parameter block which contains
the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device
can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please
refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip
is t
erased.
pin makes a high to low transition during a program or erase operation, the operation
pin. When a high level is reasserted on the RESET pin, the device
pin, the boot block array can be reprogrammed even if
. If the boot block lockout feature has been enabled, the data in the boot sector will not be
EC
input halts the
4.4.1 Chip Erase
4.4.2 Sector Erase
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter
Block 1, Parameter Block 2, Main Memory Block 1-4 but not the boot block. If the Boot Block
Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full
chip erase the device will return back to read mode. Any command during chip erase will be
ignored.
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and four main memory blocks. The 8Kbyte parameter block sections and the four main memory blocks can be independently erased
and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the falling WE
latched at the rising edge of WE
cycle. The erase operation is internally controlled; it will automatically time to completion.
edge of the sixth cycle while the 30H data input command is
. The sector erase starts after the rising edge of WE of the sixth
4
AT49F002A(N)(T)
3354F–FLASH–2/05
4.5 Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will
automatically generate the required internal program pulses.
AT49F002A(N)(T)
The program cycle has addresses latched on the falling edge of WE
last, and the data latched on the rising edge of WE
is completed after the specified t
indicate the end of a program cycle.
4.6 Boot Block Programming Lockout
The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size
of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 00000 to 03FFF for the AT49F002A(N) while the address range of the boot
block is 3C000 to 3FFFF for the AT49F002A(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed
with input voltage levels of 5.5V or less. Data in the main memory block can still be changed
through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the
Command Definitions table.
4.6.1 Boot Block Lockout Detection
A software method is available to determine if programming of the boot block section is locked
out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming
the boot block is locked out for the AT49F002A(N), and a read from address location 3C002H
will show if programming the boot block is locked out for AT49F002A(N)T. If the data on I/O0 is
low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature
has been activated and the block cannot be programmed. The software product identification
exit code should be used to return to standard operation.
or CE, whichever occurs
or CE, whichever occurs first. Programming
cycle time. The DATA polling feature may also be used to
BP
4.6.2 Boot Block Programming Lockout Override
The user can override the boot block programming lockout by taking the RESET
By doing this, protected boot block data can be altered through a chip erase, sector erase or
word programming. When the RESET
ming lockout feature is again active. This feature is not available on the AT49F002AN(T).
3354F–FLASH–2/05
pin to 12 volts.
pin is brought back to TTL levels the boot block program-
5
4.7 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.8 DATA Polling
The AT49F002A(N)(T) features DATA polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA
cycle.
4.9 Toggle Bit
In addition to DATA polling the AT49F002A(N)(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
polling may begin at any time during the program
4.10 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49F002A(N)(T) in the
following ways: (a) V
(b) Program inhibit: holding any one of OE
(c) Noise filter: pulses of less than 15 ns (typical) on the WE
gram cycle.
sense: if VCC is below 3.8V (typical), the program function is inhibited.
CC
low, CE high or WE high inhibits program cycles.
or CE inputs will not initiate a pro-
6
AT49F002A(N)(T)
3354F–FLASH–2/05
5. Command Definition Table
AT49F002A(N)(T)
1st Bus
Command
Sequence
Read 1 Addr D
Chip Erase 6 555 AA AAA
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
Byte Program 4 555 AA AAA 55 555 A0 Addr D
Boot Block Lockout
Product ID Entry 3 555 AA AAA 55 555 90
Product ID Exit
Product ID Exit
(4)
(4)
Bus
Cycles
(3)
6 555 AA AAA 55 555 80 555 AA AAA 55 555 40
3 555 AA AAA 55 555 F0
1XXXXF0
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
OUT
2nd Bus
Cycle
(2)
3rd Bus
Cycle
55 555 80 555 AA AAA 55 555 10
4th Bus
Cycle
5th Bus
Cycle
IN
6th Bus
Cycle
(5)
30
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:
A11 - A0 (Hex); A11 - A17 (don’t care).
2. Since A11 is don’t care, AAA can be replaced with 2AA.
3. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F002A(N) and 3C000H to 3FFFFH for the
AT 4 9F 0 0 2A ( N )T
4. Either one of the Product ID Exit commands can be used.
5. SA = sector addresses:
For the AT49F002A(N):
SA = 00000 to 03FFF for BOOT BLOCK
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 3
SA = 30000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 4
For the AT49F002A(N)T:
SA = 3C000 to 3FFFF for BOOT BLOCK
SA = 3A000 to 3BFFF for PARAMETER BLOCK 1
SA = 38000 to 39FFF for PARAMETER BLOCK 2
SA = 30000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1
SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 2
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 3
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 4
6. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
3354F–FLASH–2/05
+ 0.6V
CC
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
7
7. DC and AC Operating Range
AT49F002A(N)(T)-55
Operating Temperature (Case) Ind. -40°C - 85°C
Power Supply 5V ± 10%
V
CC
8. Operating Modes
Mode CE OE WE RESET
Read V
Program/Erase
(2)
Standby/Write Inhibit V
IL
V
IL
IH
XXV
Program Inhibit
XVILXV
Output Disable X V
V
IL
V
IH
(1)
X
IH
V
IH
V
IL
XV
IH
XV
Reset XXX V
(6)
V
IH
V
IH
IH
V
IH
IH
IH
IL
Product Identification
Hardware V
Software
Notes: 1. X can be VIL or V
(5)
IH.
IL
V
IL
V
IH
2. Refer to AC Programming Waveforms.
3. V
= 12.0V ± 0.5V.
H
4. Manufacturer Code: 1FH, Device Code: 07H - AT49F002A(N), 08H – AT49F002A(N)T
5. See details under Software Product Identification Entry/Exit.
6. This pin is not available on the AT49F002AN(T).
A1 - A17 = VIL, A9 = VH,
A1 - A17 = VIL, A9 = V
A0 = VIL, A1 - A17=V
A0 = VIH, A1 - A17=V
Ai
Ai D
Ai D
X High Z
X High Z
(3)
A0 = V
IL
(3)
A0 = V
H,
IH
IL
IL
I/O
OUT
IN
High Z
Manufacturer Code
Device Code
(4)
Manufacturer Code
Device Code
(4)
(4)
(4)
9. DC Characteristics
Symbol Parameter Condition Min Max Units
I
I
I
I
I
V
V
V
V
V
LI
LO
SB1
SB2
CC
(1)
IL
IH
OL
OH1
OH2
Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = V
VCC Standby Current TTL CE = 2.0V to V
V
Active Current f = 5 MHz; I
CC
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
Note: 1. In the erase mode, I
8
AT49F002A(N)(T)
is 90 mA.
CC
= 0V to V
I/O
CC
CC
- 0.3V to V
CC
OUT
CC
CC
= 0 mA 25 mA
10 µA
10 µA
100 µA
3mA
3354F–FLASH–2/05
10. AC Read Characteristics
Symbol Parameter
AT49F002A(N)(T)
AT49F002A(N)(T)-55
UnitsMin Max
t
ACC
t
CE
t
OE
t
DF
t
OH
(1)
(2)
(3)(4)
Address to Output Delay 55 ns
CE to Output Delay 55 ns
OE to Output Delay 0 30 ns
CE or OE to Output Float 0 25 ns
Output Hold from OE, CE or Address, whichever
occurred first
11. AC Read Waveforms
Notes: 1. CE may be delayed up to t
may be delayed up to tCE - t
2. OE
without impact on t
3. t
is specified from OE or CE whichever occurs first (CL = 5 pF).
DF
ACC
4. This parameter is characterized and is not 100% tested.
ACC
.
0ns
(1)(2)(3)(4)
ADDRESS
CE
OE
OUTPUT
- tCE after the address transition without impact on t
after the falling edge of CE without impact on tCE or by t
OE
ADDRESS VALID
t
CE
t
OE
t
ACC
HIGH Z
OUTPUT
VALID
t
DF
t
OH
ACC
.
- tOE after an address change
ACC
3354F–FLASH–2/05
9
12. Input Test Waveform and Measurement Level
tR, tF < 5 ns
13. Output Load Test
55 ns
5.0V
1.8K
OUTPUT
PIN
1.3K
30 pF
14. Pin Capacitance
f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
(1)
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
46pFV
812pFV
IN
OUT
= 0V
= 0V
10
AT49F002A(N)(T)
3354F–FLASH–2/05
AT49F002A(N)(T)
15. AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, t
OES
t
AH
t
CS
t
CH
t
WP
t
DS
tDH, t
OEH
t
WPH
16. AC Byte Load Waveforms
16.1 WE Controlled
Address, OE Set-up Time 0 ns
Address Hold Time 25 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)25ns
Data Set-up Time 25 ns
Data, OE Hold Time 0 ns
Write Pulse Width High 20 ns
ADDRESS
DATA IN
16.2 CE Controlled
ADDRESS
OE
CE
WE
OE
WE
t
OES
t
t
t
OES
t
AS
CS
AS
t
OEH
t
AH
t
WP
t
DS
t
AH
t
t
OEH
t
CH
CH
t
t
DH
WPH
3354F–FLASH–2/05
CE
DATA IN
t
CS
t
WPH
t
WP
t
DS
t
DH
11
17. Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
t
AS
t
AH
t
DS
t
DH
t
WP
t
WPH
t
EC
Byte Programming Time 20 50 µs
Address Set-up Time 0 ns
Address Hold Time 25 ns
Data Set-up Time 25 ns
Data Hold Time 0 ns
Write Pulse Width 25 ns
Write Pulse Width High 20 ns
Erase Cycle Time 4 8 seconds
18. Program Cycle Waveforms
19. Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
12
AT49F002A(N)(T)
3354F–FLASH–2/05
AT49F002A(N)(T)
20. Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
spec in AC Read Characteristics.
OE
21. Data Polling Waveforms
WE
CE
t
OE
t
I/O7
A0-A17
DH
OEH
t
OE
HIGH Z
An An An An An
t
WR
ns
22. Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 50 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
23. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t
spec in AC Read Characteristics.
OE
(1)(2)(3)
WE
CE
OE
I/O6
t
t
OEH
t
OE
DH
t
OEHP
HIGH Z
t
WR
specification must be met by the toggling
OEHP
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
ns
3354F–FLASH–2/05
13
24. Software Product Identification
Entry
(1)
LOAD DATA AA
TO
ADDRESS 555
26. Boot Block Lockout Feature Enable
Algorithm
(1)
LOAD DATA AA
ADDRESS 555
TO
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 90
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
(2)(3)(5)
MODE
25. Software Product Identification
(1)
Exit
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = V
Manufacture Code is read for A0 = V
Device Code is read for A0 = V
Additional Device Code is read for address 0003H
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 07H - AT49F002A(N)
08H - AT49F002A(N)T
Additional Device Code: 0FH - AT49F002A(N)(T)
OR
.
IL
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
IH
.
MODE
;
IL
(4)
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 40
TO
ADDRESS 555
PAUSE 1 second
(2)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
14
AT49F002A(N)(T)
3354F–FLASH–2/05
27. Ordering Information
27.1 Standard Package
I
(mA)
t
ACC
(ns)
55 25 0.1
55 25 0.1
55 25 0.1
55 25 0.1
CC
Ordering Code Package Operation RangeActive Standby
AT49F002A-55JI
AT49F002A-55TI
AT49F002A-55VI
AT49F002AN-55JI
AT49F002AN-55TI
AT49F002AN-55VI
AT 4 9F 0 0 2AT- 5 5J I
AT 4 9F 0 0 2AT- 5 5T I
AT 4 9F 0 0 2AT- 5 5V I
AT49F002ANT-55JI
AT49F002ANT-55TI
AT49F002ANT-55VI
32J
32T
32V
32J
32T
32V
32J
32T
32V
32J
32T
32V
AT49F002A(N)(T)
Industrial
(-40° to 85°C)
Industrial
(-40° to 85°C)
Industrial
(-40° to 85°C)
Industrial
(-40° to 85°C)
27.2 Green Package Option (Pb/Halide-free)
I
(mA)
t
ACC
(ns)
55 25 0.1
55 25 0.1
CC
Ordering Code Package Operation RangeActive Standby
AT49F002AN-55JU
AT49F002AN-55TU
AT49F002AN-55VU
AT49F002ANT-55JU
AT49F002ANT-55TU
AT49F002ANT-55VU
Package Type
32J
32T
32V
32J
32T
32V
Industrial
(-40° to 85°C)
Industrial
(-40° to 85°C)
32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32T 32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
3354F–FLASH–2/05
15
28. Packaging Information
28.1 32J – PLCC
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1
IDENTIFIER
D1
D
D2
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
E2
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
MIN
NOM
MAX
NOTE
10/04/01
16
2325 Orchard Parkway
R
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
AT49F002A(N)(T)
TITLE
DRAWING NO.
32J
3354F–FLASH–2/05
REV.
B
28.2 32T – TSOP
AT49F002A(N)(T)
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
MIN
c
L1
GAGE PLANE
(Unit of Measure = mm)
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
3354F–FLASH–2/05
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
32T
10/18/01
REV.
B
17
28.3 32V – VSOP
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 13.80 14.00 14.20
D1 12.30 12.40 12.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
MIN
c
L1
GAGE PLANE
(Unit of Measure = mm)
NOM
MAX
NOTE
18
2325 Orchard Parkway
R
San Jose, CA 95131
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
AT49F002A(N)(T)
TITLE
DRAWING NO.
32V
3354F–FLASH–2/05
10/18/01
REV.
B
AT49F002A(N)(T)
3354F–FLASH–2/05
19
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not
intended, authorized, or warranted for use as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, and others, are registered trademarks, and
Everywhere You Are
trademarks of others.
SM
and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be
Printed on recycled paper.
3354F–FLASH–2/05
Loading...