ATMEL AT49BV8192A-20CI, AT49BV8192A-20CC, AT49BV8192A-15TI, AT49BV8192A-15TC, AT49BV8192A-15CI Datasheet

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Features

•

2.7V to 3.6V Read/Write Operation

•

Fast Read Access Time - 120 ns

•

Internal Erase/Program Control

•

Sector Architecture

– One 8K Words (16K bytes) Boot Block with Programming Lockout – Two 4K Words (8K bytes) Parameter Blocks – One 496K Words (992K bytes) Main Memory Array Block

•

Fast Sector Erase Time - 10 seconds

•

Byte-by-Byte or Word-By-Word Programming - 30

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low-Power Dissipation

– 25 mA Active Current

µµµµ

–50

A CMOS Standby Current

•

Typical 10,000 Write Cycles

µµµµ

s Typical

8-Megabit (1M x 8/ 512K x 16)

Description

The AT49BV008A(T) and AT49BV8192A(T) are 3-volt, 8-megabit Flash Memories organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 120 ns with power di ssipati on of jus t 67 mW at 2.7V read . When de selec ted, the CMOS standby current is less than 50 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available: the AT49BV008A/8192A locates the boot block at lowest order address es (“bott om boot”); the AT49 BV008AT /8192AT l ocates it at high est order addresses (“top boot”).

To allow for simple in- system reprog ramma bili ty, the AT49BV 008A(T )/8192A (T) d oes not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE bus contention. Reprogramming the AT49BV008A(T)/8192A(T) is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis.

, OE, and WE inputs to avoid

(continued)

Pin Configurations

Pin Name Function

A0 - A18 Addresses CE

Chip Enable

CMOS Flash Memory

AT49BV008A AT49BV008AT AT49BV8192A AT49BV8192AT Preliminary

OE WE Write Enable RESET RDY/BUSY

VPP

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

BYTE Selects Byte or Word Mode NC No Connect

Output Enable

Reset Ready/Busy Output Optional Power Supply for Faster

Program/Era se Op erations

I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

Rev. 1049C–09/98

AT49BV8192A(T) TSOP Top View

B C D

234567

A14 A15 A16 A17 NC

GND

A12 A10 A13

NC A11 I/O7

A9 I/O5 I/O6 NC

VPP RST

NC NC NC

I/O4

NC A19 NC I/O2 I/O3

VCC

A18

A6 NC NC NC

A7 A5 A3

CE I/O0 I/O1

A4 A2 A1 A0

GND

Type 1

AT49BV008A(T) TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

RESET

A18 A17

13 14

16 17 18

*NC/VPP

AT49BV8192A(T)

CBGA Top View (Ball Down)

234567

A13

A11

*NC/VPP

A14

A10

A15

A16

BYTE

GND

A12 I/O14 I/O15

I/O7

I/O5 I/O6

I/O13

RST

A18

I/O11

I/O2

I/O12

I/O3

I/O4

VCC

A17

A6 I/O8 I/O9

I/O10

A7 A5 A3

CE I/O0 I/O1

A4 A2 A1 A0

GND

A16

BYTE

GND

I/O15 / A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

RDY/BUSY

AT49BV008A(T) Standard Pin Definition

CBGA Top View (Ball Down)

234567

A13

A11

VPP

A6 NC NC NC

A5 A3

CE I/O0 I/O1

A4 A2 A1 A0

GND

A14

A10

RST

A18

A15

A12

A16

GND

NC A-1 I/O7

A9 I/O5 I/O6 NC

NC NC NC

I/O4

A17

NC I/O2 I/O3

VCC

RESET

*NC/VPP

A16 A15 A14 A13 A12 A11

A18

1 2 3 4 5 6 7

9 10 11 12 13 14

A17

GND

A-1

A10

I/O7

I/O6

I/O5

I/O4

VCC

I/O3

I/O2

I/O1

I/O0

GND

AT49BV008A(T) Alternate Pin Definition

CBGA Top View (Ball Down)

*Standard device is a NC. Please contact Atmel for VPP option.

The device is erased by executing the er ase command sequence; the device internally controls the erase operation. The memory is divided into four bloc k s for eras e oper ations. There are two 4K word parameter block sections, the boot block, and the main memor y array blo ck. Th e typ ical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming lock out feature to provide data inte grity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cann ot be chan ged when input level s of 3.6

For the AT49BV8192A(T), the BYTE the device data I/O pi ns op er ate in the by te or wo rd c onfiguration. If the BYTE

pin is set at a logi c “1” o r lef t ope n, the device is in word co nfigurat ion, I/O0 - I/O15 are activ e and controlled by CE

If the BYTE

and OE.

pin is set at logic “0”, the devi ce is in byte configuration, and only data I/O pins I/O 0 - I/O7 ar e active an d controlled by CE

and OE. The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.

An optional V

pin is available to improve program/erase

times. Please contact Atmel for more information.

pin controls whether

volts or less are used. The boot sector is designed to contain user secure code.

AT49BV008A(T)/8192A(T)

AT49BV008A(T) Block Diagram

GND

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49BV8192A(T) Block Diagram

GND

AT49BV008A AT49BV008AT

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES Y-GATING

MAIN MEMORY

(992K BYTES)

PARAMETER

BLOCK 2

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

BOOT BLOCK

16K BYTES

AT49BV8192A AT49BV8192AT

DATA INPUTS/OUTPUTS

I/O0 - I/O15

AT49BV008A(T)/8192A(T)

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

FFFFF FFFFF

08000

07FFF

06000

05FFF

04000

03FFF 00000 00000

DATA INPUTS/OUTPUTS

Y-GATING

BOOT BLOCK

16K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 2

8K BYTES

MAIN MEMORY

(992K BYTES)

I/O0 - I/O15

FC000 FBFFF

7A000 79FFF

78000

77FFF

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES Y-GATING

MAIN MEMORY (496K WORDS)

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

BOOT BLOCK

8K WORDS

Device Operation

READ:

EPROM. When CE data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE high. This dual-line con tr ol gi v es d esign er s fl ex ibi lit y in pr eventing bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command

The AT49BV008A(T)/8192A(T) is accessed like an

and OE are low and WE is high, th e

or OE is

When the device is first pow-

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

7FFFF 7FFFF

04000 03FFF

03000

02FFF

02000 01FFF

00000 00000

Y-GATING

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 2

4K WORDS

MAIN MEMORY (496K WORDS)

7E000

7DFFF 7D000

7CFFF

7C000

7BFFF

sequences are shown in the Com mand Definition s table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE tively) and OE edge of CE latched by the first rising edge of CE

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is prov ided to eas e so me s ys-

is at a logic high level, the

device is in its standa rd oper at ing mod e. A low l ev el on the RESET the outputs of the de vice in a hi gh imped ance stat e. When a high level is reasse rted on the RES ET returns to the Read or Standby mod e, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RE SE T grammed even if the boot block program lockout feature has been enable d (see Boot B lock Pr ogrammi ng Lock out Override section).

ERASURE:

must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands.

CHIP ERASE:

by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t

If the boot block lockou t has be en enabled, the Ch ip Eras e will not erase the data in t he boot block; it wil l erase the main memory block and the parameter blocks only. After the chip erase, the de vi ce wi ll retu rn to the read or standby mode.

SECTOR ERASE:

device is organized into four sectors that can be individually erased. There are two 4K word parameter block sections, one boot block, and the main memory array block. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE sixth cycle while the 30 H data in put com mand is la tched at the rising edge of WE ing edge of WE internally controlled; it will automatically time to completion. Whenever the main memory block is erased and reprogrammed, the two parame ter bloc ks should be erased and reprogrammed before the main memory block is erased again. Whenever a parameter block is erased and reprogrammed, the other parameter block should be erased and reprogrammed before the first parameter block is erased again.

BYTE/WORD PROGRAMMING:

erased, it is programmed (to a logical “0”) on a byte-by-byte or word-by-word bas is. Progr amming is accom plished via the internal device command register and is a 4 bus cycle operation. The device will automatically generate the required internal program pulses.

Any commands written to the c hip during the em bedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0”

input halts the prese nt device oper ation and puts

pin, the device

pin the boot blo ck ar ray c an b e r epro-

Before a byte or word can be reprogrammed, it

The entire device can be erased at one time

As an alternative to a full chip erase, the

edge of the

. The sector erase s tar ts after the ris-

of the sixth cycle. The erase o peration is

Once a memory block is

cannot be programmed back to a “1”; only erase operations can convert “ 0”s to “ 1”s. Pro grammi ng is co mplete d after the specified t also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

has one designated block that has a programming lockout feature. This feature prevents programming of data in th e designated block once the feature has been enabled. The size of the block is 8K words. Thi s blo ck, refe rred to a s the boot block, can contain secure code that is used to bring up the system. Enablin g the l ockou t feature w ill al low the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’ s u sag e as a wr i te pro t ected r eg io n is optional to the user. The address range of the boot block is 00000H to 03FFFH for the AT49BV008A; FC000H to FFFFFH for the AT49BV008AT; 00000H to 01FFFH for the AT49BV8192A; and 7E000H to 7FFFFH for the AT49BV8192AT.

Once the feature is enabled, the data in the boot blo ck ca n no longer be erased or programmed when input levels of

5.5V or less are u sed. Dat a in the ma in memo ry bloc k can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit section s) a read from the following address location will show if programming the boot block is lock ed out—00002H for the AT4 9BV008A an d AT49BV8192A; FC002H for the AT49BV008AT; and 7E002H for the AT49B V8192AT. If the da ta on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the block cann ot be programm ed. The soft ware product identification exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override th e boot blo ck progr amming lo ckout by taking the RESET erase, sector erase or word pro grammin g oper ation. W hen the RESET programming lockout feature is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

cycle time. The DATA polling feature may

The device

A software

pin to 12 volts during the entire chip

pin is brought back to TTL levels the boot block

The product identification

AT49BV008A(T)/8192A(T)

For details, see O peratin g Modes (for har dware operatio n) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

polling to indic ate the en d o f a program cycle. Dur in g

DATA

The AT49BV008A(T)/8192A(T) features

a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and th e next cyc le may be gin. Du ring a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device.

polling may begi n at any ti me during the program

DATA cycle.

TOGGLE BIT:

In addition to DATA

polling the AT49BV008A(T)/8192A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the de vice will res ult in I/O6 toggling be tween one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

READY/BUSY

drain READY/BUSY

For the AT49F008A(T), pin 12 i s an open

output pin whic h provides a nother method of detecting the end of a program or erase operation. RDY/BUSY

is activ ely pu lled lo w dur ing th e inte rnal

program and erase cycles and it is rele ased at the co mpletion of the cycle. The open drain connec tion allow s for ORtying of several devices to the same RDY/BUSY

HARDWARE DATA PROTECTION:

Hardware features

line.

protect against inadvertent programs to the AT49BV008A(T)/8192A(T) in the following ways: (a) V

sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) V the V

sense level, the device will automaticall y time out

power on delay: onc e VCC has reached

10 ms (typical) before programming. (c) Program inhibit: holding any one of OE

low, CE high or WE h igh inhi bits program cycles. (d) Noise filter: pulses o f less than 15 ns (typical) on the WE

or CE inputs will not initiate a program

cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, th e address inpu ts and cont rol inputs (OE

, and WE) may be dr iven from 0 to 5.5V without

CE adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V

AT49BV008A(T) ALTERNATE PIN DEFINITION:

+ 0.6V.

Two AT49BV008A(T) BGA pin definitions are shown. The standard pin definition allows use of the JEDEC standard programming algorithm. If the alternate pin definition is used, the programming algorithm must be modified as shown in the Command Definition for Alternate Pin Definition Table on page 7.

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