ATMEL AT49BV642D, AT49BV642DT User Manual
Features
•
Single Voltage Operation Read/Write: 2.65V - 3.6V
•
2.7V - 3.6V Read/Write
•
Access Time – 70 ns
•
Sector Erase Architecture
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
– Eight 4K Word Sectors with Individual Write Lockout
•
Fast Word Program Time – 10 µs
•
Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
•
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
•
Low-power Operation
– 10 mA Active
– 15 µA Standby
•
Data Polling and Toggle Bit for End of Program Detection
•
VPP Pin for Write Protection and Accelerated Program Operations
•
RESET Input for Device Initialization
•
Sector Lockdown Support
•
TSOP Package
•
Top or Bottom Boot Block Configuration Available
•
128-bit Protection Register
•
Common Flash Interface (CFI)
•
Green (Pb/Halide-free) Packaging
64-megabit
(4M x 16)
3-volt Only
Flash Memory
AT49BV642D
AT49BV642DT
1. Description
The AT49BV642D(T) is a 2.7-volt 64-megabit Flash memory organized as 4,194,304
words of 16 bits each. The memory is divided into 135 sectors for erase operations.
The device can be read or reprogrammed off a single 2.7V power supply, making it
ideally suited for in-system programming.
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors.
The end of program or erase is detected by Data
The VPP pin provides data protection and faster programming times. When the V
input is below 0.4V, the program and erase functions are inhibited. When VPP is at
1.65V or above, normal program and erase operations can be performed. With V
10.0V, the program (dual-word program command) operation is accelerated.
A six-word command (Enter Single Pulse Program Mode) to remove the requirement
of entering the three-word program sequence is offered to further improve programming time. After entering the six-word code, only single pulses on the write control
lines are required for writing into the device. This mode (Single Pulse Word Program)
is exited by powering down the device, by taking the RESET
to-low transition on the V
pend/Resume and Read Reset commands will not work while in this mode; if entered
they will result in data being programmed into the device. It is not recommended that
the six-word code reside in the software of the final product but only exist in external
programming code.
input. Erase, Erase Suspend/Resume, Program Sus-
PP
Polling or toggle bit.
pin to GND or by a high-
PP
PP
at
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2. Pin Configurations
Pin Name Pin Function
I/O0 - I/O15 Data Inputs/Outputs
A0 - A21 Addresses
CE
OE
WE
RESET
VPP
VCCQ Output Power Supply
2.1 TSOP Top View (Type 1)
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
VPP
NC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Chip Enable
Output Enable
Write Enable
Reset
Write Protection and Power Supply for Accelerated Program
Operations
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
2
AT49BV642D(T)
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3. Device Operation
3.1 Command Sequences
The device powers on in the read mode. Command sequences are used to place the device in
other operating modes such as program and erase. After the completion of a program or an
erase cycle, the device enters the read mode. The command sequences are written by applying
a low pulse on the WE
CE
input with WE low and OE high. The address is latched on the falling edge of the WE or CE
pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected by
entering the command sequences.
3.2 Read
The AT49BV642D(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE
control gives designers flexibility in preventing bus contention.
3.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
present device operation and puts the outputs of the device in a high-impedance state. When a
high level is reasserted on the RESET
ing upon the state of the control pins.
AT49BV642D(T)
input with CE low and OE high or by applying a low-going pulse on the
or OE is high. This dual-line
pin halts the
pin, the device returns to read or standby mode, depend-
3.4 Erase
3.4.1 Chip Erase
3.4.2 Sector Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
sectors can be erased by using the Sector Erase command.
Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the
last WE
erase the device will return back to the read mode. The hardware reset during Chip Erase will
stop the erase but the data will be of unknown state. Any command during Chip Erase except
Erase Suspend will be ignored.
As an alternative to a full chip erase, the device is organized into multiple sectors that can be
individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose
address is valid at the sixth falling edge of WE
been protected.
pulse. Chip Erase does not alter the data of the protected sectors. After the full chip
will be erased provided the given sector has not
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3
3.5 Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The programming address
and data are latched in the fourth cycle. The device will automatically generate the required
internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only
erase operations can convert “0”s to “1”s.
3.6 Sector Lockdown
Each sector has a programming lockdown feature. This feature prevents programming of data in
the designated sectors once the feature has been enabled. These sectors can contain secure
code that is used to bring up the system. Enabling the lockdown feature will allow the boot code
to stay in the device while data in the rest of the device is updated. This feature does not have to
be activated; any sector’s usage as a write-protected region is optional to the user.
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the
six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down,
the contents of the sector is read-only and cannot be erased or programmed.
3.6.1 Sector Lockdown Detection
A software method is available to determine if programming of a sector is locked down. When
the device is in the software product identification mode (see “Software Product Identification
Entry/Exit” sections on page 23), a read from address location 00002H within a sector will show
if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the
sector cannot be programmed. The software product identification exit code should be used to
return to standard operation.
3.6.2 Sector Lockdown Override
The only way to unlock a sector that is locked down is through reset or power-up cycles. After
power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.
3.7 Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O3, I/O5, I/O6, and I/O7. All other status bits are don’t care. The “Status Bit Table” on page 10
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV642D(T) contains a programmable configuration register. The
configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to
“00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be given
after a successful program or erase operation before the part will return to the read mode. It is
important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the
device to read mode. The default value (after power-up) for the configuration register is “00”.
Using the four-bus cycle set configuration register command as shown in the “Command Defini-
tion Table” on page 11, the value of the configuration register can be changed. Voltages applied
to the reset pin will not alter the value of the configuration register. The value of the configuration
register will affect the operation of the I/O7 status bit as described below.
4
AT49BV642D(T)
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3.7.1 Data Polling
AT49BV642D(T)
The AT49BV642D(T) features Data
configuration register is set to a “00”, during a program cycle an attempted read of the last word
loaded will result in the complement of the loaded data on I/O7. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may begin. During a chip or
sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program
or erase cycle has completed, true data will be read from the device. Data
any time during the program cycle. Please see “Status Bit Table” on page 10 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
Polling to indicate the end of a program cycle. If the status
Polling may begin at
The Data
Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 3-1 and 3-2 on page 8.
3.7.2 Toggle Bit
In addition to Data
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the memory will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle. Please see “Status Bit Table” on page 10 for
more details.
The toggle bit status bit should be used in conjunction with the erase/program and V
as shown in the algorithm in Figures 3-3 and 3-4 on page 9.
3.7.3 Erase/Program Status Bit
The device offers a status bit on I/O5 that indicates whether the program or erase operation has
exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to
verify that an erase or a word program operation has been successfully performed. The device
may also output a “1” on I/O5 if the system tries to program a “1” to a location that was previously programmed to a “0”. Only an erase operation can change a “0” back to a “1”. If a program
(Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set
high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 10 for more details.
Polling, the AT49BV642D(T) provides another method for determining the
status bit
PP
3.7.4 VPP Status Bit
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The AT49BV642D(T) provides a status bit on I/O3 that provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is
not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”.
Once the V
status bit has been set to a “1”, the system must write the Product ID Exit com-
PP
mand to return to the read mode. On the other hand, if the voltage level is high enough to
perform a program or erase operation successfully, the V
status bit will output a “0”. Please
PP
see “Status Bit Table” on page 10 for more details.
5
3.8 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation.
After the erase operation has been suspended, the system can then read data or program data
to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector
erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a
complete chip erase. While the chip erase is suspended, the user can read from any sector
within the memory that is protected. The command sequence for a chip erase suspend and a
sector erase suspend are the same.
3.9 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
erase suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same.
3.10 128-Bit Protection Register
The AT49BV642D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can be
locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 11. To lock out block B, the four-bus cycle
lock protection register command must be used as shown in the Command Definition table. Data
bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are
don’t cares. To determine whether block B is locked out, the status of Block B Protection command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be
reprogrammed. Please see the “Protection Register Addressing Table” on page 12 for the
address locations in the protection register. To read the protection register, the Product ID Entry
command is given followed by a normal read operation from an address within the protection
register. After determining whether block B is protected or not or reading the protection register,
the Product ID Exit command must be given prior to performing any other operation.
6
AT49BV642D(T)
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3.11 Common Flash Interface (CFI)
Common Flash Interface (CFI) is a published, standardized data structure that may be read from
a Flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is
used to allow the system to learn how to interface to the Flash device most optimally. The two
primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h
to address 55h. The CFI Query command can be written when the device is ready to read data
or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the
system can read CFI data at the addresses given in the “Common Flash Interface Definition
Table” on page 24. To exit the CFI Query mode, the product ID exit command must be given.
3.12 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV642D(T) in the following
ways: (a) V
power-on delay: once VCC has reached the VCC sense level, the device will automatically timeout 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE
or WE
high inhibits program cycles. (d) VPP is less than V
sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) V
CC
ILPP
AT49BV642D(T)
CC
low, CE high
.
3.13 Input Levels
3.14 Output Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,
CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
device. The I/O lines can be driven from 0 to V
For the AT49BV642D(T), output high levels are equal to V
3.6V output levels, V
must be tied to VCC.
CCQ
CCQ
+ 0.6V.
- 0.1V (not VCC). For 2.65V to
CCQ
3631A–FLASH–04/06
7
Figure 3-1. Data Polling Algorithm
(Configuration Register = 00)
Figure 3-2. Data Polling Algorithm
(Configuration Register = 01)
Read I/O7 - I/O0
I/O7 = Data?
NO
I/O3, I/O5 = 1?
Read I/O7 - I/O0
START
Addr = VA
NO
YES
Addr = VA
I/O7 = Data?
YES
YES
Read I/O7 - I/O0
Addr = VA
NO
I/O7 = 1?
I/O3, I/O5 = 1?
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
START
YES
YES
NO
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
8
AT49BV642D(T)
Program/Erase
Operation
Successful,
Device in
Read Mode
Note: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
3631A–FLASH–04/06
AT49BV642D(T)
Figure 3-3. Toggle Bit Algorithm
(Configuration Register = 00)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
NO
Toggle?
YES
NO
I/O3, I/O5 = 1?
Figure 3-4. Toggle Bit Algorithm
(Configuration Register = 01)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
NO
Toggle?
YES
NO
I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
NO
Toggle?
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Program/Erase
Operation
Successful,
Device in
Read Mode
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
NO
Toggle?
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
3631A–FLASH–04/06
9
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