ATMEL AT49BV640DT User Manual
BDTIC www.BDTIC.com/ATMEL
Features
•
Single Voltage Operation Read/Write: 2.65V - 3.6V
•
Access Time – 70 ns
•
Sector Erase Architecture
– One Hundred Twenty-seven 32K Word (64K Bytes) Main Sectors with
Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
•
Fast Word Program Time – 10 µs
•
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 100 ms
•
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending
Erase of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
•
Low-power Operation
– 10 mA Active
– 15 µA Standby
•
VPP Pin for Write Protection and Accelerated Program Operation
•
WP Pin for Sector Protection
•
RESET Input for Device Initialization
•
Flexible Sector Protection
•
Top or Bottom Boot Block Configuration Available
•
128-bit Protection Register
•
Minimum 100,000 Erase Cycles
•
Common Flash Interface (CFI)
•
Green (Pb/Halide-free/RoHS Compliant) Packaging
64-megabit
(4M x 16)
3-volt Only
Flash Memory
AT49BV640D
AT49BV640DT
1. Description
The AT49BV640D(T) is a 2.7-volt 64-megabit Flash memory organized as 4,194,304
words of 16 bits each. The memory is divided into 135 sectors for erase operations.
The device is offered in a 48-ball CBGA package. The device has CE
signals to avoid any bus contention. This device can be read or reprogrammed using
a single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place
the device in other operation modes such as program and erase. The device has
the capability to protect the data in any sector (see “Flexible Sector Protection” on
page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory.
The VPP pin provides data protection. When the V
and erase functions are inhibited. When V
and erase operations can be performed. With V
Program command) operation is accelerated.
PP
input is below 0.4V, the program
PP
is at 1.65V or above, normal program
at 10.0V, the program (Dual-word
PP
and OE control
3608C–FLASH–11/06
2. Pin Configurations
Pin Name Pin Function
A0 - A21 Addresses
CE
Chip Enable
OE
WE
RESET
Output Enable
Write Enable
Reset
VPP Write Protection and Power Supply for Accelerated Program Operations
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
VCCQ Output Power Supply
WP
Write Protect
2.1 48-ball CBGA – Top View
A7
A5
A3
CE
I/O0
I/O1
8
A4
A2
A1
A0
GND
OE
234567
1
A
A13
VPP
WP
A19
A8
A11
B
A14
RESET
A18
A17
WE
A10
C
A15
A21
A20
A6
A9
A12
D
A16
I/O11
I/O2
I/O8
I/O5
I/O14
E
VCCQ
I/O12
I/O3
I/O9
I/O6
I/O15
F
I/O13
I/O7
GND
I/O4
VCC
I/O10
2
AT49BV640D(T)
3608C–FLASH–11/06
3. Block Diagram
AT49BV640D(T)
I/O0 - I/O15
A0 - A21
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
OUTPUT
BUFFER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
STAT US
REGISTER
DATA
COMPARATOR
Y-GATING
MAIN
MEMORY
INPUT
BUFFER
DATA
REGISTER
COMMAND
REGISTER
WRITE STAT E
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
WP
VPP
VCC
GND
4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are
used to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE
applying a low-going pulse on the CE
on the first rising edge of the WE
the CE
affected by entering the command sequences.
4.2 Read
The AT49BV640D(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the
outputs. The outputs are put in the high impedance state whenever CE
dual-line control gives designers flexibility in preventing bus contention.
3608C–FLASH–11/06
input with CE low and OE high or by
input with WE low and OE high. The address is latched
or CE. Valid data is latched on the rising edge of the WE or
pulse, whichever occurs first. The addresses used in the command sequences are not
or OE is high. This
3
4.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
present device operation and puts the outputs of the device in a high-impedance state. When
a high level is reasserted on the RESET
4.4 Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is
a logical “1”. The individual sectors can be erased by using the Sector Erase command.
4.4.1 Sector Erase
The device is organized into 135 sectors (SA0 - SA134) that can be individually erased. The
Sector Erase command is a two-bus cycle operation. The sector address and the D0H Data
Input command are latched on the rising edge of WE
edge of WE
operation is internally controlled; it will automatically time to completion. The maximum time to
erase a sector is t
operation terminating immediately.
4.5 Word Programming
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus
cycle operation. The device will automatically generate the required internal program pulses.
pin halts the
pin, the device returns to read mode.
. The sector erase starts after the rising
of the second cycle provided the given sector has not been protected. The erase
. An attempt to erase a sector that has been protected will result in the
SEC
4.6 VPP Pin
Any commands except Read Status Register, Program Suspend and Program Resume written to the chip during the embedded programming cycle will be ignored. If a hardware reset
happens during programming, the data at the location being programmed will be corrupted.
Please note that a data “0” cannot be programmed back to a “1”; only erase operations can
convert “0”s to “1”s. Programming is completed after the specified t
gram status bit is a “1”, the device was not able to verify that the program operation was
performed successfully. The status register indicates the programming status. While the program sequence executes, status bit I/O7 is “0”.
The circuitry of the AT49BV640D(T) is designed so that the device cannot be programmed or
erased if the V
and erase operations can be performed. The VPP pin cannot be left floating.
voltage is less that 0.4V. When VPP is at 1.65V or above, normal program
PP
cycle time. If the pro-
BP
4
AT49BV640D(T)
3608C–FLASH–11/06
4.7 Read Status Register
The status register indicates the status of device operations and the success/failure of that
operation. The Read Status Register command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the memory,
issue a Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
AT49BV640D(T)
The contents of the status register [SR7:SR0] are latched on the falling edge of OE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE
or OE must be toggled with each subsequent status
read, or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing
the preferred operation (see Table 4-1).
Table 4-1. Status Register Bit Definition
WSMS ESS ES PRS VPPS PSS SLS R
76543210
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
or CE
SR4 = PROGRAM STATUS (PRS)
1 = Error in Programming
0 = Successful Programming
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR1 = SECTOR LOCK STATUS (SLS)
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
SR0 = Reserved for Future Enhancements (R)
Note: 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
3608C–FLASH–11/06
When this bit is set to “1”, WSM has attempted but failed to
program a word
The V
level. The WSM interrogates V
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
This bit is reserved for future use and should be masked out
when polling the status register.
status bit does not provide continuous indication of VPP
PP
level only after the Program or
PP
5
4.8 Clear Status Register
The WSM can set status register bits 1 through 7 and can clear bits 2, 6 and 7; but, the WSM
cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4 and 5 indicate various error
conditions, these bits can be cleared only through the Clear Status Register command. By
allowing the system software to control the resetting of these bits, several operations may be
performed (such as cumulatively programming several addresses or erasing multiple sectors
in sequence) before reading the status register to determine if an error occurred during those
operations. The status register should be cleared before beginning another operation. The
Read command must be issued before data can be read from the memory array. The status
register can also be cleared by resetting the device.
4.9 Flexible Sector Protection
The AT49BV640D(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is
read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all
sectors have their Softlock protection mode enabled.
4.9.1 Softlock and Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
4.9.2 Hardlock and Write Protect (WP
The Hardlock sector protection mode operates in conjunction with the Write Protection (WP
pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock
software command to the selected sector. The state of the Write Protect pin affects whether
the Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
)
)
6
AT49BV640D(T)
3608C–FLASH–11/06
AT49BV640D(T)
Table 4-2. Hardlock and Softlock Protection Configurations in Conjunction with WP
Erase/
Hard-
V
PP
/5V 0 0 0 Yes No sector is locked
V
CC
WP
lock
VCC/5V 0 0 1 No
V
/5V 0 1 1 No
CC
/5V 1 0 0 Yes No sector is locked.
V
CC
VCC/5V 1 0 1 No
V
/5V 1 1 0 Yes
CC
V
/5V 1 1 1 No
CC
V
IL
xx x No
Soft-
lock
Prog
Allowed? Comments
Sector is Softlocked. The Unlock
command can unlock the sector.
Hardlock protection mode is
enabled. The sector cannot be
unlocked.
Sector is Softlocked. The Unlock
command can unlock the sector.
Hardlock protection mode is
overridden and the sector is not
locked.
Hardlock protection mode is
overridden and the sector can be
unlocked via the Unlock command.
Erase and Program Operations
cannot be performed.
Figure 4-1. Sector Locking State Diagram
UNLOCKED LOCKED
60h/
D0h
6
60h/D0h
60h/
D0h
0
h
/
2
F
WP = V
WP = V
[000] [001]
=0
IL
[110]
=1
IH
[100]
60h/01h
h
60h/
2Fh
60h/
01h
60h/
2Fh
[011]
60h/
01h
[111]
[101]
60h/D0h = Unlock Comman d
60h/01h = Softlock Command
60h/2Fh = Hardlock Command
Power-Up/Rese t
Default
Hardlocked
Hardlocked is disabled by
WP = V
60h/
Power-Up/Rese t
2Fh
Default
IH
3608C–FLASH–11/06
Note: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a
sector is defined by the state of WP
and the two bits of the sector-lock status D[1:0].
7
4.9.3 Sector Protection Detection
A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode a read from
the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is
unlocked, softlocked, or hardlocked.
Table 4-3. Sector Protection Status
I/O1 I/O0 Sector Protection Status
0 0 Sector Not Locked
0 1 Softlock Enabled
1 0 Hardlock Enabled
1 1 Both Hardlock and Softlock Enabled
4.10 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and
then program or read data from a different sector within the memory. After the Erase Suspend
command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or
program data to any other sector within the device. An address is not required during the
Erase Suspend command. During a sector erase suspend, another sector cannot be erased.
To resume the sector erase operation, the system must write the Erase Resume command.
The Erase Resume command is a one-bus cycle command. The only valid commands while
erase is suspended are Read Status Register, Product ID Entry, CFI Query, Program, Program Resume, Erase Resume, Sector Softlock/Hardlock, and Sector Unlock.
4.11 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command
is given, the device requires a maximum of 10 µs to suspend the programming operation. After
the programming operation has been suspended, the system can then read from any other
word within the device. An address is not required during the program suspend operation. To
resume the programming operation, the system must write the Program Resume command.
The program suspend and resume are one-bus cycle commands. The command sequence for
the erase suspend and program suspend are the same, and the command sequence for the
erase resume and program resume are the same. Read, Read Status Register, Product ID
Entry, Program Resume are valid commands during a Program Suspend.
4.12 Product Identification
The product identification mode identifies the device and manufacturer as Atmel®. It may be
accessed by a software operation. For details, see “Operating Modes” on page 21.
8
AT49BV640D(T)
3608C–FLASH–11/06
4.13 128-bit Protection Register
The AT49BV640D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can
be locked out such that data in the sector cannot be reprogrammed. To program block B in the
protection register, the two-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 15. To lock out block B, the two-bus cycle
Lock Protection Register command must be used as shown in the “Command Definition
Table”. Data bit D1 must be zero during the second bus cycle. To determine whether block B
is locked out, use the status of block B protection command. If data bit D1 is zero, block B is
locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Regis-
ter Addressing Table” on page 16 for the address locations in the protection register. To read
the protection register, the Product ID Entry command is given followed by a normal read
operation from an address within the protection register. After determining whether block B is
protected or not, or reading the protection register, the Read command must be given to return
to the read mode.
4.14 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI
allows system software to query the installed device to determine the configurations, various
electrical and timing parameters, and functions supported by the device. CFI is used to allow
the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter
the CFI Query mode is a one-bus cycle command which requires writing data 98h to any
address. The CFI Query command can be written when the device is ready to read data or can
also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in “Common Flash Interface Definition Table”
on page 26. To return to the read mode, the read command should be issued.
AT49BV640D(T)
4.15 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV640D(T) in the following ways: (a) V
erase functions are inhibited. (b) Program inhibit: holding any one of OE
high inhibits program cycles. (c) Program inhibit: VPP is less than V
4.16 Input Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,
CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
device. The I/O lines can be driven from 0 to V
4.17 Output Levels
For the AT49BV640D(T), output high levels are equal to V
3.6V output levels, V
3608C–FLASH–11/06
sense: if VCC is below 1.8V (typical), the device is reset and the program and
CC
low, CE high or WE
.
ILPP
+ 0.6V.
CCQ
- 0.1V (not VCC). For 2.65V to
CCQ
must be tied to VCC.
CCQ
9
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