ATMEL AT49BV512-15VI, AT49BV512-15VC, AT49BV512-15TI, AT49BV512-15TC, AT49BV512-15PI Datasheet

Features

•

Single Supply Voltage, Range 2.7V to 3.6V

•

Single Supply for Read and Write

•

Fast Read Access Time - 120 ns

•

Internal Program Control and Timer

•

8K bytes Boot Block With Lockout

•

Fast Erase Cycle Time - 10 seconds

•

Byte By Byte Programming - 30

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low Power Dissipation

µµµµ

s/Byte typical

– 25 mA Active Current

µµµµ

–50

A CMOS Standby Current

•

Typical 10,000 Write Cycles

Description

The AT49BV512 is a 3-volt-only, 512K Flas h mem or ie s organized as 65,536 words of
8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
devices offer access times to 120 ns with power di ssipation of just 9 0 mW ov er the
commercial temperature range. When the devices are deselected, the CMOS standby
current is less than 50

To allow for simple in-system reprogrammability, the AT49BV512 does not require
high input voltages for programming. Three-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing
the entire 1 megabit of memory and then programming on a byte by byte basis. The

µµµµA.

(continued)

512K (64K x 8)
Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV512

™

Pin Configurations

Pin Name Function

A0 - A15 Addresses
CE
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

VSOP Top View (8 x 14 mm) or

TSOP Top View (8 x 20 mm)

1

A11

2

A9

3

A8

4

A13

5

A14

6

NC

7

WE

8

VCC

9

NC

10

NC

11

A15

12

A12

13

A7

14

A6

15

A5

16

A4

Chip Enable
Output En able
Write Enable

Type 1

DIP Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A15NCNC

I/O2

GND

1

I/O3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VCCWENC

323130

I/O4

I/O5

VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

Rev. 1026C–09/98

NC

NC
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

PLCC Top View

A12
432

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14151617181920

I/O1

1

typical byte programming time is a fast 30
program cycle can be optionally detected by the DATA

µµµµs. The end of a

poll­ing feature. Once the end of a byte program cycle has
been detected, a new acce ss for a re ad or progr am can
begin. The typical number of program and erase cycles is
in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a repro­gramming write lock out feature to provide data integrity.
The boot sector is desig ned to contai n user secure code,
and when the featur e is e nabled , th e boot sector is pe rma­nently protected from being reprogrammed.

Block Diagram

DATA INPUTS/OUTPUTS

VCC

GND

OE

WE

CE

ADDRESS

INPUTS

OE, CE AND WE

LOGIC

Y DECODER

X DECODER

I/O0 - I/O7

DATA LATCH

INPUT/OUTPUT

BUFFERS
Y-GATING

MAIN MEMORY

(56K BYTES)

OPTIONAL BOOT

BLOCK (8K BYTES)

FFFFH

2000H
1FFFH

0000H

Device Operation

READ:

When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE
line control gives designers flexibility in preventing bus con­tention.

ERASURE:

bytes memory array (or 56K bytes if the boot block featured
is used) must be erased. The erased state of the memory
bits is a logical “1”. The entire device can be erased at one
time by using a 6-byte software code. The software chip
erase code consists of 6-byte load commands to specific
address locat ions with a s pecif ic data patte rn (plea se refer
to the Chip Erase Cycle Waveforms).

After the software chip erase has been ini tiated , the devi ce
will internally time the eras e operatio n so that no ex ternal
clocks are required . The ma ximum tim e needed to erase
the whole chip is t
been enabled, the data in the boot sector will not be
erased.

BYTE PROGRAMMING:

erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be

The AT49BV512 is accessed like an EPROM.

and OE are low and WE is high, the data stored

or OE is high. This dual-

Before a byte can be reprogrammed, the 64K

. If the boot block lockout feature has

EC

Once the memory array is

programmed ba ck to a “1”; only era se oper ation s can con ­vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper­ation (please refer to the Com mand Definitions table). The
device will automatically generate the required internal pro­gram pulses.

The program cycle has addresses latched on the falling
edge of WE
latched on the rising edge of WE
first. Programming is c ompleted after the sp ecified t

or CE, whichever occurs last, and the data

or CE, whichever occurs

BP

cycle time. The DATA poll ing featu re may al so be use d to
indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the fe ature has be en enable d. The
size of the block is 8 K bytes. Thi s block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This fe ature do es not have to be acti­vated; the boot block’ s u sa ge a s a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.

Once the feature is enabl ed, the da ta in the bo ot block c an
no longer be erased or programmed. Data i n the main
memory block can still be changed through the regular pro­gramming method. To activate the lockout feature, a series
of six program commands to spec ific addresses wi th spe­cific data must be performed. Please refer to the Com­mand Definitions table.

BOOT BLOC K LOCKOUT DET ECTION:

A software
method is available to determine if programming of the boot
block section is l ocked out. W hen the device is in the sof t­ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H wil l s how i f pr ogram mi ng the b oot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock­out feature has been activated and the block cannot be
programmed. The software product i dentification code
should be used to return to standard operation.

PRODUCT IDENTIFICATION:

The product identif ication
mode identifies the device and manufac turer as Atmel. It
may be accessed by hardwar e or softwar e operatio n. The
hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for
the Atmel product.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

2

AT49BV512

AT49BV512

DATA POLLING:

The AT49BV512 features DATA

polling
to indicate the end of a program cycle. Dur ing a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O 7. Once the pro­gram cycle has been com pleted, true data is valid on all
outputs and the next cycle may begin . DATA

polling may

begin at any time during the program cycle.

TOGGLE BIT:

In addition to DATA

polling the AT49 BV512
provides another method for determining the end of a pro­gram or erase cycle. During a prog ra m or era se oper ati on ,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data

HARDWARE DATA PROTECTION:

Hardware features
protect against inadvertent programs to the AT49BV512 in
the following ways: (a) V

sense: if VCC is below 1.8V

CC

(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE

low, CE high or WE high
inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE

or CE inputs will not i ni t ia t e a pro-

gram cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, th e address inp uts and con trol inputs (OE

and WE) may be driven from 0 to 5.5V without

CE
adversely affecting the operation of the devic e. The I/O
lines can only be driven from 0 to V

+ 0.6V.

CC

will be read. Examinin g the toggl e bit may begin at a ny
time during a program cycle.

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Byte

Program

Bus

Cycles

4 5555 AA 2AAA 55 5555 A0 Addr D

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

IN

6th Bus

Cycle

,

Boot Block
Lockout

Product ID
Entry

Product ID
Exit

Product ID
Exit

Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.

(1)

(2)

(2)

2. Either one of the Product ID exit commands can be used.

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 90

3 5555 AA 2AAA 55 5555 F0

1 XXXX F0

Absolute Maximum Ratings*

Temperature Under Bias............................. ..-55°C to +125°C

Storage Temperature.....................................-65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the de vice at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

3

DC and AC Operating Range

AT49BV512-12 AT49BV512-15

Com. 0°C - 70°C0°C - 70°C

Operating Temperature (Case)

Ind. -40°C - 85°C-40°C - 85°C

V

Power Supply 2.7V to 3.6V 2.7V to 3.6V

CC

Operating Modes

Mode CE OE WE Ai I/O

Read V
Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

X

V

IL

V

IH

(1)

Program Inhibit X X V
Program Inhibit X V
Output Disable X V

IL

IH

Product Identification

Hardware V

Software

(5)

IL

V

IL

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.
= 12.0V ± 0.5V.

3. V

H

4. Manufacturer Code: 1FH, Device Code: 03H.

5. See details under Software Product Identification Entry/Exit.

DC Characteristics

V

IH

V

IL

Ai D
Ai D

OUT

IN

XXHigh Z

IH

X
XHigh Z

V

IH

A1 - A15 = VIL, A9 = VH,

A0 = V

IL

A1 - A15 = VIL, A9 = VH,

A0 = V

IH

A0 = VIL, A1 - A15 = V

A0 = VIH, A1 - A15 = V

(3)

(3)

IL

IL

Manufacturer Code

Device Code

Manufacturer Code
Device Code

(4)

(4)

(4)

(4)

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

(1)

I

CC

V

IL

V

IH

V

OL

V

OH

Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to V
VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

CC

CC

= 0 mA 25 mA

10 µA
10 µA
50 µA

1mA

Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -100 µA; VCC = 3.0V 2.4 V

Note: 1. In the erase mode, ICC is 50 mA.

4

AT49BV512