BDTIC www.BDTIC.com/ATMEL
Features
•
Single Voltage Read/Write Operation: 1.65V to 1.95V
•
Access Time – 80 ns
•
Sector Erase Architecture
– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
•
Fast Word Program Time – 10 µs
•
Fast Sector Erase Time – 100 ms
•
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word in the Non-suspending Sectors by Suspending
Programming of Any Other Word
•
Low-power Operation
– 10 mA Active
– 15 µA Standby
•
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
•
VPP Pin for Write Protection and Accelerated Program Operation
•
RESET Input for Device Initialization
•
Sector Lockdown Support
•
TSOP and CBGA Package Options
•
Top or Bottom Boot Block Configuration Available
•
128-bit Protection Register
•
Minimum 100,000 Erase Cycles
•
Common Flash Interface (CFI)
32-megabit
(2M x 16)
1.8-volt Only
Flash Memory
AT49SV322D
AT49SV322DT
1. Description
The AT49SV322D(T) is a 1.8-volt 32-megabit Flash memory organized as 2,097,152
words of 16 bits each. The memory is divided into 71 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device
has CE
or reprogrammed using a single power supply, making it ideally suited for in-system
programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the
capability to protect the data in any sector (see “Sector Lockdown” on page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory. The end of a program or an erase cycle is detected by the
READY/BUSY
The VPP pin provides data protection. When the V
and erase functions are inhibited. When V
and erase operations can be performed. With V
Program command) operation is accelerated.
and OE control signals to avoid any bus contention. This device can be read
pin, Data Polling or by the toggle bit.
input is below 0.4V, the program
PP
is at 1.65V or above, normal program
PP
at 10.0V, the program (Dual-word
PP
3623A–FLASH–7/06
A six-word command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-word program sequence is offered to further improve programming
time. After entering the six-word code, only single pulses on the write control lines are required
for writing into the device. This mode (Single Pulse Word Program) is exited by powering
down the device, or by pulsing the RESET
it back to V
not work while in this mode; if entered they will result in data being programmed into the
device. It is not recommended that the six-word code reside in the software of the final product
but only exist in external programming code.
2. Pin Configurations
Pin Name Function
A0 - A20 Addresses
CE
OE Output Enable
WE
RESET
RDY/BUSY READY/BUSY Output
VPP Write Protection
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
pin low for a minimum of 500 ns and then bringing
. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will
CC
Chip Enable
Write Enable
Reset
2.1 TSOP Top View (Type 1)
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
A19
10
A20
11
WE
NC
VPP
A18
A17
A7
A6
A5
A4
A3
A2
A1
12
13
14
15
16
17
18
19
20
21
22
23
24
RESET
RDY/BUSY
2.2 CBGA Top View (Ball Down)
2 3 456
1
48
A16
47
VCC
46
GND
45
I/O15
44
I/O7
43
I/O14
42
I/O6
41
I/O13
40
I/O5
39
I/O12
38
I/O4
37
VCC
36
I/O11
35
I/O3
34
I/O10
33
I/O2
32
I/O9
31
I/O1
30
I/O8
29
I/O0
28
OE
27
GND
26
CE
25
A0
G
A
A3
A7
RDY/BUSY
WE
A9
A13
B
A4
A17
VPP
RST
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
I/O0
I/O2
I/O5
I/O7
A16
F
CE
I/O8
I/O10
I/O12
I/O14
NC
OE
I/O9
I/O11
VCC
I/O13
I/015
H
VSS
I/O1
I/O3
I/O4
I/O6
VSS
2
AT49SV322D(T)
3623A–FLASH–7/06
3. Block Diagram
AT49SV322D(T)
I/O0 - I/O15
A0 - A20
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
OUTPUT
BUFFER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
STAT US
REGISTER
DATA
COMPARATOR
Y-GATING
MAIN
MEMORY
INPUT
BUFFER
DATA
REGISTER
COMMAND
REGISTER
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
RDY/BUSY
VPP
VCC
GND
4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be reset to the read or standby mode, depending
upon the state of the control line inputs. In order to perform other device functions, a series of
command sequences are entered into the device. The command sequences are shown in the
“Command Definition Table” on page 12 (I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying a low pulse on the WE
with CE
CE
or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.
Standard microprocessor write timings are used. The address locations used in the command
sequences are not affected by entering the command sequences.
4.2 Read
The AT49SV322D(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the
outputs. The outputs are put in the high impedance state whenever CE
dual-line control gives designers flexibility in preventing bus contention.
3623A–FLASH–7/06
or CE input
or WE low (respectively) and OE high. The address is latched on the falling edge of
or OE is high. This
3
4.3 Reset
4.4 Erase
4.4.1 Chip Erase
4.4.2 Sector Erase
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
the present device operation and puts the outputs of the device in a high impedance state.
When a high level is reasserted on the RESET
mode, depending upon the state of the control inputs.
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The entire device can be erased by using the Chip Erase command or individual
sectors can be erased by using the Sector Erase command.
The entire device can be erased at one time by using the six-word chip erase software code.
After the chip erase has been initiated, the device will internally time the erase operation so
that no external clocks are required. The maximum time to erase the chip is t
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that
can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE
command is latched on the rising edge of WE
WE
of the sixth cycle. The erase operation is internally controlled; it will automatically time to
completion. The maximum time to erase a sector is t
down feature is not enabled, the sector will erase (from the same Sector Erase command). An
attempt to erase a sector that has been protected will result in the operation terminating
immediately.
pin, the device returns to the read or standby
edge of the sixth cycle while the 30H data input
. The sector erase starts after the rising edge of
. When the sector programming lock-
SEC
EC
.
input halts
4.5 Word Programming
Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the internal device command register and is a four-bus
cycle operation. The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
time. The Data
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
4
AT49SV322D(T)
cycle
BP
Polling feature or the Toggle Bit feature may be used to indicate the end of a
3623A–FLASH–7/06
4.6 VPP Pin
The circuitry of the AT49SV322D(T) is designed so that the device cannot be programmed or
erased if the V
and erase operations can be performed. The VPP pin cannot be left floating.
4.7 Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11 and the following four sections
describe the function of these bits. To provide greater flexibility for system designers, the
AT49SV322D(T) contains a programmable configuration register. The configuration register
allows the user to specify the status bit operation. The configuration register can be set to one
of two different values, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the
configuration register is set to a “01”, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important
to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful
program or erase operation requires using the Product ID Exit command to return the device
to read mode. The default value (after power-up) for the configuration register is “00”. Using
the four-bus cycle Set Configuration Register command as shown in the “Command Definition
Table” on page 12, the value of the configuration register can be changed. Voltages applied to
the RESET
tion register will affect the operation of the I/O7 status bit as described below.
AT49SV322D(T)
voltage is less that 0.4V. When VPP is at 1.65V or above, normal program
PP
pin will not alter the value of the configuration register. The value of the configura-
4.7.1 Data
4.7.2 Toggle Bit
Polling
The AT49SV322D(T) features Data
configuration register is set to a “00”, during a program cycle an attempted read of the last
word loaded will result in the complement of the loaded data on I/O7. Once the program cycle
has been completed, true data is valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data
may begin at any time during the program cycle. Please see “Status Bit Table” on page 11 for
more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data
bit as shown in the algorithm in Figures 4-1 and 4-2 on page 9.
In addition to Data
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on
page 11 for more details.
Polling status bit must be used in conjunction with the erase/program and VPP status
Polling the AT49SV322D(T) provides another method for determining the
Polling to indicate the end of a program cycle. If the status
Polling
3623A–FLASH–7/06
The toggle bit status bit should be used in conjunction with the erase/program and V
bit as shown in the algorithm in Figures 4-3 and 4-4 on page 10.
status
PP
5
4.7.3 Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation
has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is
unable to verify that an erase or a word program operation has been successfully performed. If
a program (Sector Erase) command is issued to a protected sector, the protected sector will
not be programmed (erased). The device will go to a status read mode and the I/O5 status bit
will be set high, indicating the program (erase) operation did not complete as requested. Once
the erase/program status bit has been set to a “1”, the system must write the Product ID Exit
command to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 11 for more
details.
4.7.4 VPP Status Bit
The AT49SV322D(T) provides a status bit on I/O3, which provides information regarding the
voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP
pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be
a “1”. Once the V
command to return to the read mode. On the other hand, if the voltage level is high enough to
perform a program or erase operation successfully, the V
see “Status Bit Table” on page 11 for more details.
4.8 Sector Lockdown
Each sector has a programming lockdown feature. This feature prevents programming of data
in the designated sectors once the feature has been enabled. These sectors can contain
secure code that is used to bring up the system. Enabling the lockdown feature will allow the
boot code to stay in the device while data in the rest of the device is updated. This feature
does not have to be activated; any sector’s usage as a write-protected region is optional to the
user.
status bit has been set to a “1”, the system must write the Product ID Exit
PP
status bit will output a “0”. Please
PP
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
4.8.1 Sector Lockdown Detection
A software method is available to determine if programming of a sector is locked down. When
the device is in the software product identification mode (see “Software Product Identification
Entry/Exit” sections on page 25), a read from address location 00002H within a sector will
show if programming the sector is locked down. If the data on I/O0 is low, the sector can be
programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and
the sector cannot be programmed. The software product identification exit code should be
used to return to standard operation.
6
AT49SV322D(T)
3623A–FLASH–7/06
4.8.2 Sector Lockdown Override
The only way to unlock a sector that is locked down is through reset or power-up cycles. After
power-up or reset, the content of a sector that is locked down can be erased and
reprogrammed.
4.9 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector or chip erase operation
and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase
operation. After the erase operation has been suspended, the system can then read data or
program data to any other sector within the device. An address is not required during the
Erase Suspend command. During a sector erase suspend, another sector cannot be erased.
To resume the sector erase operation, the system must write the Erase Resume command.
The Erase Resume command is a one-bus cycle command. The device also supports an
erase suspend during a complete chip erase. While the chip erase is suspended, the user can
read from any sector within the memory that is protected. The command sequence for a chip
erase suspend and a sector erase suspend are the same.
4.10 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command
is given, the device requires a maximum of 10 µs to suspend the programming operation. After
the programming operation has been suspended, the system can then read data from any
other word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the
programming operation, the system must write the Program Resume command. The program
suspend and resume are one-bus cycle commands. The command sequence for the erase
suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same.
AT49SV322D(T)
4.11 Product Identification
The product identification mode identifies the device and manufacturer as Atmel®. It is
accessed using a software operation.
For details, see “Operating Modes” on page 18 or “Software Product Identification Entry/Exit”
sections on page 25.
4.12 128-bit Protection Register
The AT49SV322D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can
be locked out such that data in the block cannot be reprogrammed. To program block B in the
protection register, the four-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle
Lock Protection Register command must be used as shown in the “Command Definition
Table” . Data bit D1 must be zero during the fourth bus cycle. All other data bits during the
fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID
Entry command is given followed by a read operation from address 80H. If data bit D1 is zero,
3623A–FLASH–7/06
7
block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protec-
tion Register Addressing Table” on page 13 for the address locations in the protection register.
To read the protection register, the Product ID Entry command is given followed by a normal
read operation from an address within the protection register. After determining whether block
B is protected or not, or reading the protection register, the Product ID Exit command must be
given prior to performing any other operation.
4.13 RDY/BUSY
An open-drain READY/BUSY output pin provides another method of detecting the end of a
program or erase operation. RDY/BUSY
erase cycles and is released at the completion of the cycle. The open-drain connection allows
for OR-tying of several devices to the same RDY/BUSY
page 11 for more details.
4.14 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI
allows system software to query the installed device to determine the configurations, various
electrical and timing parameters, and functions supported by the device. CFI is used to allow
the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter
the CFI Query mode is a one-bus cycle command which requires writing data 98h to address
55h. The CFI Query command can be written when the device is ready to read data or can
also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in “Common Flash Interface Definition Table”
on page 26. To exit the CFI Query mode, the product ID exit command must be given.
is actively pulled low during the internal program and
line. Please see “Status Bit Table” on
4.15 Hardware Data Protection
The Hardware Data Protection feature protects against inadvertent programs to the
AT49SV322D(T) in the following ways: (a) V
gram function is inhibited. (b) V
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE
V
is less than V
PP
4.16 Input Levels
While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs
(OE
, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of
the device. The I/O lines can only be driven from 0 to V
sense: if VCC is below 1.65V (typical), the pro-
CC
power-on delay: once VCC has reached the VCC sense level,
CC
low, CE high or WE high inhibits program cycles. (d) Program inhibit:
.
ILPP
+ 0.6V.
CC
8
AT49SV322D(T)
3623A–FLASH–7/06
Figure 4-1. Data Polling Algorithm
(Configuration Register = 00)
Figure 4-2. Data Polling Algorithm
(Configuration Register = 01)
Read I/O7 - I/O0
I/O7 = Data?
NO
I/O3, I/O5 = 1?
Read I/O7 - I/O0
START
Addr = VA
NO
YES
Addr = VA
YES
Read I/O7 - I/O0
I/O7 = Data?
NO
I/O3, I/O5 = 1?
Read I/O7 - I/O0
START
Addr = VA
NO
YES
Addr = VA
YES
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
Program/Erase
Operation
Successful,
Device in
Read Mode
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
9
AT49SV322D(T)
3623A–FLASH–7/06
AT49SV322D(T)
Figure 4-3. Toggle Bit Algorithm
(Configuration Register = 00)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
NO
Toggle Bit =
Toggle?
YES
I/O3, I/O5 = 1?
NO
Figure 4-4. Toggle Bit Algorithm
(Configuration Register = 01)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
NO
Toggle?
YES
NO
I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
NO
Program/Erase
Operation
Successful, Device
in Read Mode
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
NO
Toggle?
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
3623A–FLASH–7/06
10
AT49SV322D(T)
5. Status Bit Table
Status Bit
I/O7 I/O7 I/O6 I/O5
Configuration Register 00 01 00/01 00/01 00/01 00/01 00/01
Programming I/O7
Erasing 0 0 TOGGLE 0 0 TOGGLE 0
Erase Suspended & Read
Erasing Sector
11100TOGGLE1
0 TOGGLE 0 0 1 0
(1)
I/O3
(2)
I/O2 RDY/BUSY
Erase Suspended & Read
Non-erasing Sector
Erase Suspended &
Program Non-erasing Sector
Erase Suspended &
Program Suspended and
Reading from Nonsuspended Sectors
Program Suspended & Read
Programming Sector
Program Suspended & Read
Non-programming Sector
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the V
DATA DATA DATA DATA DATA DATA 1
I/O7
DATA DATA DATA DATA DATA DATA 1
I/O71100TOGGLE1
DATA DATA DATA DATA DATA DATA 1
0 TOGGLE 0 0 TOGGLE 0
level is not high enough to successfully perform program and erase operations.
PP
3623A–FLASH–7/06
11
6. Command Definition Table
1st Bus
Command
Sequence
Bus
Cycles
Read 1 Addr D
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
OUT
Chip Erase 6 555 AA AAA
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
Word Program 4 555 AA AAA 55 555 A0 Addr D
Dual Word
(4)
Program
Enter Single Pulse
Program Mode
Single Pulse Word
Program
5 555 AA AAA 55 555 E0 Addr0 D
6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0
1AddrD
IN
Sector Lockdown 6 555 AA AAA
Erase/Program
Suspend
Erase/Program
Resume
1 XXX B0
1 XXX 30
Product ID Entry 3 555 AA AAA 55 555 90
(11)
(6)
(6)
3 555 AA AAA 55 555 F0
1 XXX F0
(7)
4 555 AA AAA 55 555 C0 Addr
4 555 AA AAA 55 555 C0 080 X0
4 555 AA AAA 55 555 90 80 D
4 555 AA AAA 55 555 D0 XXX 00/01
1 X55 98
Product ID Exit
Product ID Exit
Program Protection
Register
Lock Protection
Register - Block B
Status of Block B
Protection
Set Configuration
Register
CFI Query
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are don’t care.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 17 for
details).
4. This fast programming option enables the user to program two words in parallel only when V
Addr0 and Addr1, of the two words, D
manufacturing purposes only.
5. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or
power cycled.
6. Either one of the Product ID Exit commands can be used.
7. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
8. Any addresses within the user programmable protection register region. Address locations are shown on “Protection Regis-
ter Addressing Table” on page 13.
9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
10. The default state (after power-up) of the configuration register is “00”.
11. When accessing the data in the CFI table, the address format is A15 - A0 (Hex).
2nd Bus
Cycle
(2)
(2)
and D
IN0
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
55 555 80 555 AA AAA 55 555 10
(3)
IN
(9)
(10)
Addr1 D
= 9.5V. The Addresses,
PP
IN1
(3)(5)
IN0
55 555 80 555 AA AAA 55 SA
(7)
(8)
, must only differ in address A0. This command should be used during
IN1
D
OUT
IN
30
60
12
AT49SV322D(T)
3623A–FLASH–7/06
7. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
+ 0.6V
CC
AT49SV322D(T)
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on V
with Respect to Ground ....................................-0.6V to + 9.5V
PP
8. Protection Register Addressing Table
AddressUseBlockA7A6A5A4A3A2A1A0
81FactoryA10000001
82FactoryA10000010
83FactoryA10000011
84FactoryA10000100
85UserB10000101
86UserB10000110
87UserB10000111
88UserB10001000
Notes: 1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A20 - A8 = 0.
3623A–FLASH–7/06
13
9. AT49SV322D – Sector Address Table
Sector Size (Bytes/Words) Address Range (A20 - A0)
SA0 8K/4K 00000 - 00FFF
SA1 8K/4K 01000 - 01FFF
SA2 8K/4K 02000 - 02FFF
SA3 8K/4K 03000 - 03FFF
SA4 8K/4K 04000 - 04FFF
SA5 8K/4K 05000 - 05FFF
SA6 8K/4K 06000 - 06FFF
SA7 8K/4K 07000 - 07FFF
SA8 64K/32K 08000 - 0FFFF
SA9 64K/32K 10000 - 17FFF
SA10 64K/32K 18000 - 1FFFF
SA11 64K/32K 20000 - 27FFF
SA12 64K/32K 28000 - 2FFFF
SA13 64K/32K 30000 - 37FFF
SA14 64K/32K 38000 - 3FFFF
SA15 64K/32K 40000 - 47FFF
SA16 64K/32K 48000 - 4FFFF
SA17 64K/32K 50000 - 57FFF
SA18 64K/32K 58000 - 5FFFF
SA19 64K/32K 60000 - 67FFF
SA20 64K/32K 68000 - 6FFFF
SA21 64K/32K 70000 - 77FFF
SA22 64K/32K 78000 - 7FFFF
SA23 64K/32K 80000 - 87FFF
SA24 64K/32K 88000 - 8FFFF
SA25 64K/32K 90000 - 97FFF
SA26 64K/32K 98000 - 9FFFF
SA27 64K/32K A0000 - A7FFF
SA28 64K/32K A8000 - AFFFF
SA29 64K/32K B0000 - B7FFF
SA30 64K/32K B8000 - BFFFF
SA31 64K/32K C0000 - C7FFF
SA32 64K/32K C8000 - CFFFF
SA33 64K/32K D0000 - D7FFF
SA34 64K/32K D8000 - DFFFF
SA35 64K/32K E0000 - E7FFF
SA36 64K/32K E8000 - EFFFF
SA37 64K/32K F0000 - F7FFF
14
AT49SV322D(T)
3623A–FLASH–7/06
AT49SV322D(T)
9. AT49SV322D – Sector Address Table (Continued)
Sector Size (Bytes/Words) Address Range (A20 - A0)
SA38 64K/32K F8000 - FFFFF
SA39 64K/32K 100000 - 107FFF
SA40 64K/32K 108000 - 10FFFF
SA41 64K/32K 110000 - 117FFF
SA42 64K/32K 118000 - 11FFFF
SA43 64K/32K 120000 - 127FFF
SA44 64K/32K 128000 - 12FFFF
SA45 64K/32K 130000 - 137FFF
SA46 64K/32K 138000 - 13FFFF
SA47 64K/32K 140000 - 147FFF
SA48 64K/32K 148000 - 14FFFF
SA49 64K/32K 150000 - 157FFF
SA50 64K/32K 158000 - 15FFFF
SA51 64K/32K 160000 - 167FFF
SA52 64K/32K 168000 - 16FFFF
SA53 64K/32K 170000 - 177FFF
SA54 64K/32K 178000 - 17FFFF
SA55 64K/32K 180000 - 187FFF
SA56 64K/32K 188000 - 18FFFF
SA57 64K/32K 190000 - 197FFF
SA58 64K/32K 198000 - 19FFFF
SA59 64K/32K 1A0000 - 1A7FFF
SA60 64K/32K 1A8000 - 1AFFFF
SA61 64K/32K 1B0000 - 1B7FFF
SA62 64K/32K 1B8000 - 1BFFFF
SA63 64K/32K 1C0000 - 1C7FFF
SA64 64K/32K 1C8000 - 1CFFFF
SA65 64K/32K 1D0000 - 1D7FFF
SA66 64K/32K 1D8000 - 1DFFFF
SA67 64K/32K 1E0000 - 1E7FFF
SA68 64K/32K 1E8000 - 1EFFFF
SA69 64K/32K 1F0000 -1F7FFF
SA70 64K/32K 1F8000 - 1FFFFF
3623A–FLASH–7/06
15
10. AT49SV322DT – Sector Address Table
Sector Size (Bytes/Words) Address Range (A20 - A0)
SA0 64K/32K 00000 - 07FFF
SA1 64K/32K 08000 - 0FFFF
SA2 64K/32K 10000 - 17FFF
SA3 64K/32K 18000 - 1FFFF
SA4 64K/32K 20000 - 27FFF
SA5 64K/32K 28000 - 2FFFF
SA6 64K/32K 30000 - 37FFF
SA7 64K/32K 38000 - 3FFFF
SA8 64K/32K 40000 - 47FFF
SA9 64K/32K 48000 - 4FFFF
SA10 64K/32K 50000 - 57FFF
SA11 64K/32K 58000 - 5FFFF
SA12 64K/32K 60000 - 67FFF
SA13 64K/32K 68000 - 6FFFF
SA14 64K/32K 70000 - 77FFF
SA15 64K/32K 78000 - 7FFFF
SA16 64K/32K 80000 - 87FFF
SA17 64K/32K 88000 - 8FFFF
SA18 64K/32K 90000 - 97FFF
SA19 64K/32K 98000 - 9FFFF
SA20 64K/32K A0000 - A7FFF
SA21 64K/32K A8000 - AFFFF
SA22 64K/32K B0000 - B7FFF
SA23 64K/32K B8000 - BFFFF
SA24 64K/32K C0000 - C7FFF
SA25 64K/32K C8000 - CFFFF
SA26 64K/32K D0000 - D7FFF
SA27 64K/32K D8000 - DFFFF
SA28 64K/32K E0000 - E7FFF
SA29 64K/32K E8000 - EFFFF
SA30 64K/32K F0000 - F7FFF
SA31 64K/32K F8000 - FFFFF
SA32 64K/32K 100000 - 107FFF
SA33 64K/32K 108000 - 10FFFF
SA34 64K/32K 110000 - 117FFF
SA35
SA36
SA37 64K/32K 128000 - 12FFFF
64K/32K 118000 - 11FFFF
64K/32K 120000 - 127FFF
16
AT49SV322D(T)
3623A–FLASH–7/06
AT49SV322D(T)
10. AT49SV322DT – Sector Address Table (Continued)
Sector Size (Bytes/Words) Address Range (A20 - A0)
SA38 64K/32K 130000 - 137FFF
SA39 64K/32K 138000 - 13FFFF
SA40 64K/32K 140000 - 147FFF
SA41 64K/32K 148000 - 14FFFF
SA42 64K/32K 150000 - 157FFF
SA43 64K/32K 158000 - 15FFFF
SA44 64K/32K 160000 - 167FFF
SA45 64K/32K 168000 - 16FFFF
SA46 64K/32K 170000 - 177FFF
SA47 64K/32K 178000 - 17FFFF
SA48 64K/32K 180000 - 187FFF
SA49 64K/32K 188000 - 18FFFF
SA50 64K/32K 190000 - 197FFF
SA51 64K/32K 198000 - 19FFFF
SA52 64K/32K 1A0000 - 1A7FFF
SA53 64K/32K 1A8000 - 1AFFFF
SA54 64K/32K 1B0000 - 1B7FFF
SA55 64K/32K 1B8000 - 1BFFFF
SA56 64K/32K 1C0000 - 1C7FFF
SA57 64K/32K 1C8000 - 1CFFFF
SA58 64K/32K 1D0000 - 1D7FFF
SA59 64K/32K 1D8000 - 1DFFFF
SA60 64K/32K 1E0000 - 1E7FFF
SA61 64K/32K 1E8000 - 1EFFFF
SA62 64K/32K 1F0000 - 1F7FFF
SA63 8K/4K 1F8000 - 1F8FFF
SA64 8K/4K 1F9000 - 1F9FFF
SA65 8K/4K 1FA000 - 1FAFFF
SA66 8K/4K 1FB000 - 1FBFFF
SA67 8K/4K 1FC000 - 1FCFFF
SA68 8K/4K 1FD000 - 1FDFFF
SA69 8K/4K 1FE000 - 1FEFFF
SA70 8K/4K 1FF000 - 1FFFFF
3623A–FLASH–7/06
17
11. DC and AC Operating Range
AT49SV322D(T)-80
Operating Temperature (Case) Ind. -40°C - 85°C
VCC Power Supply 1.65V to 1.95V
12. Operating Modes
V
PP
X
IHPP
(1)
(2)
(4)
Ai I/O
Ai D
Ai D
X
(5)
V
ILPP
X X High-Z
A0 = VIL, A1 - A20 = V
A0 = VIH, A1 - A20 = V
Manufacturer Code
IL
IL
Mode CE OE WE RESET V
Read V
Program/Erase
(3)
Standby/Program Inhibit V
V
V
IL
V
IL
X
IH
XXV
Program Inhibit
XV
XXX V
Output Disable X V
Reset XXX V
Product Identification
Software
(6)
V
IL
IH
(2)
IL
IH
IH
V
IL
XVIHX X High-Z
IH
XVIHX
XVIHX High-Z
V
IH
V
IH
V
IH
IH
IL
V
IH
Notes: 1. The VPP pin can be tied to VCC. For faster program operations, VPP can be set to 9.5V ± 0.5V.
2. X can be V
or VIH.
IL
3. Refer to “Program Cycle Waveforms” on page 23.
4. V
5. V
(min) = 1.65V
IHPP
(max) = 0.4V.
ILPP
6. See details under “Software Product Identification Entry/Exit” on page 25.
7. Manufacturer Code: 001FH.
Device Code: 01DBH - AT49SV322D; 01D1H - AT49SV322DT.
OUT
IN
Device Code
(7)
(7)
18
AT49SV322D(T)
3623A–FLASH–7/06
AT49SV322D(T)
13. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
I
I
I
I
I
V
V
V
V
V
V
LI
LO
SB
CC
CC1
PP1
IL
IH
OL1
OL2
OH1
OH2
(1)
Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = VCC - 0.3V to V
V
Active Read Current f = 5 MHz; I
CC
VCC Programming Current 25 mA
VPP Input Load Current 10 µA
Input Low Voltage 0.4 V
Input High Voltage VCC - 0.2 V
Output Low Voltage IOL = 2.1 mA 0.25 V
Output Low Voltage IOL = 1.0 mA 0.1 V
Output High Voltage IOH = -400 µA 1.4 V
Output High Voltage IOH = -100 µA VCC - 0.1 V
Note: 1. In the erase mode, ICC is 25 mA.
= 0V to V
I/O
CC
CC
CC
= 0 mA 10 15 mA
OUT
15 25 µA
2µA
2µA
3623A–FLASH–7/06
19
14. Input Test Waveforms and Measurement Level
9
tR, tF < 5 ns
15. Output Test Load
16. Pin Capacitance
f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
(1)
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
46pFV
812pFV
IN
OUT
= 0V
= 0V
20
AT49SV322D(T)
3623A–FLASH–7/06
17. AC Read Characteristics
Symbol Parameter
AT49SV322D(T)
AT49SV322D(T)-80
UnitsMin Max
t
t
t
t
t
t
t
RC
ACC
CE
OE
DF
OH
RO
(1)
(2)
(3)(4)
Read Cycle Time 80 ns
Address to Output Delay 80 ns
CE to Output Delay 80 ns
OE to Output Delay 0 20 ns
CE or OE to Output Float 0 25 ns
Output Hold from OE, CE or Address,
whichever occurred first
RESET to Output Delay 100 ns
18. AC Read Waveforms
ADDRESS
CE
OE
(1)(2)(3)(4)
t
RC
ADDRESS VALID
t
CE
t
OE
0ns
t
DF
RESET
OUTPUT
Notes: 1. CE may be delayed up to t
2. OE
may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t
3. t
is specified from OE or CE, whichever occurs first (CL = 5 pF).
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
t
ACC
t
RO
HIGH Z
- tCE after the address transition without impact on t
ACC
OUTPUT
VALID
t
OH
.
ACC
- tOE after an address change
ACC
3623A–FLASH–7/06
21
19. AC Word Load Characteristics
Symbol Parameter Min Max Units
t
AS
t
AH
t
CS
t
CH
t
WP
t
WPH
t
DS
t
DH
, t
OES
, t
OEH
Address, OE Setup Time 0 ns
Address Hold Time 25 ns
Chip Select Setup Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)25 ns
Write Pulse Width High 15 ns
Data Setup Time 25 ns
Data, OE Hold Time 0 ns
20. AC Word Load Waveforms
20.1 WE Controlled
20.2 CE Controlled
22
AT49SV322D(T)
3623A–FLASH–7/06
AT49SV322D(T)
21. Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
t
BPD
t
AS
t
AH
t
DS
t
DH
t
WP
t
WPH
t
WC
t
RP
t
EC
t
SEC1
t
SEC2
t
ES
t
PS
Word Programming Time 10 120 µs
Word Programming Time in Dual Programming Mode 5 60 µs
Address Setup Time 0 ns
Address Hold Time 25 ns
Data Setup Time 25 ns
Data Hold Time 0 ns
Write Pulse Width 25 ns
Write Pulse Width High 15 ns
Write Cycle Time 70 ns
Reset Pulse Width 500 ns
Chip Erase Cycle Time 33 seconds
Sector Erase Cycle Time (4K Word Sectors) 0.1 2.0 seconds
Sector Erase Cycle Time (32K Word Sectors) 0.5 6.0 seconds
Erase Suspend Time 15 µs
Program Suspend Time 10 µs
22. Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
WE
A0 - A20
DATA
t
t
AS
AH
555 555
t
WC
AA
t
WP
t
DH
AAA
t
DS
t
WPH
55
23. Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
A0-A20
DATA
WE
t
AS
555
t
WC
WP
t
AH
AAA AAA
t
DS
AA
WORD 0
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under “Command Definition Table” on page 12.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
t
WPH
t
DH
555
55 55
WORD 1 WORD 2
80
t
BP
Note 3
555
AA
t
EC
ADDRESS
555
AA
WORD 3
INPUT
DATA
WORD 4
Note 2
WORD 5
A0
3623A–FLASH–7/06
23
24. Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
t
t
t
DH
OEH
OE
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 21.
25. Data Polling Waveforms
WE
CE
t
OE
OEH
ns
t
DH
I/O7
A0-A20
26. Toggle Bit Characteristics
(1)
t
OE
HIGH Z
An
An
An
An
An
t
WR
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 50 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
27. Toggle Bit Waveforms
spec in “AC Read Characteristics” on page 21.
OE
(1)(2)(3)
ns
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
24
AT49SV322D(T)
specification must be met by the toggling
OEHP
3623A–FLASH–7/06
28. Software Product Identification
Entry
(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 90
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
(2)(3)(5)
MODE
29. Software Product Identification
(1)(6)
Exit
LOAD DATA AA
TO
ADDRESS 555
OR
LOAD DATA F0
TO
ANY ADDRESS
30. Sector Lockdown Enable
Algorithm
(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
Notes: 1.
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), and A11 - A20
(Don’t Care).
2.
A1 - A20 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = V
. Additional Device Code is
IH
read from address 0003H.
3.
The device does not remain in identification mode if
powered down.
4.
The device returns to standard operation mode.
5.
Manufacturer Code: 001FH
Device Code: 01DBH – AT49SV322D;
01D1H – AT49SV322DT.
Additional Device Code: 0001H – AT49SV322D(T)
6.
Either one of the Product ID Exit commands can be used.
Notes: 1.
LOAD DATA 60
TO
SECTOR ADDRESS
PAUSE 200 µs
(2)
Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), and A11 - A20
(Don’t Care).
2.
Sector Lockdown feature enabled.
25
AT49SV322D(T)
3623A–FLASH–7/06
31. Common Flash Interface Definition Table
Address Data
CommentsAT49SV322D(T) AT49SV322D(T)
10h 0051h “Q”
11h 0052h “R”
12h 0059h “Y”
13h 0002h
14h 0000h
15h 0041h
16h 0000h
17h 0000h
18h 0000h
19h 0000h
1Ah 0000h
1Bh 0017h VCC min write/erase
1Ch 0019h VCC max write/erase
1Dh 0090h VPP min voltage
1Eh 00A0h VPP max voltage
1Fh 0004h Typ word write – 10 µs
20h 0002h Typ dual word program time – 5 µs
21h 0009h Typ sector erase, 500 ms
22h 000Fh Typ chip erase, 33,000 ms
23h 0004h Max word write/typ time
24h 0004h Max dual word program time/typ time
25h 0004h Max sector erase/typ sector erase
26h 0004h Max chip erase/ typ chip erase
27h 0016h Device size
28h 0001h x16 device
29h 0000h x16 device
2Ah 0002h Maximum number of bytes in multiple byte write = 4
2Bh 0000h Maximum number of bytes in multiple byte write = 4
2Ch 0002h 2 regions, x = 2
2Dh 0007h 8K bytes, Y = 7
2Eh 0000h 8K bytes, Y = 7
2Fh 0020h 8K bytes, Z = 32
30h 0000h 8K bytes, Z = 32
31h 003Eh 64K bytes, Y = 62
32h 0000h 64K bytes, Y = 62
33h 0000h 64K bytes, Z = 256
34h 0001h 64K bytes, Z = 256
26
AT49SV322D(T)
3623A–FLASH–7/06
31. Common Flash Interface Definition Table (Continued)
Address Data
CommentsAT49SV322D(T) AT49SV322D(T)
VENDOR SPECIFIC EXTENDED QUERY
41h 0050h “P”
42h 0052h “R”
43h 0049h “I”
44h 0031h Major version number, ASCII
45h 0030h Minor version number, ASCII
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported,
46h 0087h
0000h (top)
47h
48h 0000h
49h 0000h
4Ah 0080h Location of protection register lock byte, the section’s first byte
4Bh 0003h # of bytes in the factory prog section of prot register – 2*n
4Ch 0003h # of bytes in the user prog section of prot register – 2*n
or
0001h (bottom)
0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
Bit 0 – top (“0”) or bottom (“1”) boot block device, undefined bits are “0”
Bit 0 – 4 word linear burst with wrap around,
0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around,
0 – no, 1 – yes
Bit 2 – continuos burst, 0 - no, 1 - yes
Undefined bits are “0”
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
AT49SV322D(T)
3623A–FLASH–7/06
27
32. Ordering Information
32.1 Green Package (Pb/Halide-free)
I
(mA)
t
ACC
(ns)
80 15 0.025
80 15 0.025
CC
AT49SV322D-80CU
AT49SV322D-80TU
AT49SV322DT-80CU
AT49SV322DT-80TU
Ordering Code Package Operation RangeActive Standby
48C17
48T
48C17
48T
Industrial
(-40° to 85° C)
Package Type
48C17 48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48T 48-lead, Plastic Thin Small Outline Package (TSOP)
28
AT49SV322D(T)
3623A–FLASH–7/06
33. Packaging Information
33.1 48C17 – CBGA
AT49SV322D(T)
A1 Ball ID
1.50 REF
E
D
Top View
A
A1
Side View
E1
A
B
C
D
E
F
G
H
6543 21
Øb
Bottom View
A1 Ball Corner
e
D1
e
2.20 REF
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
E 6.9 7.0 7.1
E1 4.0 TYP
D 9.9 10.0 10.1
D1 5.6 TYP
A – – 1.0
A1 0.20 – –
e0.80 BSC
Øb 0.35 TYP
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
3623A–FLASH–7/06
TITLE
48C17, 48-ball (6 x 8 Array), 0.80 mm Pitch,
7.0 x 10.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
48C17
10/26/05
REV.
B
29
33.2 48T – TSOP
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 11.90 12.00 12.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
MIN
c
L1
GAGE PLANE
(Unit of Measure = mm)
NOM
MAX
NOTE
30
2325 Orchard Parkway
R
San Jose, CA 95131
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
AT49SV322D(T)
TITLE
DRAWING NO.
48T
3623A–FLASH–7/06
10/18/01
REV.
B
34. Revision History
Revision No. History
Revision A – July 2006
• Initial Release
AT49SV322D(T)
3623A–FLASH–7/06
31
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