ATMEL AT49BV322DT User Manual

BDTIC www.BDTIC.com/ATMEL

Features

•

Single Voltage Read/Write Operation: 1.65V to 1.95V

•

Access Time – 80 ns

•

Sector Erase Architecture

– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout – Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

•

Fast Word Program Time – 10 µs

•

Fast Sector Erase Time – 100 ms

•

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Word in the Non-suspending Sectors by Suspending

Programming of Any Other Word

•

Low-power Operation

– 10 mA Active – 15 µA Standby

•

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

•

VPP Pin for Write Protection and Accelerated Program Operation

•

RESET Input for Device Initialization

•

Sector Lockdown Support

•

TSOP and CBGA Package Options

•

Top or Bottom Boot Block Configuration Available

•

128-bit Protection Register

•

Minimum 100,000 Erase Cycles

•

Common Flash Interface (CFI)

32-megabit (2M x 16)

1.8-volt Only Flash Memory

AT49SV322D AT49SV322DT

1. Description

The AT49SV322D(T) is a 1.8-volt 32-megabit Flash memory organized as 2,097,152 words of 16 bits each. The memory is divided into 71 sectors for erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device has CE or reprogrammed using a single power supply, making it ideally suited for in-system programming.

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see “Sector Lockdown” on page 6).

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY

The VPP pin provides data protection. When the V and erase functions are inhibited. When V and erase operations can be performed. With V Program command) operation is accelerated.

and OE control signals to avoid any bus contention. This device can be read

pin, Data Polling or by the toggle bit.

input is below 0.4V, the program

is at 1.65V or above, normal program

at 10.0V, the program (Dual-word

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A six-word command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-word program sequence is offered to further improve programming time. After entering the six-word code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET it back to V not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-word code reside in the software of the final product but only exist in external programming code.

2. Pin Configurations

Pin Name Function

A0 - A20 Addresses

OE Output Enable

RESET

RDY/BUSY READY/BUSY Output

VPP Write Protection

I/O0 - I/O15 Data Inputs/Outputs

NC No Connect

pin low for a minimum of 500 ns and then bringing

. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will

Chip Enable

Write Enable

Reset

2.1 TSOP Top View (Type 1)

A15

A14

A13

A12

A11

A10

A19

A20

VPP

A18 A17

A7 A6 A5 A4 A3 A2 A1

12 13 14 15 16 17 18 19 20 21 22 23 24

RESET

RDY/BUSY

2.2 CBGA Top View (Ball Down)

2 3 456

A16

VCC

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

RDY/BUSY

A13

A17

VPP

RST

A12

A18

A10

A14

A20

A19

A11

A15

I/O0

I/O2

I/O5

I/O7

A16

I/O8

I/O10

I/O12

I/O14

I/O9

I/O11

VCC

I/O13

I/015

VSS

I/O1

I/O3

I/O4

I/O6

VSS

AT49SV322D(T)

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3. Block Diagram

AT49SV322D(T)

I/O0 - I/O15

A0 - A20

INPUT

BUFFER

ADDRESS

LATCH

Y-DECODER

X-DECODER

OUTPUT BUFFER

OUTPUT

MULTIPLEXER

IDENTIFIER

STAT US

DATA

COMPARATOR

Y-GATING

MAIN

MEMORY

INPUT

BUFFER

DATA

COMMAND REGISTER

WRITE STATE

MACHINE

PROGRAM/ERASE VOLTAGE SWITCH

CE WE OE RESET

RDY/BUSY

VPP

VCC GND

4. Device Operation

4.1 Command Sequences

When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the

“Command Definition Table” on page 12 (I/O8 - I/O15 are don’t care inputs for the command

codes). The command sequences are written by applying a low pulse on the WE with CE CE

or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences.

4.2 Read

The AT49SV322D(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE dual-line control gives designers flexibility in preventing bus contention.

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or CE input

or WE low (respectively) and OE high. The address is latched on the falling edge of

or OE is high. This

4.3 Reset

4.4 Erase

4.4.1 Chip Erase

4.4.2 Sector Erase

A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET mode, depending upon the state of the control inputs.

Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.

The entire device can be erased at one time by using the six-word chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode.

As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE command is latched on the rising edge of WE WE

of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is t down feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating immediately.

pin, the device returns to the read or standby

edge of the sixth cycle while the 30H data input

. The sector erase starts after the rising edge of

. When the sector programming lock-

SEC

input halts

4.5 Word Programming

Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t time. The Data program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or program operation was performed successfully.

AT49SV322D(T)

cycle

Polling feature or the Toggle Bit feature may be used to indicate the end of a

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4.6 VPP Pin

The circuitry of the AT49SV322D(T) is designed so that the device cannot be programmed or erased if the V and erase operations can be performed. The VPP pin cannot be left floating.

4.7 Program/Erase Status

The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49SV322D(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register command as shown in the “Command Definition

Table” on page 12, the value of the configuration register can be changed. Voltages applied to

the RESET tion register will affect the operation of the I/O7 status bit as described below.

AT49SV322D(T)

voltage is less that 0.4V. When VPP is at 1.65V or above, normal program

pin will not alter the value of the configuration register. The value of the configura-

4.7.1 Data

4.7.2 Toggle Bit

Polling

The AT49SV322D(T) features Data configuration register is set to a “00”, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data may begin at any time during the program cycle. Please see “Status Bit Table” on page 11 for more details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked.

The Data bit as shown in the algorithm in Figures 4-1 and 4-2 on page 9.

In addition to Data end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on

page 11 for more details.

Polling status bit must be used in conjunction with the erase/program and VPP status

Polling the AT49SV322D(T) provides another method for determining the

Polling to indicate the end of a program cycle. If the status

Polling

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The toggle bit status bit should be used in conjunction with the erase/program and V bit as shown in the algorithm in Figures 4-3 and 4-4 on page 10.

status

4.7.3 Erase/Program Status Bit

The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to verify that an erase or a word program operation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or program operation is still in progress. Please see “Status Bit Table” on page 11 for more details.

4.7.4 VPP Status Bit

The AT49SV322D(T) provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”. Once the V command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the V see “Status Bit Table” on page 11 for more details.

4.8 Sector Lockdown

Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector’s usage as a write-protected region is optional to the user.

status bit has been set to a “1”, the system must write the Product ID Exit

status bit will output a “0”. Please

At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed.

4.8.1 Sector Lockdown Detection

A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see “Software Product Identification

Entry/Exit” sections on page 25), a read from address location 00002H within a sector will

show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.

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4.8.2 Sector Lockdown Override

The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.

4.9 Erase Suspend/Erase Resume

The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same.

4.10 Program Suspend/Program Resume

The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 µs to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same.

AT49SV322D(T)

4.11 Product Identification

The product identification mode identifies the device and manufacturer as Atmel®. It is accessed using a software operation.

For details, see “Operating Modes” on page 18 or “Software Product Identification Entry/Exit” sections on page 25.

4.12 128-bit Protection Register

The AT49SV322D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the “Command Definition

Table” . Data bit D1 must be zero during the fourth bus cycle. All other data bits during the

fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero,

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block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protec-

tion Register Addressing Table” on page 13 for the address locations in the protection register.

To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation.

4.13 RDY/BUSY

An open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY

page 11 for more details.

4.14 Common Flash Interface (CFI)

CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in “Common Flash Interface Definition Table”

on page 26. To exit the CFI Query mode, the product ID exit command must be given.

is actively pulled low during the internal program and

line. Please see “Status Bit Table” on

4.15 Hardware Data Protection

The Hardware Data Protection feature protects against inadvertent programs to the AT49SV322D(T) in the following ways: (a) V gram function is inhibited. (b) V the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE V

is less than V

4.16 Input Levels

While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE

, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of

the device. The I/O lines can only be driven from 0 to V

sense: if VCC is below 1.65V (typical), the pro-

power-on delay: once VCC has reached the VCC sense level,

low, CE high or WE high inhibits program cycles. (d) Program inhibit:

ILPP

+ 0.6V.

AT49SV322D(T)

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Figure 4-1. Data Polling Algorithm

(Configuration Register = 00)

Figure 4-2. Data Polling Algorithm

(Configuration Register = 01)

Read I/O7 - I/O0

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

START

Addr = VA

YES

Addr = VA

YES

Read I/O7 - I/O0

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

START

Addr = VA

YES

Addr = VA

YES

I/O7 = Data?

YES

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Notes: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5.

Program/Erase

Operation

Successful,

Device in

Read Mode

I/O7 = Data?

YES

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Notes: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5.

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

AT49SV322D(T)

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AT49SV322D(T)

Figure 4-3. Toggle Bit Algorithm

(Configuration Register = 00)

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

YES

I/O3, I/O5 = 1?

Figure 4-4. Toggle Bit Algorithm

(Configuration Register = 01)

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

YES

I/O3, I/O5 = 1?

YES

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

YES

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Note: 1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”.

Program/Erase

Operation

Successful, Device

in Read Mode

YES

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

YES

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Note: 1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”.

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

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