ATMEL AT49BV163DT User Manual
BDTIC www.BDTIC.com/ATMEL
Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Fast Read Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 10 µs
• Fast Sector Erase Time – 100 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending
Programming of Any Other Byte/Word
• Low-power Operation
–10 mA Active
– 15 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
• Green (Pb/Halide-free) Packaging
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV163D
AT49BV163DT
1. Description
The AT49BV163D(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for
erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device has CE
device can be read or reprogrammed using a single power supply, making it ideally
suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the
capability to protect the data in any sector (see “Sector Lockdown” on page 5).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory. The end of a program or an erase cycle is detected by the
READY/BUSY
A six-byte command (Enter Single Pulse Program Mode) sequence to remove
the requirement of entering the three-byte program sequence is offered to further
improve programming time. After entering the six-byte code, only single pulses on the
write control lines are required for writing into the device. This mode (Single
Pulse Byte/Word Program) is exited by powering down the device, or by pulsing
the RESET
pin, Data Polling or by the toggle bit.
pin low for a minimum of 500 ns and then bringing it back to VCC. Erase,
and OE control signals to avoid any bus contention. This
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Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this
mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external
programming code.
The BYTE
pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE
and controlled by CE
If the BYTE
pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 I/O7 are active and controlled by CE
the I/O15 pin is used as an input for the LSB (A-1) address function.
2. Pin Configurations
Pin Name Function
A0 - A19 Addresses
CE
OE
WE
RESET Reset
RDY/BUSY
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (A-1)
Chip Enable
Output Enable
Write Enable
READY/BUSY Output
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
pin is set at logic “1”, the device is in word configuration, I/O0 - I/O15 are active
and OE.
and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and
BYTE
Selects Byte or Word Mode
NC No Connect
2.1 48-lead TSOP (Type 1) Top View
A15
A14
A13
A12
A11
A10
A19
RESET
RDY/BUSY
A18
A17
1
2
3
4
5
6
7
A9
8
A8
9
10
NC
11
WE
12
13
NC
14
NC
15
16
17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
48
A16
47
BYTE
46
GND
45
I/O15/A-1
44
I/O7
43
I/O14
42
I/O6
41
I/O13
40
I/O5
I/O12
39
I/O4
38
VCC
37
36
I/O11
35
I/O3
34
I/O10
33
I/O2
32
I/O9
31
I/O1
30
I/O8
29
I/O0
28
OE
27
GND
26
CE
25
A0
2.2 48-ball CBGA Top View (Ball Down)
2 3 456
1
A
A3
A7
RDY/BUSY
WE
A9
A13
B
A4
A17
NC
RST
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
NC
A19
A11
A15
E
A0
I/O0
I/O2
I/O5
I/O7
A16
F
CE
I/O8
I/O10
I/O12
I/O14
BYTE
G
OE
I/O9
I/O11
VCC
I/O13
I/015/A-1
H
VSS
I/O1
I/O3
I/O4
I/O6
VSS
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AT49BV163D(T)
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3. Block Diagram
AT49BV163D(T)
I/O0 - I/O15/A-1
4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be reset to the read or standby mode, depending
upon the state of the control line inputs. In order to perform other device functions, a series of
command sequences are entered into the device. The command sequences are shown in the
“Command Definition Table” on page 11 (I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying a low pulse on the WE
with CE
or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences
are not affected by entering the command sequences.
or WE low (respectively) and OE high. The address is latched on the falling edge of CE
A0 - A19
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
OUTPUT
BUFFER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y-GATING
MAIN
MEMORY
INPUT
BUFFER
DATA
REGISTER
COMMAND
REGISTER
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
BYTE
RDY/BUSY
VCC
GND
or CE input
4.2 Read
4.3 Reset
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The AT49BV163D(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the
out-puts. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-
line control gives designers flexibility in preventing bus contention.
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
input halts the
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET
pin, the device returns to the read or standby mode,
depending upon the state of the control inputs.
3
4.4 Erase
4.4.1 Chip Erase
4.4.2 Sector Erase
Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is
a logical “1”. The entire device can be erased by using the Chip Erase command or individual
sectors can be erased by using the Sector Erase command.
The entire device can be erased at one time by using the six-byte chip erase software code.
After the chip erase has been initiated, the device will internally time the erase operation so that
no external clocks are required. The maximum time to erase the chip is t
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that
has been locked out; it will erase only the unprotected sectors. After the chip erase, the device
will return to the read or standby mode.
As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that
can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector
address is latched on the falling WE
latched on the rising edge of WE
cycle. The erase operation is internally controlled; it will automatically time to completion. The
maximum time to erase a sector is t
enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a
sector that has been protected will result in the operation terminating immediately.
edge of the sixth cycle while the 30H data input command is
. The sector erase starts after the rising edge of WE of the sixth
. When the sector programming lockdown feature is not
SEC
EC
.
4.5 Byte/Word Programming
Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a
word-by-word basis. Programming is accomplished via the internal device command register
and is a four-bus cycle operation. The device will automatically generate the required internal
program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If a
hardware reset happens during programming, the data at the location being programmed will be
corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t
Polling feature or the Toggle Bit feature may be used to indicate the end of a program
Data
cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or
program operation was performed successfully.
4.6 Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O5, I/O6 and I/O7. The “Status Bit Table” on page 10 and the following four sections describe
the function of these bits. To provide greater flexibility for system designers, the
AT49BV163D(T) contains a programmable configuration register. The configuration register
allows the user to specify the status bit operation. The configuration register can be set to one of
two different values, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration
register is set to a “01”, a Product ID Exit command must be given after a successful program or
erase operation before the part will return to the read mode. It is important to note that whether
the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default
value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register command as shown in the “Command Definition Table” on page 11, the value
cycle time. The
BP
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AT49BV163D(T)
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AT49BV163D(T)
of the configuration register can be changed. Voltages applied to the RESET pin will not alter the
value of the configuration register. The value of the configuration register will affect the operation
of the I/O7 status bit as described below.
4.6.1 DATA
4.6.2 Toggle Bit
Polling
The AT49BV163D(T) features Data
configuration register is set to a “00”, during a program cycle an attempted read of the last
byte/word loaded will result in the complement of the loaded data on I/O7. Once the program
cycle has been completed, true data is valid on all outputs and the next cycle may begin. During
a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data
begin at any time during the program cycle. Please see “Status Bit Table” on page 10 for more
details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data
shown in the algorithm in Figures 4-1 and and 4-2 on page 8.
In addition to Data
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the memory will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle. Please see “Status Bit Table” on page 10 for more
details.
Polling status bit must be used in conjunction with the erase/program status bit as
Polling the AT49BV163D(T) provides another method for determining the end
Polling to indicate the end of a program cycle. If the status
Polling may
The toggle bit status bit should be used in conjunction with the erase/program status bit as
shown in the algorithm in Figures 4-3 and and 4-4 on page 9.
4.6.3 Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation
has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable
to verify that an erase or a byte/word program operation has been successfully performed. If a
program (Sector Erase) command is issued to a protected sector, the protected sector will not
be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be
set high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 10 for more details.
4.7 Sector Lockdown
Each sector has a programming lockdown feature. This feature prevents programming of data in
the designated sectors once the feature has been enabled. These sectors can contain secure
code that is used to bring up the system. Enabling the lockdown feature will allow the boot code
to stay in the device while data in the rest of the device is updated. This feature does not have to
be activated; any sector’s usage as a write-protected region is optional to the user.
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5
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the
six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down,
the contents of the sector is read-only and cannot be erased or programmed.
4.7.1 Sector Lockdown Detection
A software method is available to determine if programming of a sector is locked down. When
the device is in the software product identification mode (see “Software Product Identification
Entry/Exit” sections on page 21), a read from address location 00002H within a sector will show
if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the
sector cannot be programmed. The software product identification exit code should be used to
return to standard operation.
4.7.2 Sector Lockdown Override
The only way to unlock a sector that is locked down is through reset or power-up cycles. After
power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.
4.8 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector or chip erase operation
and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase
operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase
Suspend command. During a sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write the Erase Resume command. The
Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same.
4.9 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different byte/word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 µs to suspend the programming operation.
After the programming operation has been suspended, the system can then read data from any
other byte/word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the
programming operation, the system must write the Program Resume command. The program
suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume
and program resume are the same.
4.10 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It is accessed
using a software operation.
For details, see “Operating Modes” on page 15 or “Software Product Identification Entry/Exit”
sections on page 21.
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AT49BV163D(T)
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4.11 128-bit Protection Register
The AT49BV163D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can be
locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 11. To lock out block B, the four-bus cycle
Lock Protection Register command must be used as shown in the “Command Definition Table” .
Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus
cycle are don’t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is
locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register
Addressing Table” on page 12 for the address locations in the protection register. To read the
protection register, the Product ID Entry command is given followed by a normal read operation
from an address within the protection register. After determining whether block B is protected or
not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation.
4.12 RDY/BUSY
An open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY
cycles and is released at the completion of the cycle. The open-drain connection allows for ORtying of several devices to the same RDY/BUSY
for more details.
AT49BV163D(T)
is actively pulled low during the internal program and erase
line. Please see “Status Bit Table” on page 10
4.13 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters, and functions supported by the device. CFI is used to allow the system
to learn how to interface to the flash device most optimally. The two primary benefits of using
CFI are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in “Common Flash Interface Definition Table” on page 22. To exit
the CFI Query mode, the product ID exit command must be given.
4.14 Hardware Data Protection
The Hardware Data Protection feature protects against inadvertent programs to the
AT49BV163D(T) in the following ways: (a) V
function is inhibited. (b) Program inhibit: holding any one of OE
program cycles.
4.15 Input Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
CE
device. The I/O lines can only be driven from 0 to V
sense: if VCC is below 1.8V (typical), the program
CC
low, CE high or WE high inhibits
+ 0.6V.
CC
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7
Figure 4-1. Data Polling Algorithm
(Configuration Register = 00)
Figure 4-2. Data Polling Algorithm
(Configuration Register = 01)
Read I/O7 - I/O0
I/O7 = Data?
NO
Read I/O7 - I/O0
START
Addr = VA
NO
I/O5 = 1?
YES
Addr = VA
YES
Read I/O7 - I/O0
I/O7 = Data?
NO
Read I/O7 - I/O0
START
Addr = VA
NO
I/O5 = 1?
YES
Addr = VA
YES
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
Program/Erase
Operation
Successful,
Device in
Read Mode
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
8
AT49BV163D(T)
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