ATMEL AT49BV1614T-12TI, AT49BV1614T-12TC, AT49BV1614T-12CI, AT49BV1614T-12CC, AT49BV1614-90TI Datasheet

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Features

•

2.7V to 3.6V Read/Write

•

Access Time - 90 ns

•

Sector Erase Architecture

– Thirty 32K word (64K byte) Sectors with Individual Write Lockout – Eight 4K word (8K byte) Sectors with Individual Write Lockout – Two 16K word (32K byte) Sectors with Individual Write Lockout

•

Fast Word Program Time - 20

µµµµ

•

Fast Sector Erase Time - 200 ms

•

Dual Plane Organization, Permitting Concurrent Read while Program/E rase

– Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors – Memory Plane B: Twenty-Four 32K Word Sectors

•

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

•

Low Power Operation

– 25 mA Active –10

µµµµ

A Standby

•

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

•

Optional VPP Pin for Fast Programming

•

RESET Input for Device Initialization

•

Sector Program Unlock Command

•

TSOP, CBGA, and

µµµµ

BGA Package Options

•

Top or Bottom Boot Block Configuration Available

Description

The AT49BV16X4(T) is 2.7 to 3.6 volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 blocks for er ase ope ratio ns. The device is o ffered in 48-p in TSOP and 48 -ball

BGA packages. The device has CE

, and OE control signals to avoid any bus contention. This de vic e c an be read or repro gra mmed using a s ingle 2. 7V p ower s uppl y, making it ideally suited for in-system programming.

Rev. 0925B–05/98

AT49BV1604

16-Megabit (1M x 16/2M x 8) 3-volt Only Flash Memory

AT49BV1604 AT49BV1604T AT49BV1614 AT49BV1614T Adv ance Information

AT49BV16X4(T)

Pin Configurations

Pin Name Function

A0 - A19 Addresses CE

Chip Enable

Output Enable

Write Enable

RESET

Reset

RDY/BUSY

READY/BUSY Output

Optional Pow er Supply for Faster Program/Erase Operations

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

BYTE

Selects Byte or Word Mode NC No Connect V

CCQ

Output Power Supply DC Don’t Connect

(continued)

AT49BV16X4(T)

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any se ctor. Once the d ata protection for a given sector is enabled, the data in that sector cannot be changed usin g input levels between ground and V

The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by no t requiri ng the syst em to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it

contains an Erase Suspend feature. This feature will put the Erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memo ry plane. There is no rea son to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an Erase cycle is det ect e d by th e Rea dy / Bu sy

pin, Data polling, or by

the toggle bit. A V

pin is provided to improve program/erase times at lower supply vo ltages. Thi s pin does not ne ed to be utilized. If it is not used the pin should be connected to ground or V

. To take advantage of faster pr ogramming, the pi n should supply 5.0 volts during program and erase operations.

TSOP Top View

Type 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A15 A14 A13 A12 A11 A10

A8 NC NC

RESET

VPP

A19 A18 A17

A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0

CBGA Top View

1 2 3 4 5 6

GFEDCB

VSS

I/O1

I/O3

I/O4

I/O6

VSS

I/O9

I/O11

VCC

I/O13

I/O15

/A-1

I/O8

I/O10

I/O12

I/O14

BYTE

I/O0

I/O2

I/O5

I/O7

A16

A19

A11

A15

A18

A10

A14

A17

RESET

A12

RDY/BUSY

A13

BGA Top View (Ball Down)

B C D

234567

A13

A14

A15

A16

VCCQ

GND

A11

A10

A12

I/O14

I/O15

I/O7

I/O5

I/O6

I/O13

VPP

RST

I/O11

I/O12

I/O4

A18

I/O2

I/O3

VCC

A19

A17

I/O8

I/O9

I/O10

I/O0

I/O1

GND

TSOP T op View

Type 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A15 A14 A13 A12 A11 A10

A9 A8

A19

RESET

VPP

RDY/BUSY

A18 A17

A7 A6 A5 A4 A3 A2 A1

A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0

AT49BV1604(T)

AT49BV1614(T)

AT49BV16X4(T)

A six byte command (bypass unlock) sequence to remove the requirement of entering the three byte prog ram sequence is offered to further improve programming time. After entering the six byte code, only si ngle pulses on the write control lines are required for writing into the device. This mode (single pulse byte/word program) is exited by powering down the device, or by pulsing the RESET

low and then bringing it back to V

. Erase and Erase Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six byte code reside

in the software of the final produ ct but only exist in external programming code.

The BYTE

pin controls whethe r the device data I/O pins

operate in the byte or word configuration. If the BYTE

pin is set at logic “1”, the device is in word configuration, I/O0I/O15 are active and controlled by CE

and OE.

If the BYTE

pin is set at logic “0”, the devi ce is in byte configuration, and only data I/O pins I/O0-I/O7 are active and controlled by CE

and OE. The data I/O pins I/O8-I/O14 are tri-stated, and the I/O1 5 pin is us ed a s an inp ut for the LSB (A-1) address function.

Block Diagram

Device Operation

READ:

The AT49BV16X4(T) is accessed like an EPROM.

When CE

and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE

or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command

sequences are entered into the device. The command sequences are shown in the Com mand Definition s table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE

or CE input with CE or WE low (respec-

tively) and OE

high. The address is latched on the falling

edge of CE

or WE, whichever occurs last. The data is

latched by the first rising edge of CE

or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences.

IDENTIFIER

STATUS

DATA

COMPARATOR

OUTPUT

MULTIPLEXER

OUTPUT BUFFER

INPUT

BUFFER

COMMAND REGISTER

DATA

Y-GATING

WRITE STATE

MACHINE

PROGRAM/ERASE VOLTAGE SWITCH

CE WE OE RESET BYTE

RDY/BUSY

VPP

VCC GND

Y-DECODER

X-DECODER

INPUT

BUFFER

ADDRESS

LATCH

I/O0 - I/O15/A-1

A0 - A19

PLANE B

SECTORS

PLANE A SECTORS

AT49BV16X4(T)

RESET:

A RESET

input pin is p rov ided to e ase some sy s-

tem application s. When RE SET

is at a logic high level, the device is in its standa rd oper at ing mod e. A low l evel on th e RESET

input halts the prese nt device oper ation and puts the outputs of the de vice in a hi gh impedan ce stat e. When a high level is reasse rted on the RES ET

pin, the device returns to the Read or Standby mod e, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET

pin any sector can be reprogrammed even if the sector lockout feature has been enabled (see Sector Programming Lockout Override section).

ERASURE:

Before a byte/word ca n be reprogramm ed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands.

CHIP ERASE:

The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been in itiate d, the devi ce wil l internal ly tim e the erase operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockout has been enabled, the Chip Erase will not erase the data in the secto r th at ha s be en l oc ked; it wi ll erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into forty sectors (SA0 - SA39) that can be individually erased . The Secto r Erase comm and is a six bus cycle operation. The sector ad dress is latched on the falling WE

edge of the sixth cy cle whil e the 30H d ata inpu t

command is latched on the rising edge of WE

. The sector

erase starts after the rising edge of WE

of the sixth cycle. The erase operation is i nterna ll y con troll ed ; it wi ll aut oma tically time to completion. The maximum time to erase a section is t

SEC

. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). Once a sector has been protected, data in the protected s ectors cannot be changed unles s the RESET pin is taken to 12V ± 0. 5V. An attempt to erase a sector that has been pr otected wi ll result in the operation terminating in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a word-by- word ba si s. Pr o gr amm ing i s ac co mpl is he d via the intern al device command r egister and is a 4-b us cycle operation. The devic e will automati cally gener ate the required internal program pulses.

Any commands written to the c hip during the em bedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after

the specified t

cycle time. The DATA polling feature or the toggle bit feature may be used to indicate the end of a program cycle.

SECTOR PROGRAMMING LOCKOUT:

Each sector has a programming lockout featur e. This feature prevents programming of data in the design ated sectors o nce the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockout feature will all ow the boot code to stay i n the device while data in the rest of the device is upd ated. Thi s featur e does not have to be activated; any sector’s usage as a write protected region is optional to the user.

Once the feature is enabled, the data in the protected sectors can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the remaining sectors can still be changed through the regular programming method. To activate the lo ck ou t fea tur e, a seri es of s ix pr ogram commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

SECTOR PROGRAMMING LOCKOUT OVERRIDE:

The user can override the sector programming lockout by taking the RESET

pin to 12V ± 0.5V. By doing this prote cted da ta can be altered through a chip erase, sector era se or byte/word program ming. When the RESET

pin is brought back to TTL levels th e secto r programm ing lock out featu re is again active.

ERASE SUSPEND/ERASE RESUME:

The erase suspen d command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual plane architecture, there is no need to use the erase suspend feature while erasin g a sec tor when y ou want to r ead data from a sector in the other plane. After the erase suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane which contains the suspended sec tor enters th e erase-s uspend-r ead mode. The system can then read data or program da ta to any other sector within the device. An address is not required during the erase suspend comm and. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the erase resume command. The erase resume command is a one bus cycl e co mma nd, whi c h d oes req ui re the p lan e address (determined by A18 and A19). The device also supports an erase suspend during a complete chip erase. While the chip erase is suspen ded, the use r can read from any sector within the me mory that is protec ted. The command sequence for a ch ip erase suspen d and a sector erase suspend are the same.

PRODUCT IDENTIFICATION:

The product identification

mode identifies the device and manufacturer as Atmel. It

AT49BV16X4(T)

may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see O peratin g Modes (for har dware operatio n) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING:

The AT49BV16X4(T) features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and th e next cyc le may be gin. Du ring a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA

polling may begi n at any ti me during the program

cycle. Please see “Status Bit Table” for more details.

TOGGLE BIT:

In addition to DATA

polling the AT49BV16X4(T) provides another method for determining the end of a program or erase cycle. Du ring a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

An additional to ggle bit is available on I/O2 whi ch can be used in conjunction with the toggle bit which is available on I/O6. While a sector is erase suspe nded, a read or a program operation fr om th e su sp ended sector will re sul t in th e

I/O2 bit togglin g. Please see s tatus bit table fo r more details.

RDY/BUSY

An open drain READY/BUSY

output pin provides another method of detecting the end of a progr am or erase operation. RDY/BUSY

is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY

line.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs to the AT49BV16X4(T) in the following ways: (a) V

sense: if

is below 1.8V (typical), the program function is inhib-

ited. (b) V

power on delay: once VCC has reached the

sense level, the device will automatically time out 10 ms (typical) before prog ramming. (c) Program inhibi t: holding any one of OE

low, CE high or WE high inhib its program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program

cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, the ad dress inpu ts and cont rol inputs (OE

, and WE) may be dr iven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V

+ 0.6V.

OUTPUT LEVELS:

Output High Levels (V

) are equal to

CCQ

- 0.2V (n ot VCC). For 2.7V - 3.6V output levels, V

CCQ

must be tied to VCC. For 1.8V - 2.2V output leve ls, V

CCQ

must be regulated to 2.0V ± 10% while VCC must be regulated to 2.7V - 3.0V (for minimum power).

AT49BV16X4(T)

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next four pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET

pin is taken to

12V ± 0.5V.

5. PA is the plane address (A19 - A18).

Command Definition in (Hex)

(1)

Command Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(3)(4)

Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

Bypass Unlock 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0 Single Pulse

Byte/Word Program

1 Addr D

Sector Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(3)(4)

40 Erase Suspend 1 xxxx B0 Erase Resume 1 PA

(5)

30 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit

(2)

3 5555 AA 2AAA 55 5555 F0

Product ID Exit

(2)

1 xxxx F0

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice. Th is is a s tress rating only an d functional oper ati on of the devi ce at t hes e o r any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect dev ice reliability .

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

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