BDTIC www.BDTIC.com/ATMEL
Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 10 µs
• Fast Sector Erase Time – 100 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 10 mA Active
– 15 µA Standby
• VPP Pin for Write Protection and Accelerated Program Operation
• WP Pin for Sector Protection
• RESET Input for Device Initialization
• Flexible Sector Protection
• TSOP Package
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
• Green (Pb/Halide-free) Packaging
16-megabit
(1M x 16)
3-volt Only
Flash Memory
AT49BV160D
AT49BV160DT
1. Description
The AT49BV160D(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each. The memory is divided into 39 sectors for erase operations.
The device is offered in a 48-lead TSOP package. The device has CE
signals to avoid any bus contention. This device can be read or reprogrammed using
a single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place
the device in other operation modes such as program and erase. The device has
the capability to protect the data in any sector (see “Flexible Sector Protection” on
page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory.
The VPP pin provides data protection. When the V
and erase functions are inhibited. When V
and erase operations can be performed. With V
Program Command) operation is accelerated.
PP
input is below 0.4V, the program
PP
is at 1.65V or above, normal program
at 10.0V, the program (Dual-word
PP
and OE control
3591C–FLASH–6/06
2. Pin Configurations
Pin Name Function
A0 - A19 Addresses
CE
OE
WE
RESET
VPP Write Protection
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
VCCQ Output Power Supply
WP
2.1 TSOP Top View (Type 1)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
2
AT49BV160D(T)
3591C–FLASH–6/06
3. Block Diagram
AT49BV160D(T)
I/O0 - I/O15
A0 - A19
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
OUTPUT
BUFFER
OUTPUT
IDENTIFIER
MULTIPLEXER
COMPARATOR
MEMORY
REGISTER
STATUS
REGISTER
DATA
Y-GATING
MAIN
INPUT
BUFFER
DATA
REGISTER
COMMAND
REGISTER
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
WP
VPP
VCC
GND
4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be in the read mode. In order to perform other device
functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition Table” on page 15 (I/O8 - I/O15 are don’t care
inputs for the command codes). The command sequences are written by applying a low pulse
on the WE
latched by the first rising edge of CE
The address locations used in the command sequences are not affected by entering the command sequences.
4.2 Read
When the AT49BV160D(T) is in the read mode, with CE and OE low and WE high, the data
stored at the memory location determined by the address pins are asserted on the outputs. The
outputs are put in the high impedance state whenever CE
gives designers flexibility in preventing bus contention.
3591C–FLASH–6/06
or CE input with CE or WE low (respectively) and OE high. The address and data are
or WE. Standard microprocessor write timings are used.
or OE is high. This dual-line control
3
4.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET
the state of the control inputs.
4.4 Erase
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The individual sectors can be erased by using the Sector Erase command.
4.4.1 Sector Erase
The device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector
Erase command is a two-bus cycle operation. The sector address and the D0H Data Input command are latched on the rising edge of WE
of the second cycle provided the given sector has not been protected. The erase operation is
internally controlled; it will automatically time to completion. The maximum time to erase a sector
is t
SEC
ing immediately.
4.5 Word Programming
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus cycle
operation. The device will automatically generate the required internal program pulses.
input halts the
pin, the device returns to the read mode, depending upon
. The sector erase starts after the rising edge of WE
. An attempt to erase a sector that has been protected will result in the operation terminat-
4.6 VPP Pin
Any commands written to the chip during the embedded programming cycle will be ignored. If a
hardware reset happens during programming, the data at the location being programmed will be
corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t
program status bit is a “1”, the device was not able to verify that the program operation was performed successfully. The status register indicates the programming status. While the program
sequence executes, status bit I/O7 is “0”. While programming, the only valid commands are
Read Status Register, Program Suspend and Program Resume.
The circuitry of the AT49BV160D(T) is designed so that the device cannot be programmed or
erased if the V
erase operations can be performed. The VPP pin cannot be left floating.
voltage is less that 0.4V. When VPP is at 1.65V or above, normal program and
PP
cycle time. If the
BP
4
AT49BV160D(T)
3591C–FLASH–6/06
4.7 Read Status Register
The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the
status register until another command is issued. To return to reading from the memory, issue a
Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
AT49BV160D(T)
The contents of the status register [SR7:SR0] are latched on the falling edge of OE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE
or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see Table 4-1).
Table 4-1. Status Register Bit Definition
WSMS ESS ES PS VPPS PSS SLS R
76543210
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
SR4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
When this bit is set to “1”, WSM has attempted but failed to
program a word
The V
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if V
before the operation is verified by the WSM.
status bit does not provide continuous indication of VPP
PP
has not been switched on. The VPP is also checked
PP
or CE
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR1 = SECTOR LOCK STATUS (SLS)
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Note: 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
3591C–FLASH–6/06
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
This bit is reserved for future use and should be masked out
when polling the status register.
5
4.7.1 Clear Status Register
The WSM can set status register bits 1 through 7 and can clear bits 2, 6 and 7; but, the WSM
cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register command. By allowing
the system software to control the resetting of these bits, several operations may be performed
(such as cumulatively programming several addresses or erasing multiple sectors in sequence)
before reading the status register to determine if an error occurred during those operations. The
status register should be cleared before beginning another operation. The Read command must
be issued before data can be read from the memory array. The status register can also be
cleared by resetting the device.
4.8 Flexible Sector Protection
The AT49BV160D(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
4.8.1 Softlock and Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
4.8.2 Hardlock and Write Protect
The Hardlock sector protection mode operates in conjunction with the Write Protect (WP
The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock Software command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP
unlocked and the contents of the sector is read-only.
• When the WP
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
) pin.
pin is low and the Hardlock protection mode is enabled, the sector cannot be
pin is high, the Hardlock protection mode is overridden and the sector can be
6
AT49BV160D(T)
3591C–FLASH–6/06
Table 4-2. Hardlock and Softlock Protection Configurations in Conjunction with WP
Erase/
Hard-
V
PP
/5V 0 0 0 Yes No sector is locked
V
CC
/5V 0 0 1 No
V
CC
WP
lock
Soft-
lock
Prog
Allowed? Comments
Sector is Softlocked. The Unlock command can
unlock the sector.
AT49BV160D(T)
/5V 0 1 1 No
V
CC
Hardlock protection mode is enabled. The sector
cannot be unlocked.
VCC/5V 1 0 0 Yes No sector is locked.
VCC/5V 1 0 1 No
V
/5V 1 1 0 Yes
CC
/5V 1 1 1 No
V
CC
V
IL
xxx No
Sector is Softlocked. The Unlock command can
unlock the sector.
Hardlock protection mode is overridden and the
sector is not locked.
Hardlock protection mode is overridden and the
sector can be unlocked via the Unlock command.
Erase and Program Operations cannot be
performed.
Figure 4-1. Sector Locking State Diagram
UNLOCKED LOCKED
WP = V
60h/
[000] [001]
=0
IL
D0h
6
0
h
/
2
60h/01h
F
h
60h/
2Fh
[011]
Power-Up/Reset
Default
Hardlocked
WP = V
60h/
2Fh
60h/
01h
60h/
01h
[110]
=1
IH
[100]
60h/D0h
60h/
D0h
Hardlocked is disabled by
[111]
60h/
2Fh
[101]
60h/D0h = Unlock Comm and
60h/01h = Softlock Comma nd
60h/2Fh = Hardlock Command
WP = V
Power-Up/Reset
Default
IH
Note: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP
and the two bits of the sector-lock status D[1:0].
3591C–FLASH–6/06
7
4.8.3 Sector Protection Detection
A software method is available to determine if the sector protection Softlock or Hardlock features
are enabled. When the device is in the software product identification mode, a read from the
I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked.
Table 4-3. Sector Protection Status
I/O1 I/O0 Sector Protection Status
0 0 Sector Not Locked
0 1 Softlock Enabled
1 0 Hardlock Enabled
1 1 Both Hardlock and Softlock Enabled
4.9 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation.
After the erase operation has been suspended, the system can then read data or program data
to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector
erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The only valid commands while erase is suspended are
Read Status Register, Product ID Entry, CFI Query, Program, Program Resume, Erase
Resume, Sector Softlock/Hardlock, Sector Unlock.
4.10 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read data from any other
word within the device. An address is not required during the program suspend operation. To
resume the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
erase suspend and program suspend are the same and the command sequence for the erase
resume and program resume are the same. The only other valid commands while program is
suspended are Read Status Register, Product ID Entry, CFI Query and Program Resume.
4.11 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed a software operation. For details, see “Operating Modes” on page 19.
8
AT49BV160D(T)
3591C–FLASH–6/06
4.12 128-bit Protection Register
The AT49BV160D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit sectors. The two sectors are
designated as sector A and sector B. The data in sector A is non-changeable and is programmed at the factory with a unique number. The data in sector B is programmed by the user
and can be locked out such that data in the sector cannot be reprogrammed. To program sector
B in the protection register, the two-bus cycle Program Protection Register command must be
used as shown in the “Command Definition Table” on page 15. To lock out sector B, the two-bus
cycle Lock Protection Register command must be used as shown in the “Command Definition
Table” . Data bit D1 must be zero during the second bus cycle. All other data bits during the sec-
ond bus cycle are don’t cares. To determine whether sector B is locked out, use the status of
sector B protection command. If data bit D1 is zero, sector B is locked. If data bit D1 is one, sector B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 16
for the address locations in the protection register. To read the protection register, the Product
ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether sector B is protected or not, or reading the protection
register, the Read command must be given to return to the read mode.
4.13 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters and functions supported by the device. CFI is used to allow the system to
learn how to interface to the flash device most optimally. The two primary benefits of using CFI
are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to any address. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in “Common Flash Interface Definition Table” on page 24. To return
to the read mode, issue the Read command.
AT49BV160D(T)
4.14 Hardware Data Protection
The Hardware Data Protection feature protects against inadvertent programs to the
AT49BV160D(T) in the following ways: (a) V
function is inhibited. (b) Program inhibit: holding any one of OE
program cycles. (c) Program inhibit: V
4.15 Input Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,
CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
device. The I/O lines can only be driven from 0 to V
4.16 Output Levels
For the AT49BV160D(T), output high levels (VOH) are equal to V
2.65V -3.6V output levels, V
3591C–FLASH–6/06
is less than V
PP
must be tied to VCC.
CCQ
sense: if VCC is below 1.8V (typical), the program
CC
low, CE high or WE high inhibits
.
ILPP
+ 0.6V.
CCQ
- 0.1V (not VCC). For
CCQ
9
5. Word Program Flowchart
Start
6. Word Program Procedure
Bus
Operation Command Comments
Wri te 40,
Any Address
Wr ite Data,
Wor d Add r es s
Read-Status
Regi ster
SR7 =
1
Full Status
Check
(If Desi red)
Progr am
Complete
(Setu p)
(Confirm)
0
No
Suspend?
Program
Suspend
Loop
Ye s
Write
Program
Setup
Write Data
Data = 40
Addr = Any Address
Data = Data to program
Addr = Location to program
Status register data: Toggle CE
Read None
or
to update status register
OE
Check SR7
Idle None
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent Word Program operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to set to the Read state.
7. Full Status Check Flowchart
Read Status
Regi ster
SR3 =
0
SR4 =
0
SR1 =
0
Program
Successful
1 V
1
1
Range
PP
Error
Program
Error
Device
Protect Error
8. Full Status Check Procedure
Bus
Operation Command Comments
Idle None
Idle None
Idle None
SR3 MUST be cleared before the Write State Machine allows
further program attempts.
If an error is detected, clear the status register before
continuing operations – only the Clear Status Register
command clears the status register error bits.
Check SR3:
1 = V
Error
PP
Check SR4:
1 = Data Program Error
Check SR1:
1 = Sector locked; operation
aborted
10
AT49BV160D(T)
3591C–FLASH–6/06
AT49BV160D(T)
9. Program Suspend/Resume Flowchart
Start
Wr i te B0
Any Address
Wr i te 70
Any Address
Read Status
Regi ster
SR7 =
1
SR2 =
1
Wr i te FF
Read
Data
(Program Suspend)
(Read Status)
0
0
(Read Array)
Program
Completed
Wr i te F F
(Re ad
Array)
10. Program Suspend/Resume Procedure
Bus
Operation Command Comments
Write
Write
Program
Suspend
Read
Status
Read None
Idle None
Idle None
Write Read Array
Read None
Write
Program
Resume
Data = B0
Addr = Any Address
Data = 70
Addr = Any address
Status register data: Toggle CE
or
to update status register
OE
Addr = Any address
Check SR7
1 = WSM Ready
0 = WSM Busy
Check SR2
1 = Program suspended
0 = Program completed
Data = FF
Addr = Any address
Read data from any word in the
memory
Data = D0
Addr = Any address
Done
Reading
Ye s
Wr i te D 0
Any Address
Program
Resumed
No
(Progra m Resume)
Read
Data
3591C–FLASH–6/06
11
11. Sector Erase Flowchart
Start
12. Sector Erase Procedure
Bus
Operation Command Comments
Wri te 2 0,
Any Address
Wri te D 0,
Addr ess
Sector
Read Status
Register
SR7 =
Full Er ase
Status Check
(IfDesired)
Sector
Complete
(Erase)
Sector
(Erase Confirm)
0 Ye s
1
Erase
No
Suspend
Eras e
Suspend
Eras e
Loop
13. Full Erase Status Check Flowchart
Read Status
Register
SR3 =
SR4, SR5
SR5 =
SR1 =
Sector
Erase
Successful
1
0
1,1
=
0
1
0
1
0
VPPRange
Error
Command
Sequenc e Err or
Sector
Eras e
Error
Sector
Lock ed
Error
Write
Write
Sector
Erase
Setup
Erase
Confirm
Data = 20
Addr = Any Address
Data = D0
Addr = Sector to be erased (SA)
Status register data: Toggle CE
Read None
or
to update status register data
OE
Check SR7
Idle None
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent sector erasures.
Full status register check can be done after each sector erase,
or after a sequence of sector erasures.
Write FF after the last operation to enter read mode.
14. Full Erase Status Check Procedure
Bus
Operation Command Comments
Idle None
Idle None
Idle None
Idle None
SR1, SR3 must be cleared before the Write State Machine
allows further erase attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4, SR5.
If an error is detected, clear the status register before
attempting an erase retry or other error recovery.
Check SR3:
1 = V
Range Error
PP
Check SR4, SR5:
Both 1 = Command Sequence
Error
Check SR5:
1 = Sector Erase Error
Check SR1:
1 = Attempted erase of locked
sector; erase aborted.
12
AT49BV160D(T)
3591C–FLASH–6/06
AT49BV160D(T)
15. Erase Suspend/Resume Flowchart
Star t
(Rea d A rray)
(E ra se R esu me )
Write B0,
Any Address
Write 70,
Any Address
Read Status
Regis ter
SR7 =
SR6 =
Wr it e FF
Read
Data
Done
Reading
Write D0,
Any Address
1
1
1
(Erase Suspend)
(Read Status)
0
0
0
Erase
Completed
Wri te FF
(Rea d A rray)
16. Erase Suspend/Resume Procedure
Bus
Operation Command Comments
Write
Write
Erase
Suspend
Read
Status
Read None
Idle None
Idle None
Write
Read or
Write
Write
Read or
Program
None
Program
Resume
Data = B0
Addr = Any address
Data = 70
Addr = Any address
Status register data: Toggle CE
or
to update status register
OE
Addr = Any address
Check SR7
1 = WSM Ready
0 = WSM Busy
Check SR6
1 = Erase suspended
0 = Erase completed
Data = FF or 40
Addr = Any address
Read or program data from/to
sector other than the one being
erased
Data = D0
Addr = Any address
Erase
Resumed
Read Array
Data
3591C–FLASH–6/06
13
17. Protection Register Programming
18. Protection Register Programming
Flowchart
Start
Wri te C0,
Any Address
Wri te PR
Addres s Data
Read-Status
Register
SR7 =
1
Full-Status
Chec k
(If Des ired)
Progr am
Complete
(Program-Setup)
(Confirm Data )
0
Procedure
Bus
Operation Command Comments
Write
Write
Program
PR Setup
Protection
Program
Read None
Idle None
Program Protection Register operation addresses must be
within the protection register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to return to the Read mode.
Data = C0
Addr = Any Address
Data = Data to Program
Addr = Location to Program
Status register data: Toggle CE
or
to update status register data
OE
Check SR7
1 = WSM Ready
0 = WSM Busy
19. Full Status Check Flowchart
Read Status
Register Data
SR3, SR4
SR3, SR4
SR3, SR4
Program
Successful
1
= VPPRangeError
0
1
1
Progr am Er ror
Regi ster Locked;
Progr am Abor ted
=
0
=
0
20. Full Status Check Procedure
Bus
Operation Command Comments
Idle None
Idle None
Idle None
SR3 must be cleared before the Write State Machine allows
further program attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Check SR1, SR3, SR4:
0,1,1 = V
Range Error
PP
Check SR1, SR3, SR4:
0,0,1 = Programming Error
Check SR1, SR3, SR4:
1, 0,1 = Sector locked; operation
aborted
14
AT49BV160D(T)
3591C–FLASH–6/06
21. Command Definition Table
AT49BV160D(T)
1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle
Addr Data Addr Data Addr Data
Command Sequence
Bus
Cycles
Read 1 XX FF
Sector Erase/Confirm 2 XX 20 SA
Word Program 2 XX 40/10 Addr D
Dual-word Program
(3)
3XXE0Addr0D
(2)
D0
IN0
IN
Addr1 D
IN1
Erase/Program Suspend 1 XX B0
Erase/Program Resume 1 XX D0
Product ID Entry
Sector Softlock 2 XX 60 SA
Sector Hardlock 2 XX 60 SA
Sector Unlock 2 XX 60 SA
Read Status Register 2 XX 70 XX D
(4)
1XX90
(2)
(2)
(2)
01
2F
D0
OUT
(5)
Clear Status Register 1 XX 50
Program Protection Register 2 XX C0 Addr
(6)
D
IN
Lock Protection Register – Sector B 2 XX C0 80 FFFD
Status of Sector B Protection 2 XX 90 80 D
OUT
(7)
CFI Query 1 XX 98
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A19 through A8 are don’t care.
2. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 and 18
for details).
3. This fast programming option enables the user to program two words in parallel only when V
Addr0 and Addr1, of the two words, D
IN0
and D
, must only differ in address A0. This command should be used during
IN1
= 9.5V. The addresses,
PP
manufacturing purposes only.
4. During the second bus cycle, the manufacturer code is read from address 00000H, the device code is read from address
00001H, and the data in the protection register is read from addresses 00081H - 00088H.
5. The status register bits are output on I/O7 - I/O0.
6. Any addresses within the user programmable protection register region. Address locations are shown on “Protection Regis-
ter Addressing Table” on page 16.
7. If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed.
22. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground ...........................-0.6V to V
Voltage on V
PP
with Respect to Ground ...................................-0.6V to +10.0V
3591C–FLASH–6/06
CCQ
+ 0.6V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
15
23. Protection Register Addressing Table
WordUseSectorA7A6A5A4A3A2A1A0
0FactoryA10000001
1FactoryA10000010
2FactoryA10000011
3FactoryA10000100
4UserB10000101
5UserB10000110
6UserB10000111
7UserB10001000
Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
16
AT49BV160D(T)
3591C–FLASH–6/06
AT49BV160D(T)
24. AT49BV160D – Sector Address Table
Sector Size (Bytes/Words) Address Range (A19 - A0)
SA0 8K/4K 00000 - 00FFF
SA1 8K/4K 01000 - 01FFF
SA2 8K/4K 02000 - 02FFF
SA3 8K/4K 03000 - 03FFF
SA4 8K/4K 04000 - 04FFF
SA5 8K/4K 05000 - 05FFF
SA6 8K/4K 06000 - 06FFF
SA7 8K/4K 07000 - 07FFF
SA8 64K/32K 08000 - 0FFFF
SA9 64K/32K 10000 - 17FFF
SA10 64K/32K 18000 - 1FFFF
SA11 64K/32K 20000 - 27FFF
SA12 64K/32K 28000 - 2FFFF
SA13 64K/32K 30000 - 37FFF
SA14 64K/32K 38000 - 3FFFF
SA15 64K/32K 40000 - 47FFF
SA16 64K/32K 48000 - 4FFFF
SA17 64K/32K 50000 - 57FFF
SA18 64K/32K 58000 - 5FFFF
SA19 64K/32K 60000 - 67FFF
SA20 64K/32K 68000 - 6FFFF
SA21 64K/32K 70000 - 77FFF
SA22 64K/32K 78000 - 7FFFF
SA23 64K/32K 80000 - 87FFF
SA24 64K/32K 88000 - 8FFFF
SA25 64K/32K 90000 - 97FFF
SA26 64K/32K 98000 - 9FFFF
SA27 64K/32K A0000 - A7FFF
SA28 64K/32K A8000 - AFFFF
SA29 64K/32K B0000 - B7FFF
SA30 64K/32K B8000 - BFFFF
SA31 64K/32K C0000 - C7FFF
SA32 64K/32K C8000 - CFFFF
SA33 64K/32K D0000 - D7FFF
SA34 64K/32K D8000 - DFFFF
SA35 64K/32K E0000 - E7FFF
SA36 64K/32K E8000 - EFFFF
SA37 64K/32K F0000 - F7FFF
SA38 64K/32K F8000 - FFFFF
3591C–FLASH–6/06
17
25. AT49BV160DT – Sector Address Table
x16
Sector Size (Bytes/Words)
SA0 64K/32K 00000 - 07FFF
SA1 64K/32K 08000 - 0FFFF
SA2 64K/32K 10000 - 17FFF
SA3 64K/32K 18000 - 1FFFF
SA4 64K/32K 20000 - 27FFF
SA5 64K/32K 28000 - 2FFFF
SA6 64K/32K 30000 - 37FFF
SA7 64K/32K 38000 - 3FFFF
SA8 64K/32K 40000 - 47FFF
SA9 64K/32K 48000 - 4FFFF
SA10 64K/32K 50000 - 57FFF
SA11 64K/32K 58000 - 5FFFF
SA12 64K/32K 60000 - 67FFF
SA13 64K/32K 68000 - 6FFFF
SA14 64K/32K 70000 - 77FFF
SA15 64K/32K 78000 - 7FFFF
SA16 64K/32K 80000 - 87FFF
SA17 64K/32K 88000 - 8FFFF
SA18 64K/32K 90000 - 97FFF
SA19 64K/32K 98000 - 9FFFF
SA20 64K/32K A0000 - A7FFF
SA21 64K/32K A8000 - AFFFF
SA22 64K/32K B0000 - B7FFF
SA23 64K/32K B8000 - BFFFF
SA24 64K/32K C0000 - C7FFF
SA25 64K/32K C8000 - CFFFF
SA26 64K/32K D0000 - D7FFF
SA27 64K/32K D8000 - DFFFF
SA28 64K/32K E0000 - E7FFF
SA29 64K/32K E8000 - EFFFF
SA30 64K/32K F0000 - F7FFF
SA31 8K/4K F8000 - F8FFF
SA32 8K/4K F9000 - F9FFF
SA33 8K/4K FA000 - FAFFF
SA34 8K/4K FB000 - FBFFF
SA35 8K/4K FC000 - FCFFF
SA36 8K/4K FD000 - FDFFF
SA37 8K/4K FE000 - FEFFF
SA38 8K/4K FF000 - FFFFF
Address Range (A19 - A0)
18
AT49BV160D(T)
3591C–FLASH–6/06
AT49BV160D(T)
26. DC and AC Operating Range
AT49BV160D(T)-70
Operating Temperature (Case) Ind. -40°C - 85°C
VCC Power Supply 2.65V to 3.6V
27. Operating Modes
V
PP
X
IHPP
(1)
(2)
(4)
Ai I/O
Ai D
Ai D
X
(5)
V
ILPP
X X High-Z
A0 = VIL, A1 - A19 = VILManufacturer Code
A0 = VIH, A1 - A19 = V
IL
Mode CE OE WE RESET V
Read V
Program/Erase
(3)
Standby/Program Inhibit V
IL
V
IL
IH
XXV
Program Inhibit
XV
XXXV
Output Disable X V
Reset X X X V
Product Identification
Software
Notes: 1. The VPP pin can be tied to V
V
IL
V
IH
(2)
X
IL
IH
for faster program operations, VPP pin can be set 9.5V ± 0.5V.
CC
V
IH
V
IL
V
IH
V
IH
XVIHX X High-Z
IH
V
IH
XVIHX
IH
XVIHX High-Z
IL
V
IH
2. X can be VIL or VIH.
3. Refer to “Program Cycle Waveforms” on page 23.
4. V
5. V
(min) = 1.65V.
IHPP
(max) = 0.4V.
ILPP
6. Manufacturer Code: 001FH, Device Code: 90C3H – AT49BV160D; 90C2H – AT49BV160DT.
OUT
IN
Device Code
(6)
(6)
28. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
LI
I
LO
I
SB
(1)
I
CC
I
CC1
I
PP1
V
IL
V
IH
V
OL
V
OH
Note: 1. In the erase mode, ICC is 25 mA.
Input Load Current VIN = 0V to V
Output Leakage Current V
= 0V to V
I/O
CC
CC
VCC Standby Current CMOS CE = VCC - 0.3V to V
V
Active Read Current f = 5 MHz; I
CC
= 0 mA 10 15 mA
OUT
CC
15 25 µA
2µA
2µA
VCC Programming Current 25 mA
VPP Input Load Current 10 µA
Input Low Voltage 0.6 V
Input High Voltage V
- 0.6 V
CCQ
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -100 µA V
- 0.1 V
CCQ
3591C–FLASH–6/06
19
29. Input Test Waveforms and Measurement Level
2.0V
1.5V
0.6V
tR, tF < 5 ns
30. Output Test Load
V
CCQ
1.8
1.3
31. Pin Capacitance
f = 1 MHz, T = 25°C
Symbol
C
IN
C
OUT
Note: This parameter is characterized and is not 100% tested.
(1)
Typ Max Units Conditions
46pFV
812pFV
3
= 0V
IN
= 0V
OUT
20
AT49BV160D(T)
3591C–FLASH–6/06
32. AC Read Characteristics
Symbol Parameter
AT49BV160D(T)
AT49BV160D(T)-70
UnitsMin Max
t
t
t
t
t
t
t
RC
ACC
CE
OE
DF
OH
RO
(1)
(2)
(3)(4)
Read Cycle Time 70 ns
Address to Output Delay 70 ns
CE to Output Delay 70 ns
OE to Output Delay 0 20 ns
CE or OE to Output Float 0 25 ns
Output Hold from OE, CE or Address,
whichever occurred first
RESET to Output Delay 100 ns
33. AC Read Waveforms
ADDRESS
CE
OE
(1)(2)(3)(4)
t
RC
ADDRESS VALID
t
CE
t
OE
t
ACC
0ns
t
DF
t
OH
RESET
OUTPUT
Notes: 1. CE may be delayed up to t
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t
is specified from OE or CE, whichever occurs first (CL = 5 pF).
3. t
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
3591C–FLASH–6/06
t
RO
HIGH Z
- tCE after the address transition without impact on t
ACC
OUTPUT
VALID
ACC
.
- tOE after an address change
ACC
21
34. AC Word Load Characteristics
Symbol Parameter Min Max Units
t
AS
t
AH
t
CS
t
CH
t
WP
t
WPH
t
DS
t
DH
, t
OES
, t
OEH
Address, OE Setup Time 20 ns
Address Hold Time 0 ns
Chip Select Setup Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)25ns
Write Pulse Width High 15 ns
Data Setup Time 25 ns
Data, OE Hold Time 0 ns
35. AC Word Load Waveforms
35.1 WE Controlled
35.2 CE
22
AT49BV160D(T)
Controlled
3591C–FLASH–6/06
AT49BV160D(T)
36. Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
t
BPD
t
AS
t
AH
t
DS
t
DH
t
WP
t
WPH
t
WC
t
RP
t
SEC1
t
SEC2
t
ES
t
PS
t
ERES
Word Programming Time 10 120 µs
Word Programming Time in Dual Programming Mode 5 60 µs
Address Setup Time 20 ns
Address Hold Time 0 ns
Data Setup Time 25 ns
Data Hold Time 0 ns
Write Pulse Width 25 ns
Write Pulse Width High 15 ns
Write Cycle Time 70 ns
Reset Pulse Width 500 ns
Sector Erase Cycle Time (4K Word Sectors) 0.1 2.0 seconds
Sector Erase Cycle Time (32K Word Sectors) 0.5 6.0 seconds
Erase Suspend Time 15 µs
Program Suspend Time 10 µs
Delay between Erase Resume and Erase Suspend 500 µs
37. Program Cycle Waveforms
OE
PROGRAM CYCLE
CE
WE
A0 - A19
DATA
tASt
(1)
XX
t
WC
Note 3
t
WPH
AH
38. Sector Erase Cycle Waveforms
(2)
OE
CE
t
AS
XX
t
WC
(1)
20
WORD 0
t
WPH
t
AH
SA
WE
A0-A19
DATA
Notes: 1. Any address can be used to load the data.
2. OE must be high only when WE and CE are both low.
3. The data can be 40H or 10H.
4. The address depends on what sector is to be erased.
t
WP
ADDRESS
t
DS
INPUT DATA
t
WP
(4)
t
DS
D0
WORD 1
t
BP
t
DH
t
DH
t
SEC1/2
3591C–FLASH–6/06
23
39. Common Flash Interface Definition Table
Address AT49BV160DT AT49BV160D
10h 0051h 0051h “Q”
11h 0052h 0052h “R”
12h 0059h 0059h “Y”
13h 0003h 0003h
14h 0000h 0000h
15h 0041h 0041h
16h 0000h 0000h
17h 0000h 0000h
18h 0000h 0000h
19h 0000h 0000h
1Ah 0000h 0000h
1Bh 0027h 0027h VCC min write/erase
1Ch 0036h 0036h VCC max write/erase
1Dh 0090h 0090h VPP min voltage
1Eh 00A0h 00A0h VPP max voltage
1Fh 0004h 0004h Typ word write – 10 µs
20h 0002h 0002h Typ dual word program time – 5 µs
21h 0009h 0009h Typ sector erase, 500 ms
22h 0000h 0000h Typ chip erase, not supported
23h 0004h 0004h Max word write/typ time
24h 0004h 0004h Max dual word program time/typ time
25h 0004h 0004h Max sector erase/typ sector erase
26h 0000h 0000h Max chip erase/ typ chip erase
27h 0015h 0015h Device size
28h 0001h 0001h x16 device
29h 0000h 0000h x16 device
2Ah 0002h 0002h Maximum number of bytes in multiple byte write = 4
2Bh 0000h 0000h Maximum number of bytes in multiple byte write = 4
2Ch 0002h 0002h 2 regions, x = 2
2Dh 001Eh 0007h 64K bytes, Y = 30 (Top); 8K bytes, Y = 7 (Bottom)
2Eh 0000h 0000h 64K bytes, Y = 30 (Top); 8K bytes, Y = 7 (Bottom)
2Fh 0000h 0020h 64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
30h 0001h 0000h 64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
31h 0007h 001Eh 8K bytes, Y = 7 (Top); 64K bytes, Y = 30 (Bottom)
32h 0000h 0000h 8K bytes, Y = 7 (Top); 64K bytes, Y = 30 (Bottom)
33h 0020h 0000h 8K bytes, Z = 32 (Top); 64K bytes, Z = 256 (Bottom)
34h 0000h 0001h 8K bytes, Z = 32 (Top); 64K bytes, Z = 256 (Bottom)
24
AT49BV160D(T)
3591C–FLASH–6/06
AT49BV160D(T)
39. Common Flash Interface Definition Table (Continued)
Address AT49BV160DT AT49BV160D
VENDOR SPECIFIC EXTENDED QUERY
41h 0050h 0050h “P”
42h 0052h 0052h “R”
43h 0049h 0049h “I”
44h 0031h 0031h Major version number, ASCII
45h 0030h 0030h Minor version number, ASCII
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported,
46h 0086h 0086h
47h 0000h 0001h Bit 0 – top (“0”) or bottom (“1”) boot sector device undefined bits are “0”
0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
Bit 0 – 4 word linear burst with wrap around,
0 – no, 1 – yes
48h 0000h 0000h
49h 0000h 0000h
4Ah 0080h 0080h Location of protection register lock byte, the section’s first byte
4Bh 0003h 0003h # of bytes in the factory prog section of prot register – 2*n
4Ch 0003h 0003h # of bytes in the user prog section of prot register – 2*n
Bit 1 – 8 word linear burst with wrap around,
0 – no, 1 – yes
Bit 2 – continuos burst, 0 - no, 1 - yes
Undefined bits are “0”
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
3591C–FLASH–6/06
25
40. Ordering Information
40.1 Green Package (Pb/Halide-free)
I
(mA)
t
ACC
(ns)
CC
Ordering Code Package Operation RangeActive Standby
70 15 0.025
AT49BV160D-70TU
AT49BV160DT-70TU
48T
Industrial
(-40° to 85° C)
Package Type
48T 48-lead, Plastic Thin Small Outline Package (TSOP)
26
AT49BV160D(T)
3591C–FLASH–6/06
41. Packaging Information
41.1 48T – TSOP
AT49BV160D(T)
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 11.90 12.00 12.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
c
L1
GAGE PLANE
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
3591C–FLASH–6/06
TITLE
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
48T
10/18/01
REV.
B
27
42. Revision History
Revision No. History
Revision A – Dec. 2005
Revision B – Jun. 2006 • Changed the device codes of the AT49BV160D; AT49BV160DT to
Revision C – Jun. 2006 • Removed CBGA package option.
• Initial Release
90C3H and 90C2H, respectively.
• Removed the additional device code.
• Changed the comments of address 47H of the Common Flash
Interface Definition table to indicate bit 0, not bit 8, can be used to
identify the device as a top or bottom boot.
28
AT49BV160D(T)
3591C–FLASH–6/06
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