ATMEL AT49BV040B User Manual
BDTIC www.BDTIC.com/ATMEL
Features
•
Single Supply for Read and Write: 2.7V to 5.5V
•
Fast Read Access Time – 70 ns (VCC = 2.7V to 3.6V); 55 ns (VCC = 4.5V to 5.5V)
•
Internal Program Control and Timer
•
Flexible Sector Architecture
– One 16K Bytes Boot Sector with Programming Lockout
– Two 8K Bytes Parameter Sectors
– Eight Main Memory Sectors (One 32K Bytes, Seven 64K Bytes)
•
Fast Erase Cycle Time – 8 Seconds
•
Byte-by-Byte Programming – 10 µs/Byte Typical
•
Hardware Data Protection
•
DATA Polling or Toggle Bit for End of Program Detection
•
Low Power Dissipation
– 20 mA Active Current
– 25 µA CMOS Standby Current for V
– 30 µA CMOS Standby Current for V
•
Minimum 100,000 Write Cycles
= 2.7V to 3.6V
CC
= 4.5V to 5.5V
CC
4-megabit
(512K x 8)
Flash Memory
AT49BV040B
1. Description
The AT49BV040B is a 2.7V to 5.5V in-system reprogrammable Flash Memory. Its
4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers an access time of
70 ns (V
power dissipation over the industrial temperature range with V
mW and is 110 mW with V
When the device is deselected, the CMOS standby current is less than 30 µA. To
allow for simple in-system reprogrammability, the AT49BV040B does not require high
input voltages for programming. Reading data out of the device is similar to reading
from an EPROM; it has standard CE
Reprogramming the AT49BV040B is performed by erasing a sector of data and then
programming on a byte by byte basis. The byte programming time is a fast 10 µs. The
end of a program or erase cycle can be optionally detected by the DATA
toggle bit feature. Once the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase
cycles is in excess of 100,000 cycles.
The device is erased by executing a chip erase or a sector erase command sequence;
the device internally controls the erase operations. The memory array of the
AT49BV040B is organized into two 8K byte parameter sectors, eight main memory
sectors, and one boot sector.
= 2.7V to 3.6V) and an access time of 55 ns (VCC = 4.5V to 5.5V). The
CC
= 2.7V to 3.6V is 72
CC
= 4.5V to 5.5V.
CC
, OE, and WE inputs to avoid bus contention.
polling or
The device has the capability to protect the data in the boot sector; this feature is
enabled by a command sequence. The 16K-byte boot sector includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain
user secure code, and when the feature is enabled, the boot sector is permanently
protected from being reprogrammed.
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2. Pin Configurations
Pin Name Function
A0 - A18 Addresses
CE Chip Enable
OE
Output Enable
WE
I/O0 - I/O7 Data Inputs/Outputs
2.1 32-lead PLCC Top View
Write Enable
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A12
A15
A16
A18
432
1
5
6
7
8
9
10
11
12
13
14151617181920
I/O1
I/O2
I/O3
GND
VCCWEA17
323130
29
28
27
26
25
24
23
22
21
I/O4
I/O5
I/O6
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
2.2 32-lead VSOP or 32-lead TSOP Top View – Type 1
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A13
A14
A17
WE
VCC
A18
A16
A15
A12
2
AT49BV040B
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
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3. Block Diagram
VCC
GND
WE
ADDRESS
INPUTS
AT49BV040B
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE
CE
CONTROL
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
MAIN MEMORY
SECTOR 8
(64K BYTES)
MAIN MEMORY
SECTOR 7
(64K BYTES)
MAIN MEMORY
SECTOR 6
(64K BYTES)
MAIN MEMORY
SECTOR 5
(64K BYTES)
MAIN MEMORY
SECTOR 4
(64K BYTES)
MAIN MEMORY
SECTOR 3
(64K BYTES)
MAIN MEMORY
SECTOR 2
(64K BYTES)
MAIN MEMORY
SECTOR 1
(32K BYTES)
PARAMETER
SECTOR 2
(8K BYTES)
PARAMETER
SECTOR 1
(8K BYTES)
BOOT SECTOR
(16K BYTES)
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
4. Device Operation
4.1 Read
The AT49BV040B is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE
trol gives designers flexibility in preventing bus contention.
4.2 Command Sequences
When the device is first powered on, it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the
Command Definitions table. The command sequences are written by applying a low pulse on the
WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE
CE
or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
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or OE is high. This dual-line con-
or WE, whichever occurs last. The data is latched by the first rising edge of
3
4.3 Erasure
Before a byte can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
4.3.1 Chip Erase
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Sector
1, Parameter Sector 2, Main Memory Sectors 1 - 8, but not the boot sector. If the Boot Sector
Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full
chip erase the device will return back to read mode. Any command during chip erase will be
ignored.
4.3.2 Sector Erase
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter sectors and eight main memory sectors. The 8K-byte
parameter sectors and the eight main memory sectors can be independently erased and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector address is
latched on the falling WE
the rising edge of WE
erase operation is internally controlled; it will automatically time to completion.
4.4 Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4-bus cycle operation (see “Command Definition Table” on page 7). The device will
automatically generate the required internal program pulses.
edge of the sixth cycle while the 30H data input command is latched at
. The sector erase starts after the rising edge of WE of the sixth cycle. The
The program cycle has addresses latched on the falling edge of WE
last, and the data latched on the rising edge of WE
is completed after the specified t
be used to indicate the end of a program cycle.
4.5 Boot Sector Programming Lockout
The device has one designated sector that has a programming lockout feature. This feature prevents programming of data in the designated sector once the feature has been enabled. The
size of the sector is 16K bytes. This sector, referred to as the boot sector, can contain secure
code that is used to bring up the system. Enabling the lockout feature will allow the boot code to
stay in the device while data in the rest of the device is updated. This feature does not have to
be activated; the boot sector’s usage as a write protected region is optional to the user. The
address range of the boot sector is 00000 to 03FFF.
Once the feature is enabled, the data in the boot sector can no longer be erased or programmed. Data in the main memory and parameter sectors can still be changed through the
regular programming method. To activate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed. See “Command Definition Table” on
page 7.
or CE, whichever occurs
or CE, whichever occurs first. Programming
cycle time. The DATA polling or toggle bit feature may also
BP
4
AT49BV040B
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4.5.1 Boot Sector Lockout Detection
A software method is available to determine if programming of the boot sector is locked out.
When the device is in the software product identification mode (
Entry/Exit on page 15
sector is locked out. If the data on I/O0 is low, the boot sector can be programmed; if the data on
I/O0 is high, the program lockout feature has been activated and the sector cannot be programmed. The software product identification code should be used to return to standard
operation.
4.6 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.7 Data Polling
The AT49BV040B features DATA polling to indicate the end of a program or erase cycle. During
a program cycle an attempted read of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA
cycle. During a chip or sector erase operation, an attempt to read the device will give a “0” on
I/O7. Once the erase operation is completed, a “1” will be read from I/O7. The Data Polling status bit must be used in conjunction with the erase/program status bit as shown in the algorithm
in Figure 4-1 on page 6.
AT49BV040B
see Software Product Identification
) a read from address location 00002H will show if programming the boot
polling may begin at any time during the program
4.8 Toggle Bit
In addition to DATA polling, the AT49BV040B provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle. The toggle bit status bit should be used in conjunction
with the erase/program status bit shown in the algorithm in Figure 4-2 on page 6.
4.9 Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation
has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable
to verify that an erase or a byte program operation has been successfully performed. If a program (Sector Erase) command is issued to the boot sector and the boot sector programming
lockout feature is enabled, the boot sector will not be programmed (erased), and the device will
go into the read mode. Once the erase/program status bit has been set to a “1”, the system must
write the Product ID Exit command to return to the read mode. The erase/program status bit is a
“0” while the erase or program operation is still in progress.
4.10 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV040B in the following
ways: (a) V
inhibit: holding any one of OE
pulses of less than 15 ns (typical) on the WE
CC
sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program
low, CE high or WE high inhibits program cycles. (c) Noise filter:
or CE inputs will not initiate a program cycle.
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5
Figure 4-1. Data Polling Algorithm Figure 4-2. Toggle Bit Algorithm
START
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
YES
NO
NO
I/O5 = 1?
YES
Read I/O7 - I/O0
Addr = VA
YES
I/O7 = Data?
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
Program/Erase
Operation
Successful,
Device in
Read Mode
START
Read I/O7 - I/O0
Read I/O7 - I/O0
NO
Read I/O7 - I/O0
Program/Erase
Successful, Write
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Toggle Bit =
To gg l e?
YES
I/O5 = 1?
YES
Tw ic e
Toggle Bit =
To gg l e?
YES
Operation Not
Product ID
Exit Command
NO
NO
Program/Erase
Operation
Successful, Device
in Read Mode
6
AT49BV040B
3499B–FLASH–4/06
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