ATMEL AT49BV001A, AT49BV001AN, AT49BV001AT, AT49BV001ANT User Manual

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Features

• Single Supply for Read and Write: 2.7 to 3.6V

• Fast Read Access Time – 55 ns

• Internal Program Control and Timer

• Sector Architecture

– One 16K Bytes Boot Block with Programming Lockout – Two 8K Bytes Parameter Blocks – Two Main Memory Blocks (32K Bytes, 64K Bytes)

• Fast Erase Cycle Time – 3 Seconds

• Byte-by-Byte Programming – 30 µs/Byte Typical

• Hardware Data Protection

• DAT A Polling for End of Program Detection

• Low Power Dissipation

– 15 mA Active Current – 50 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49BV001A(N)(T) is a 2.7-volt-only in-system reprogrammable Flash Memory. Its 1 megabit of mem or y is o rgani zed as 13 1,072 wor ds by 8 bits. Ma nufactured wit h Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 54 mW over the industrial temperature range.

1-megabit (128K x 8) Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV001A

™

Pin Configurations

Pin Name Function

A0 - A16 Addresses CE OE Output Enable WE RESET I/O0 - I/O7 Data Inputs/Outputs NC No Connect

Chip Enable

Write Enable RESET

PLCC Top View

A12

A15

A16

RESET*

432

14151617181920

I/O0

VCCWENC

323130

29 28 27 26 25 24 23 22 21

A14 A13 A8 A9 A11 OE A10 CE I/O7

VSOP Top View (8 x 14 mm) or

TSOP Top View (8 x 20 mm)

Type 1

A11

A13

A14

VCC

A16 A15 A12

9 10 11 12 13

*RESET

AT49BV001AN AT49BV001AT AT49BV001ANT

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

GND

I/O6

Note: *This pin is a NC on the AT49BV001AN(T).

Rev. 3364C–FLASH–9/03

When the device is deselected, the CM OS standby current i s less than 50 µA. For the AT49BV001AN (T), pin 1 fo r the PL CC package and pin 9 for the TSOP packa ge are no co nnect pins. To allow for simple in-system reprogrammability, the AT49BV001A(N)(T) does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has s tan dard CE

, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV001A(N)(T) is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA

polling feature. Once the end of a byte pr og ram cycl e has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections, two main memory blocks, and one boot block.

The device has the capabil it y to prot ec t the da ta in th e boo t blo ck ; thi s featur e i s enabl ed by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data int egrity. The boot sector i s designe d to contain user secur e code, an d when the feature is enabled, the boot sector is protected from being reprogrammed.

In the AT49BV001AN(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49BV001A(T), once the boot block programming lockout feature i s enabled, the conten ts of the boot bl ock cannot be changed with input voltage levels of 5.5 volts or less.

Block Diagram

VCC

GND

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49BV001A(N)

DATA INPUTS/OUTPUTS

I/O7 - I/O0

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

1FFFF

10000 0FFFF

08000 07FFF

06000 05FFF

04000 03FFF

00000

AT49BV001A(N)T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

BOOT BLOCK

(16K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

1FFFF

1C000 1BFFF

1A000 19FFF

18000 17FFF

10000 0FFFF

00000

AT49BV001A(N)(T)

3364C–FLASH–9/03

AT49BV001A(N)(T)

Device Operation

READ: The AT49BV001A(N)(T) is accessed like an EPROM. When CE and OE are low and

is high, the data stored at the memory location determined by the address pins is asserted

WE on the outputs. The outputs are put in the high impedance state whenever CE This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the d evi ce i s fir st p owered on i t wil l be rese t to the read or standby mode depending upon the state of th e control line inputs. In order to perform other device functions , a ser i es o f c om man d se que nce s ar e en tered i nto th e device. The com man d sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE The address is latch ed on th e falling edge of CE latched by the first rising edge of CE The address location s us ed in the co mm and s equ ences are not affe cte d by enter in g the command sequences.

RESET: A RESET a logic high level, the device is in its standard operating mode. A low level on the RESET halts the present device operation and puts the outputs of the device in a high impedance state. If the RESET operation may not be su cces sfully c omple ted and th e ope ration wi ll hav e to be repea ted a fter a high level is applied to the RESET the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET grammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available on the AT49BV001AN(T).

input pin is provided to ease some system applications. When RESET is at

pin makes a high to low tr ansi ti on du ri ng a prog ram or er as e op erat ion , the

or CE input with CE or WE low (respectively) and OE high.

or WE, whichever occurs l ast. The data is

or WE. Standard microp roce ssor wr ite tim ings ar e use d.

pin. When a h igh lev el is re asse rted on th e RESET pin,

pin, the boot block a rray can be repro-

or OE is high.

input

ERASURE: Before a byte can be reprogrammed, the main memory blocks or parameter blocks which contains the byte must be erased. Th e er ased state of the memory bits i s a log ical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase operation so that no external c locks ar e requir ed. The ma ximum t ime neede d to era se the w hole chip is t not be erased.

CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1 - 2, but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections and the two main memory blocks can be independently erased and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector ad dress is latch ed on the falling WE 30H data input command is lat che d at the r ising edge of WE rising edge of WE matically time to completion.

. If the boot bl ock l ock out f eature ha s be en en able d, the data in the b oot s ecto r wil l

edge of the sixth cy cle while the

. The sector erase starts after the

of the sixth cycle. The erase operation is internally controlled; it will auto-

3364C–FLASH–9/03

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a

logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only er ase op eratio ns can c onvert “0”s t o “1”s. Progr amming is acco mplish ed via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has add ress es latch ed on the fal ling edge of WE last, and the data latched on the rising edge of WE ming is completed aft er the specified t used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one desi gnated bloc k that has a programming l ockout fe ature. This featu re prev ents prog rammi ng of data in the desig nated block once the feature has been enabled. The si ze of the block is 16K byt es. This block, referred to as th e boot bloc k, can cont ain secu re code tha t is used to br ing up the s ystem. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected regio n is optio nal to the use r. The addres s range of the bo ot block is 00000 to 03FFF for the AT49BV001A(N) while the address range of the boot block is 1C000 to 1FFFF for the AT49BV001A(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed with input voltage of 5.5V or less. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific dat a must be pe rformed. Pl ease refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTI ON: A software method is available to determine if programming of the boot bl ock sect ion is locke d out. Wh en the de vice is in the s oftwar e produc t identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out for the AT49BV001A(N), and a read from address location 1C002H will show if programming the boot block is locked out for th e AT4 9BV001A (N)T. If the data o n I/O0 is lo w, the boo t block c an be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be p rogr ammed . The so ftware p roduc t id entifi cation co de shou ld be u sed to return to standard operation.

cycle time. The DATA polling featur e may also be

or CE, whichever occurs first. Program-

or CE, whichever occurs

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET sector erase or byte programming operation. When the RESET els the boot block programming lockout feature is again active. This feature is not available on the AT49BV001AN(T).

PRODUCT IDENTIFICATION: The product identifi cation mode identifies the de vi ce and m anufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Opera ting Modes (for hardware op eration) or Software Pro duct Identi ficatio n. The manufacturer and device code is the same for both modes.

AT49BV001A(N)(T)

pin to 12 volt s duri ng the entire chip erase ,

pin is brought back to TTL lev-

3364C–FLASH–9/03

AT49BV001A(N)(T)

DATA POLLING: The AT49BV001 A( N)( T) fe ature s DA TA polling to indicate the e nd of a pro-

gram cycle. During a progr am cyc l e an att emp ted rea d of the last byte loaded will result in th e complement of the lo aded data on I/O7. Once the program cycle has been co mpleted, true data is valid on al l o u tp uts and the next cycle may b egi n. DAT A during the program cycle.

TOGGLE BIT: In addition to DATA polling the AT49BV001A(N)(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read da ta from the dev ice wil l resul t in I/O6 t ogglin g betwee n one an d zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware featu res pr otect a gainst i nadverte nt pro grams to the AT49BV001A(N) (T) in the foll owing ways: (a) V the program function is inhibited. (b) Program inhibit: holding any one of OE WE

high inhibits prog ra m cyc le s. (c) Noi se fil ter : p uls es of less than 15 ns (typ ic al) o n the WE

or CE inputs will not initiate a program cycle.

sense: if VCC is below 1.8V (t ypic al),

polling may begi n a t an y tim e

low, CE high or

3364C–FLASH–9/03

Command Definition (in Hex)

(1)

1st Bus

Command Sequence

Bus

Cycles

Read 1 Addr D

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

Chip Erase 6 555 AA AAA Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA Byte Program 4 555 AA AAA 55 555 A0 Addr D Boot Block Loc k out

(3)

6 555 AA AAA 55 555 80 555 AA AAA 55 555 40

2nd Bus

Cycle

(2)

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

55 555 80 555 AA AAA 55 555 10

(5)

Product ID Entry 3 555 AA AAA 55 555 90 Product ID Exit Product ID Exit

(4)

3 555 AA AAA 55 555 F0 1 XXXX F0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:

A11 - A0 (Hex); A11 - A16 (don’t care).

2. Since A11 is don’t care, AAA can be replaced with 2AA.

3. The 16K byte boot s ector ha s t he addre ss r ange 0 0000H to 03FFFH f o r the AT49BV001A(N) and 1C000H to 1FFFFH for the AT49BV001A(N)T

4. Either one of the Product ID Exit commands can be used.

5. SA = sector addresses: For the AT49BV001A(N): SA = 00000 to 03FFF for BOOT BLOCK SA = 04000 to 05FFF for PARAMETER BLOCK 1 SA = 06000 to 07FFF for PARAMETER BLOCK 2 SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2

For the AT49BV001A(N)T: SA = 1C000 to 1FFFF for BOOT BLOCK SA = 1A000 to 1BFFF for PARAMETER BLOCK 1 SA = 18000 to 19FFF for PARAMETER BLOCK 2 SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1 SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2

Absolute Maximum Ratings

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect de vi ce rel iab ili ty.

AT49BV001A(N)(T)

3364C–FLASH–9/03

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