ATMEL AT48801-16QI, AT48801-16QC Datasheet
8 Bit
SpreadSpectrum
Microcontroller
Preliminary
Features
0629A
Compatible with MCS-51Products
•
8K bytes of On-Board Program Mem ory
•
Fully Static Operati on : 0 Hz to 16 MHz
•
256 x 8 Bit Internal RAM
•
32 Programmable I/O Lines
•
Three 16 Bit Timer/Coun ters
•
Eight Interrupt Sources
•
Programmable Serial Ch an ne l
•
Low Power Idle and Power Down Modes
•
Description
The AT48801 is a low-power, high-performance CMOS 8 bit microcomputer with 8K
bytes on-board program memory. The device is compatible with the industry standard
80C51 and 80C52 instruction set and pinout. The Atmel AT48801 is a powerful microcomputer which provides a highly flexible and cost effective solution to spread-spectrum applications.
The AT48801 provides the following standard features: 8K bytes of program memory,
256-bytes of RAM, 32 I/O lines, three 16 bit timer/counters, a six-vector two-level
interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT48801 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next hardware reset.
AT48801
Pin Configuration
PQFP
1-1
Block Diagram
1-2 AT48801
AT48801
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8 bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.
Port 1
Port 1 is an 8 bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port Pin
P1.0
P1.1
Port 2
Port 2 is an 8 bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I
Port 2 emits the high-order address byte during fetches
from external pro gram memory and during accesses to
external data memory that use 16 bit addresses (MOVX
@ DPTR). In this application, Port 2 uses strong internal
pullups when emitting 1s. During accesses to external
data memory that use 8 bit addresses (MOVX @ RI), Port
2 emits the contents of the P2 Special Function Register.
Port 3
Port 3 is an 8 bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
) because of the internal pullups.
IL
Alternate Functions
T2 (external count input to
Timer/Counter 2), clock-out
T2EX (Timer/Counter 2 capture/reload
trigger and direction control)
) because of the internal pullups.
IL
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
Port 3 also serves the functions of various special features
of the AT89C51, as shown in the following table.
Port Pin
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2
P3.3
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6
P3.7
RST
Reset inp ut. A high on this pin for t wo machine cycles
while the oscillator is running resets the device.
ALE
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external memory.
In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external
timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data
memory.
If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only
during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no effect if the microcrontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT48801 is executing code from external program memory,
cle, except that two
each access to external data memory.
EA
External Access Enable.
order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is pr ogrammed,
internally latched on reset.
EA should be strapped to VCC for internal program executions.
) because of the pullups.
IL
Alternate Functions
INT0 (external interrupt 0)
INT1 (external interrupt 1)
WR (external data memory write strobe)
RD (external data memory read strobe)
PSEN is activated twice each machine cy-
PSEN activations are skipped during
EA must be strapped to GND in
EA will be
(continued)
1-3
Pin Description (Continued)
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Special Function Registers
A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Timer 2 Registers Control and status bits are contained
in registers T2C ON (shown in Table 2) and T2MOD
(shown in Table 4) for Timer 2. The register pair
(continued)
Table 1. AT48801 SFR Map and Reset Values
0F8H 0FFH
0F0H
0E8H 0EFH
0E0H
0D8H 0DFH
0D0H
0C8H
0C0H 0C7H
0B8H
0B0H
0A8H
0A0H
B
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0F7H
0E7H
0D7H
0CFH
0BFH
0B7H
0AFH
0A7H
98H
90H
88H
80H
1-4 AT48801
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111SP00000111
SBUF
XXXXXXXX
TMOD
00000000
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
TH1
00000000
PCON
0XXX0000
9FH
97H
8FH
87H
AT48801
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/
Bit76543210
Symbol Function
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be
set when either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on
T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector
to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its
transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer
2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
T2 CP/RL2
C/
CP/
T2
RL2
Timer or counter select for Timer 2. C/
counter (falling edge triggered).
Capture/Reload select. CP/
EXEN2 = 1. CP/
transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored
and the timer is forced to auto-reload on Timer 2 overflow.
RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative
RL2 = 1 causes captures to occur on negative transitions at T2EX if
Special Function Registers (Continued)
(RCAP2H, RCAP2L) are the Capture/Reload registers for
Timer 2 in 16 bit capture mode or 16 bit auto-reload mode.
Interrupt Registers The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Data Memory
The AT48801 implements 256-bytes of on-chip RAM. The
upper 128-bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128bytes have the same addresses as the SFR space but ar e
physically separate from SFR space.
T2 = 0 for timer function. C/T2 = 1 for external event
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128-bytes
of RAM or the SFR space. Instructions that use direct addressing access SFR space.
For example, the f ollowing direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128-bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
(continued)
1-5
Data Memory (Continued)
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128-bytes of data RAM are available as stack space.
Timer 0 and 1
Timer 0 and Timer 1 in the AT48801 operate the same
way as Timer 0 and Timer 1 in the AT89C51.
Timer 2
Timer 2 is a 16 bit Timer/Counter that can operate as
either a timer or an event counter. The type of operation is
selected by bit C/
2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table
3.
Timer 2 consists of two 8 bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a l-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cy cle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in
which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1to-0 transition, the maximum count rate is 1/24 of the os-
T2 in the SFR T2CON (shown in Table
cillator frequency. To ensure that a given level is sampled
at least once before it changes, the level should be held
for at least one full machine cycle.
Table 3. Timer 2 Operating Modes
RCLK + TCLK CP/RL2 TR2 MODE
0 0 1 16 Bit Auto-Reload
0 1 1 16 Bit Capture
1 X 1 Baud Rat e Gen erator
X X 0 (Off)
Capture Mode
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a
l-to-0 transition at external input T2EX also cause s the
current value in TH2 and TL2 to be captured into RCAP2H
and RCAP2L, respectively. In addition, the transition at
T2EX causes bit EXF2 in T2CON to be set. T he E XF2 bit,
like TF2, can generate an interrupt. The capture mode is
illustrated in Figure 1.
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when
configured in its 16 bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located
in the SFR T2MOD (see Table 4). Upon reset, the DCEN
bit is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.
(continued)
Figure 1. Timer 2 in Capture Mode
1-6 AT48801
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