ATMEL AT45DB081D User Manual

Features

Single 2.5V or 2.7V to 3.6V Supply
RapidS® Serial Interface: 66 MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
Page Program Operation
– Intelligent Programming Operation – 4,096 Pages (256/264 Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256 Bytes) – Block Erase (2 Kbytes) – Sector Erase (64 Kbytes) – Chip Erase (8 Mbits)
Two SRAM Data Buffers (256/264 Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7 mA Active Read Current Typical – 25 µA Standby Current Typical – 5 µA Deep Power Down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space – Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
8-megabit
2.5-volt or
2.7-volt DataFlash
®
AT45DB081D

1. Description

The AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB081D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies up to 66 MHz. Its 8,650,752 bits of memory are organized as 4,096 pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB081D also contains two SRAM buffers of 256/264 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self­contained three step read-modify-write operation. Unlike conventional Flash memo­ries that are accessed randomly with multiple address lines and a parallel interface,
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the DataFlash uses a RapidS serial interface to sequentially access its data. The simple sequen­tial access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential.
To allow for simple in-system reprogrammability, the AT45DB081D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB081D is enabled through the chip select pin (CS
) and accessed via a three-wire interface consisting of the Serial Input (SI),
Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.

2. Pin Configurations and Pinouts

Figure 2-1. MLF Top View Figure 2-2. DataFlash Card
Top View through Package
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO GND VCC WP
7654321
Note: 1. See AT45DCB001D Datasheet.
Figure 2-3. SOIC Top View
1
SI
SCK
RESET
CS
2 3 4
SO
8
GND
7
VCC
6
WP
5
(1)
2
AT45DB081D
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Table 2-1. Pin Configurations
Symbol Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device
will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a high-impedance state. When the device is deselected, data
CS
SCK
SI
SO
WP
RESET
V
CC
GND
will not be accepted on the input pin (SI). A high-to-low transition on the CS
transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP independently of the software controlled protection method. After the WP pin goes low, the content of the Sector Protection Register cannot be modified.
If a program or erase command is issued to the device while the WP will simply ignore the command and perform no operation. The device will return to the idle state once the CS Lockdown command, however, will be recognized by the device when the WP pin is asserted.
The WP not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET that the RESET pin be driven high externally.
Device Power Supply: The VCC pin is used to supply the source voltage to the device. Operations at invalid V
Ground: The ground reference for the power supply. GND should be connected to the system ground.
pin has been deasserted. The Enable Sector Protection command and Sector
pin is internally pulled-high and may be left floating if hardware controlled protection will
pin during power-on sequences. If this pin and feature are not utilized it is recommended
pin is required to start an operation, and a low-to-high
pin functions
pin is asserted, the device
pin. Normal operation can resume once the RESET pin is
voltages may produce spurious results and should not be attempted.
CC
AT45DB081D
Asserted
State Type
Low Input
Input
Input
Output
Low Input
Low Input
–Power
Ground
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3

3. Block Diagram

WP
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER 2 (256/264 BYTES)BUFFER 1 (256/264 BYTES)
SCK
CS
I/O INTERFACE
RESET
VCC
GND
SOSI

4. Memory Array

To provide optimal flexibility, the memory array of the AT45DB081D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
SECTOR 0a = 8 Pages
2,048/2,112 bytes
SECTOR 0b = 248 Pages
63,488/65,472 bytes
SECTOR 1 = 256 Pages
65,536/67,584 bytes
SECTOR 2 = 256 Pages
65,536/67,584 bytes
SECTOR 14 = 256 Pages
65,536/67,584 bytes
SECTOR 15 = 256 Pages
65,536/67,584 bytes
SECTOR 0a
SECTOR 0b
SECTOR 1
BLOCK 510
BLOCK 511
Block = 2,048/2,112 bytes
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
8 Pages
BLOCK 0
BLOCK 1
PAG E 0
PAG E 1
PAG E 6
PAG E 7
PAG E 8
PAG E 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAG E 1 8
PAGE 4,094
PAGE 4,095
Page = 256/264 bytes
4
AT45DB081D
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5. Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-7 on
page 31. A valid instruction starts with the falling edge of CS
opcode and the desired buffer or main memory address location. While the CS gling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are trans­ferred with the most significant bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the datasheet using the terminology BFA8 - BFA0 to denote the 9 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA11 - PA0 and BA8 - BA0, where PA11 - PA0 denotes the 12 address bits required to desig­nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte address within the page.
For “Power of 2” binary page size (256 bytes) the Buffer addressing is referenced in the datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology A19 - A0, where A19 - A8 denotes the 12 address bits required to desig­nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte address within a page.
AT45DB081D
followed by the appropriate 8-bit
pin is low, tog-

6. Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode.

6.1 Continuous Array Read (Legacy Command: E8H): Up to 66 MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read from the DataFlash standard page size (264 bytes), an opcode of E8H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the main mem­ory array to read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence specify the starting byte address within the page. To perform a continuous read from the binary page size (256 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes and 4 don’t care bytes. The first 12 bits (A19 - A8) of the 20-bits sequence specify which page of the main memory array to read, and the last 8 bits (A7 - A0) of the 20-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
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The CS bytes, and the reading of data. When the end of a page in main memory is reached during a
pin must remain low during the loading of the opcode, the address bytes, the don’t care
5
Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with cross­ing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS
pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f
specification. The Continuous Array Read bypasses both data buffers and leaves the
CAR1
contents of the buffers unchanged.

6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz

This command can be used with the serial interface to read the main memory array sequentially in high speed mode for any clock frequency up to the maximum specified by f continuous read array with the page size set to 264 bytes, the CS opcode 0BH must be clocked into the device followed by three address bytes and a dummy byte. The first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the main memory array to read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence spec­ify the starting byte address within the page. To perform a continuous read with the page size set to 256 bytes, the opcode, 0BH, must be clocked into the device followed by three address bytes (A19 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read­ing of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will con­tinue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f
specification. The Continuous Array Read bypasses both
CAR1
data buffers and leaves the contents of the buffers unchanged.
must first be asserted then an
. To perform a
CAR1

6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz

This command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to maximum frequencies specified by f read array with the page size set to 264 bytes, the CS
must first be asserted then an opcode, 03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). The first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the main memory array to read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence specify the starting byte address within the page. To perform a contin­uous read with the page size set to 256 bytes, the opcode, 03H, must be clocked into the device followed by three address bytes (A19 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read­ing of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred
6
AT45DB081D
CAR2
. To perform a continuous
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during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will con­tinue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.4 Main Memory Page Read

A main memory page read allows the user to read data directly from any one of the 4,096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the DataFlash standard page size (264 bytes), an opcode of D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The first 12 bits (PA11 - PA0) of the 21-bit address sequence specify the page in main memory to be read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence specify the starting byte address within that page. To start a page read from the binary page size (256 bytes), the opcode D2H must be clocked into the device followed by three address bytes and 4 don’t care bytes. The first 12 bits (A19 - A8) of the 20-bits sequence specify which page of the main memory array to read, and the last 8 bits (A7 - A0) of the 20-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are sent to initialize the read opera­tion. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output) pin. The CS address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS (SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the f
specification. The Main Memory Page Read bypasses both data buffers and leaves the con-
SCK
tents of the buffers unchanged.
AT45DB081D
pin must remain low during the loading of the opcode, the
pin will terminate the read operation and tri-state the output pin

6.5 Buffer Read

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The SRAM data buffers can be accessed independently from the main memory array, and utiliz­ing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to the maximum specified by f read operations up to the maximum specified by f
To perform a buffer read from the standard DataFlash buffer (264 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 don’t care bits and 9 buffer address bits (BFA8 - BFA0). To perform a buffer read from the binary buffer (256 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one don’t care byte must be clocked in to initialize the read operation. The CS during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS the output pin (SO).
. The D1H and D3H opcode can be used for lower frequency
CAR1
.
CAR2
pin must remain low
pin will terminate the read operation and tri-state
7

7. Program and Erase Commands

7.1 Buffer Write

Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the standard DataFlash buffer (264 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits and 9 buffer address bits (BFA8 - BFA0). The 9 buffer address bits specify the first byte in the buffer to be written. To load data into the binary buffers (256 bytes each), a 1-byte opcode 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). The 8 buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will con­tinue to be loaded into the buffer until a low-to-high transition is detected on the CS

7.2 Buffer to Main Memory Page Program with Built-in Erase

Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the DataFlash standard page size (264 bytes), the opcode must be followed by three address bytes consist of 3 don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written and 9 don’t care bits. To perform a buffer to main memory page program with built-in erase for the binary page size (256 bytes), the opcode 83H for buffer 1 or 86H for buffer 2, must be clocked into the device followed by three address bytes consisting of 4 don’t care bits 12 page address bits (A19 - A8) that specify the page in the main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t the status register will indicate that the part is busy.
pin.
pin, the part will first erase the
. During this time,
EP

7.3 Buffer to Main Memory Page Program without Built-in Erase

A previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device. For the DataFlash standard page size (264 bytes), the opcode must be followed by three address bytes consist of 3 don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written and 9 don’t care bits. To perform a buffer to main memory page program without built-in erase for the binary page size (256 bytes), the opcode 88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address bytes consisting of 4 don’t care bits, 12 page address bits (A19 - A8) that specify the page in the main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main mem­ory. It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register will indicate that the part is busy.
8
AT45DB081D
. During this time, the
P
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7.4 Page Erase

7.5 Block Erase

AT45DB081D
The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the DataFlash standard page size (264 bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of 3 don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be erased and 9 don’t care bits. To perform a page erase in the binary page size (256 bytes), the opcode 81H must be loaded into the device, followed by three address bytes consist of 4 don’t care bits, 12 page address bits (A19 - A8) that specify the page in the main memory to be erased and 8 don’t care bits. When a low-to-high transition occurs on the CS state is a logical 1). The erase operation is internally self-timed and should take place in a maxi­mum time of t
. During this time, the status register will indicate that the part is busy.
PE
A block of eight pages can be erased at one time. This command is useful when large amounts of data has to be written into the device. This will avoid using multiple Page Erase Commands. To perform a block erase for the DataFlash standard page size (264 bytes), an opcode of 50H must be loaded into the device, followed by three address bytes comprised of 3 don’t care bits, 9 page address bits (PA11 -PA3) and 12 don’t care bits. The 9 page address bits are used to specify which block of eight pages is to be erased. To perform a block erase for the binary page size (256 bytes), the opcode 50H must be loaded into the device, followed by three address bytes consisting of 4 don’t care bits, 9 page address bits (A19 - A11) and 11 don’t care bits. The 9 page address bits are used to specify which block of eight pages is to be erased. When a low­to-high transition occurs on the CS erase operation is internally self-timed and should take place in a maximum time of t this time, the status register will indicate that the part is busy.
pin, the part will erase the selected page (the erased
pin, the part will erase the selected block of eight pages. The
. During
BE
Table 7-1. Block Erase Addressing
PA1 1/
A19
PA1 0/
A18
000000000XXX 0
000000001XXX 1
000000010XXX 2
000000011XXX 3
111111100XXX 508
111111101XXX 509
111111110XXX 510
111111111XXX 511
PA 9/
A17
PA8 /
A16
PA7 /
A15
PA6 /
A14
PA5 /
A13
PA4 /
A12
PA3 /
A11
PA2 /
A10
PA1 /
A9
PA0 /
A8 Block
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9

7.6 Sector Erase

The Sector Erase command can be used to individually erase any sector in the main memory. There are 16 sectors and only one sector can be erased at one time. To perform sector 0a or sector 0b erase for the DataFlash standard page size (264 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 3 don’t care bits, 9 page address bits (PA11 - PA3) and 12 don’t care bits. To perform a sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of 3 don’t care bits, 4 page address bits (PA11 - PA8) and 17 don’t care bits. To perform sector 0a or sector 0b erase for the binary page size (256 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 4 don’t care bit and 9 page address bits (A19 - A11) and 11 don’t care bits. To perform a sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of 4 don’t care bit and 4 page address bits (A19 - A16) and 16 don’t care bits. The page address bits are used to specify any valid address location within the sector which is to be erased. When a low-to-high transition occurs on the CS self-timed and should take place in a maximum time of t will indicate that the part is busy.
Table 7-2. Sector Erase Addressing
pin, the part will erase the selected sector. The erase operation is internally
. During this time, the status register
SE
PA1 1/
A19
PA1 0/
A18
000000000XXX 0a
000000001XXX 0b
0001XXXXXXXX 1
0010XXXXXXXX 2
1100XXXXXXXX 12
1101XXXXXXXX 13
1110XXXXXXXX 14
1111XXXXXXXX 15
PA 9/
A17
PA8 /
A16
PA7 /
A15
PA6 /
A14
PA5 /
A13
PA4 /
A12
PA3 /
A11
PA 2/
A10
PA1 /
A9
PA0 /
A8 Sector

7.7 Chip Erase

The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS serted to start the erase process. The erase operation is internally self-timed and should take place in a time of t
. During this time, the Status Register will indicate that the device is busy.
CE
The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased.
pin can be deas-
10
AT45DB081D
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AT45DB081D
The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes.
Command Byte 1 Byte 2 Byte 3 Byte 4
Chip Erase C7H 94H 80H 9AH
Figure 7-1. Chip Erase
CS
SI
Each transition represents 8 bits
Note: Refer to errata regarding Chip Erase on page 52.
Opcode
Byte 1

7.8 Main Memory Page Program Through Buffer

This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a specified page in the main memory. To perform a main memory page program through buffer for the DataFlash standard page size (264 bytes), a 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of 3 don’t care bits, 12 page address bits, (PA11 - PA0) that select the page in the main memory where data is to be written, and 9 buffer address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a main memory page program through buffer for the binary page size (256 bytes), the opcode 82H for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytes consisting of 4 don’t care bits, 12 page address bits (A19 - A8) that specify the page in the main memory to be written, and 8 buffer address bits (BFA7 - BFA0) that selects the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t the status register will indicate that the part is busy.
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
. During this time,
EP

8. Sector Protection

Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware con­trolled method employs the use of the Write Protect (WP that are to be protected or unprotected against program and erase operations is specified in the nonvolatile Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter­mined by checking the Status Register.
3596F–DFLASH–8/07
) pin. The selection of which sectors
11

8.1 Software Sector Protection

8.1.1 Enable Sector Protection Command

Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection using the software controlled method, the CS with any other command. Once the CS sequence must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS enabled.
Command Byte 1 Byte 2 Byte 3 Byte 4
Enable Sector Protection 3DH 2AH 7FH A9H
Figure 8-1. Enable Sector Protection
CS
pin must first be asserted as it would be
pin has been asserted, the appropriate 4-byte command
pin must be deasserted after which the sector protection will be
SI

8.1.2 Disable Sector Protection Command

To disable the sector protection using the software controlled method, the CS asserted as it would be with any other command. Once the CS appropriate 4-byte sequence for the Disable Sector Protection command must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS must be deasserted after which the sector protection will be disabled. The WP deasserted state; otherwise, the Disable Sector Protection command will be ignored.
Command Byte 1 Byte 2 Byte 3 Byte 4
Disable Sector Protection 3DH 2AH 7FH 9AH
Figure 8-2. Disable Sector Protection
CS
SI
Opcode
Byte 1
Each transition represents 8 bits
Opcode
Byte 1
Each transition represents 8 bits
Opcode
Byte 2
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 3
Opcode
Byte 4
pin must first be
pin has been asserted, the
pin must be in the
Opcode
Byte 4
pin

8.1.3 Various Aspects About Software Controlled Protection

Software controlled protection is useful in applications in which the WP controlled by a host processor. In such instances, the WP internally pulled high) and sector protection can be controlled using the Enable Sector Protection and Disable Sector Protection commands.
If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro-
12
tection is desired and if the WP
AT45DB081D
pin is not used.
pin is not or cannot be
pin may be left floating (the WP pin is
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9. Hardware Controlled Protection

Sectors specified for protection in the Sector Protection Register and the Sector Protection Reg­ister itself can be protected from program and erase operations by asserting the WP keeping the pin in its asserted state. The Sector Protection Register and any sector specified for protection cannot be erased or reprogrammed as long as the WP modify the Sector Protection Register, the WP nently connected to GND, then the content of the Sector Protection Register cannot be changed. If the WP Protection Register can be modified.
pin is deasserted, or permanently connected to VCC, then the content of the Sector
AT45DB081D
pin and
pin is asserted. In order to
pin must be deasserted. If the WP pin is perma-
The WP
pin will override the software controlled protection method but only for protecting the sectors. For example, if the sectors were not previously protected by the Enable Sector Protec­tion command, then simply asserting the WP maximum specified t
time. When the WP pin is deasserted; however, the sector protection
WPE
would no longer be enabled (after the maximum specified t tor Protection command was not issued while the WP Protection command was issued before or while the WP ing the WP
pin would not disable the sector protection. In this case, the Disable Sector
Protection command would need to be issued while the WP
pin would enable the sector protection within the
time) as long as the Enable Sec-
WPD
pin was asserted. If the Enable Sector
pin was asserted, then simply deassert-
pin is deasserted to disable the sec­tor protection. The Disable Sector Protection command is also ignored whenever the WP asserted.
A noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the WP
pin.
The table below details the sector protection status for various scenarios of the WP Enable Sector Protection command, and the Disable Sector Protection command.
Figure 9-1. WP
Pin and Protection Status
12
3
WP
Table 9-1. WP Pin and Protection Status
Time
Period WP Pin
1High
2 Low X X Enabled Read Only
3High
Enable Sector Protection
Command
Command Not Issued Previously
Issue Command
Command Issued During Period 1
or 2
Issue Command
Disable Sector
Protection Command
X
Issue Command
Not Issued Yet
Issue Command
Sector Protection
Status
Disabled Disabled
Enabled
Enabled
Disabled
Enabled
pin is
pin, the
Sector
Protection
Register
Read/Write Read/Write Read/Write
Read/Write Read/Write Read/Write
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13

9.1 Sector Protection Register

The nonvolatile Sector Protection Register specifies which sectors are to be protected or unpro­tected with either the software or hardware controlled protection methods. The Sector Protection Register contains 16 bytes of data, of which byte locations 0 through 15 contain values that specify whether sectors 0 through 15 will be protected or unprotected. The Sector Protection Register is user modifiable and must first be erased before it can be reprogrammed. Table 9-3 illustrates the format of the Sector Protection Register.:
Table 9-2. Sector Protection Register
Sector Number 0 (0a, 0b) 1 to 15
Protected
Unprotected 00H
Table 9-3. Sector 0 (0a, 0b)
Sectors 0a, 0b Unprotected 00 00 xx xx 0xH
Protect Sector 0a 11 00 xx xx CxH
Protect Sector 0b (Page 8-255) 00 11 xx xx 3xH
See Table 9-3
0a 0b
(Page 0-7) (Page 8-255)
Bit 7, 6 Bit 5, 4 Bit 1, 0
Bit 3, 2
FFH
Data
Val ue
Protect Sectors 0a (Page 0-7), 0b (Page 8-255)
Note: 1. The default value for bytes 0 through 15 when shipped from Atmel® is 00H.
(1)
x = don’t care.
11 11 xx xx FxH
14
AT45DB081D
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9.1.1 Erase Sector Protection Register Command

In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command.
AT45DB081D
To erase the Sector Protection Register, the CS any other command. Once the CS
pin has been asserted, the appropriate 4-byte opcode
pin must first be asserted as it would be with
sequence must be clocked into the device via the SI pin. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and CFH. After the last bit of the opcode sequence has been clocked in, the CS cycle. The erasing of the Sector Protection Register should take place in a time of t
pin must be deasserted to initiate the internally self-timed erase
, during
PE
which time the Status Register will indicate that the device is busy. If the device is powered­down before the completion of the erase cycle, then the contents of the Sector Protection Regis­ter cannot be guaranteed.
The Sector Protection Register can be erased with the sector protection enabled or disabled. Since the erased state (FFH) of each byte in the Sector Protection Register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. If for some reason an erroneous program or erase com­mand is sent to the device immediately after erasing the Sector Protection Register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected.
Command Byte 1 Byte 2 Byte 3 Byte 4
Erase Sector Protection Register 3DH 2AH 7FH CFH
Figure 9-2. Erase Sector Protection Register
CS
SI
Opcode
Byte 1
Each transition represents 8 bits
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
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15

9.1.2 Program Sector Protection Register Command

Once the Sector Protection Register has been erased, it can be reprogrammed using the Pro­gram Sector Protection Register command.
To program the Sector Protection Register, the CS
pin must first be asserted and the appropri­ate 4-byte opcode sequence must be clocked into the device via the SI pin. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and FCH. After the last bit of the opcode sequence has been clocked into the device, the data for the contents of the Sector Protection Register must be clocked in. As described in Section 9.1, the Sector Protection Reg- ister contains 16 bytes of data, so 16 bytes must be clocked into the device. The first byte of data corresponds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data corresponding to sector 15.
After the last data byte has been clocked in, the CS
pin must be deasserted to initiate the inter­nally self-timed program cycle. The programming of the Sector Protection Register should take place in a time of t
, during which time the Status Register will indicate that the device is busy. If
P
the device is powered-down during the program cycle, then the contents of the Sector Protection Register cannot be guaranteed.
If the proper number of data bytes is not clocked in before the CS
pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed. For example, if only the first two bytes are clocked in instead of the complete 16 bytes, then the protection status of the last 14 sectors cannot be guaranteed. Furthermore, if more than 16 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if 17 bytes of data are clocked in, then the 17th byte will be stored at byte location 0 of the Sector Protection Register.
If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to that byte location cannot be guaran­teed. For example, if a value of 17H is clocked into byte location 2 of the Sector Protection Register, then the protection status of sector 2 cannot be guaranteed.
The Sector Protection Register can be reprogrammed while the sector protection enabled or dis­abled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than dis­abling sector protection completely.
The Program Sector Protection Register command utilizes the internal SRAM buffer 1 for pro­cessing. Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued.
Command Byte 1 Byte 2 Byte 3 Byte 4
Program Sector Protection Register 3DH 2AH 7FH FCH
Figure 9-3. Program Sector Protection Register
CS
16
SI
Each transition represents 8 bits
Opcode
Byte 1
AT45DB081D
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Data Byte
n
Data Byte
n + 1
Data Byte
n + 15
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