ATMEL AT45DB041-TI, AT45DB041-TC, AT45DB041-RI, AT45DB041-RC, AT45DB041-JI Datasheet
...
Features
•
Single 2.7V - 3.6V Supply
•
Serial Interface Arch itec ture
•
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Pages (264 Bytes/Page) Main Memory
•
Two 264-Byte SRAM Data Buffers – Allows Receiving of Data
While Reprogramming of Non-Volatile Memory
•
Internal Program and Control Timer
•
Fast Page Program Time – 7 ms Typical
µµµµ
•
120
s Typical Page to Buffer Transfer Time
•
Low Power Dissipation
– 4 mA Active Read Current Typical
µµµµ
–8
A CMOS Standby Current Typical
•
5 MHz Max Clock Frequency
•
Hardware Data Protection Feature
•
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
•
CMOS and TTL Compatible Inputs and Outputs
•
Commercial and Industrial Temperature Ranges
4-Megabit
2.7-volt Only
Serial
DataFlash
®
Description
The AT45DB041 is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of
264-bytes each. In addition to the main me mory, the AT45DB041 also contains two
SRAM data buffers of 264-bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface,
the DataFlash uses a serial interface to sequentially access its data. The simple serial
interface facilitates hardware layout, increases system reliability, minimizes switching
Pin Configurations
Pin Name Function
CS
SCK Serial Clock
SI Serial Input
SO Serial Output
WP
RESET
RDY/BUSY
RDY/BUSY
RESET
WP
VCC
GND
SCK
Chip Select
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
1
2
3
4
NC
5
NC
6
7
8
NC
9
NC
10
NC
11
CS
12
13
SI
14
SO
TSOP Top View
Type 1
SCK
SI
SO
NC
NC
NC
NC
NC
NC
Note: PLCC package pins 16
and 17 are DON’T CONNECT.
PLCC
CSNCNC
GND
432
5
6
7
8
9
10
11
12
13
1
14151617181920
NCNCDCDCNCNCNC
28
NC
27
NC
26
NC
25
NC
24
NC
23
NC
22
NC
21
NC
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
VCCNCNC
323130
29
28
27
26
25
24
23
22
21
GND
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
SCK
NC
CS
SO
NC
NC
NC
NC
NC
NC
NC
CBGA Top View
Through Package
1
A
B
NC
C
NC
D
NC
E
NC
SI
2345
NC
SCK
CS
SO
NC
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
GND
RDY/BSY
SI
NC
RESET
(continued)
28
VCC
27
NC
26
NC
25
WP
24
RESET
23
RDY/BUSY
22
NC
21
NC
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
NC
NC
NC
VCC
NC
WP
NC
NC
NC
AT45DB041
Rev. 0669D–07/98
1
noise, and reduces p ac ka ge si ze and active pin count. The
device is optimized for use i n many comm ercial and i ndustrial applications where high density, low pin count, low
voltage, and low power are essential. Typical applications
for the DataFlash are digital voice storage, image storage,
and data storage. The device operates at clock frequencies
up to 5 MHz with a typic al act ive read curr ent co nsump tion
of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB041 does not require high input voltages for pro-
Block Diagram
gramming. The devi ce operate s from a s ingle po wer supply, 2.7V to 3.6V, for both the program and read
operations. The AT45DB041 is enabled through the chip
select pin (CS
) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
WP
PAGE (264 BYTES)
SCK
CS
RESET
V
CC
GND
RDY/BUSY
Device Operation
The device operation is controlled by instructions from the
host processor. The l is t o f in st ru cti on s a nd thei r as so ci ated
opcodes are contained in T able 1 and Table 2. A valid
instruction starts with the falling edge of CS
appropriate 8-bit opcode and the desired buffer or main
memory address loc ati on. Whi le the CS
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ:
the user to read data directly from any one of the 2048
pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits . In the AT45DB 041, the
first four address bits are reserved for larger density
devices (see Notes on page 8), the next 11 address bits
A main memory read allows
followed by the
pin is low, toggl in g
FLASH MEMORY ARRAY
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
SOSI
(PA10-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS
pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same pag e. A l ow to hig h trans i tion on th e
pin will terminate the read operation and tri-state the
CS
SO pin.
BUFFER READ:
Data can be re ad from ei ther one of the
two buffers, usin g di fferen t o pc ode s to s pe cify wh ic h bu ffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perfo rm a buffer read, the eight bits o f the
opcode must be followed by 15 don’t care bits, nine
address bits, and eight don't care bits. Since the buffer size
is 264-bytes, nine address bits (BFA8-BFA0) are require d
to specify the first byte of data to b e read fr om the buffer.
2
AT45DB041
AT45DB041
The CS
pin must remain low during the loading of the
opcode, the address bits, t he don ’t care bi ts, an d the reading of data. When the end of a buffer is reached, the device
will continue reading back at the beginning of the buffer. A
low to high transition on the CS
pin will terminate the read
operation and tri-state the SO pin.
MAIN MEMORY PAGE TO BUFFER TRANSFER:
A page
of data can be transferred from the main memory to either
buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and
55H for buffer 2, is followed by the four reserved bits, 11
address bits (PA10-PA0) which specify the page in main
memory that is to be transferred, and nine don’t care bits.
The CS
pin must be low while to ggling the SCK pin to loa d
the opcode, the address bit s, and the don ’t care bits from
the SI pin. The transfer of the page of data from the main
memory to the buffer will begin when the CS
pin transitions
from a low to a high state. During the transfer of a page of
data (t
), the status register can be read to determin e
XFR
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE:
A page of
data in main memory can be compared to the data in buffer
1 or buffer 2. An 8-bit opcode , 60 H for bu ffer 1 and 61H for
buffer 2, is followed b y 24 address bits consisting of the
four reserved bits, 11 address bits (PA10-PA0) which specify the page in the main memory that is to be compared to
the buffer, and nine don't care bits. The loading of the
opcode and the address bits is the same as describ ed previously. The CS
pin must be low while toggling the SCK pin
to load the opcode, the address bits, and the don't care bits
from the SI pin. On t he low to high transi tion of the CS
pin,
the 264 bytes in the selected main memory page will be
compared with the 264 bytes in bu ffer 1 or buffer 2. Durin g
this time (t
), the status register will indicate that the part
XFR
is busy. On compl etion of t he com pare operat ion, b it 6 o f
the status register is updated with the result of the compare.
Program
BUFFER WRITE:
into either buffer 1 or bu ffer 2. To load data into ei ther
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
is followed by 15 don't care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in
the buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the
device will wrap around back to the beginning of the buffer.
Data will continue to be l oaded i nto the b uffer unti l a low t o
high transition is detected on the CS
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE:
2 can be programmed into the main memory. An 8-bit
opcode, 83H for buf fer 1 o r 86 H for buff er 2, is f ollow ed by
the four reserved bits, 11 address bits (PA10-PA0) that
specify the page in the main memory to be written, and
Data can be shif ted in from the SI pi n
pin.
Data written into either buff er 1 or bu ffer
nine additional don't care bits. When a low to high transition
occurs on the CS
pin, the part will first erase the selec ted
page in main memory to all 1s and then program the data
stored in the buffer in to the specified page i n the main
memory. Both th e erase an d the pr ogrammi ng of the p age
are internally self timed and should take place in a maximum time of t
. During this time, the status register will
EP
indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE:
A previously erased page within
main memory can be p rogrammed with the conten ts of
either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1
or 89H for buffer 2, is follow ed by the four res er ved bi ts, 11
address bits (PA10-PA0) that specify the page in the main
memory to be writ ten, an d nine addi tional don’t c are bits.
When a low to high transition occurs on the CS
pin, the part
will program the data stored in the buffer into the specified
page in the main memory. It is necessary that the page in
main memory that is being programmed has been previously programmed to all 1s (erased state). The programming of the page is internally se lf timed and should tak e
place in a maximum time of t
. During this tim e, the s tatus
P
register will indicate that the part is busy.
MAIN MEMORY PAGE PROGRAM:
This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations . Data is fi rst
shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. An 8bit opcode, 82H f or buff er 1 or 85 H for b uffer 2, is foll owed
by the four reserved bits and 20 add ress bits. The 11 mos t
significant address bits (PA10-PA0) select the page in the
main memory where data is to be written, and the next nine
address bits (BFA8-BFA0) select the first byte in the bu ffer
to be written. After all address bits are shifted in, the part
will take data from the SI pin and st ore it in one of the da ta
buffers. If the end of the b uffer i s reache d, the de vice wil l
wrap around back to the beginning of the buffer. W hen
there is a low to high transition on the CS
pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the programming of the page are internally self timed and should take
place in a maximum of tim e t
. During this time, the status
EP
register will indicate that the part is busy.
AUTO PAGE REWRITE:
This mode is only needed if mul tiple bytes within a page or m ultiple pa ges of dat a are mod ified in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data i s fir st tran sferred from the mai n me mory to
buffer 1 or buffer 2, and then the same data (from buffer 1
or buffer 2) is progr ammed back i nto its origi nal page of
main memory. An 8-bit op code, 58H for buffer 1 or 59H for
buffer 2, is foll owed by the four r eserved bits, 11 address
3
bits (PA10-PA0) tha t specify the page in mai n memory to
be rewritten, and nine additional don't care b its. When a
low to high transition occurs on the CS
transfer data from the page in main memory to a buffer and
then program the data from the buffer back into same page
of main memory. Th e operati on is int ernall y self-ti med and
should take place in a maximum time of t
time, the status register will indicate that the part is busy.
If the main memory is programmed or reprogrammed
sequentially page by page, then the programming algorithm shown in Figure 1 is recommended. Otherwise, if
multiple bytes in a page or sever al pages are progr ammed
randomly in the main memory, then the prog ramming algorithm shown in Figure 2 is recommended.
STATUS REGISTER:
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compa re operation, or the
device density. To read the status register, an opcode of
57H must be loaded int o th e de vi c e. A fter the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cy cles . The five most-significant bits of the status register will contain devic e information, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will rep eat itse lf (a s lo ng as CS
SCK is being toggled ) startin g again with bit 7. The data i n
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1 , the n th e dev i ce is not bus y a nd i s ready
to accept the next comman d. If bit 7 i s a 0, then the devic e
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be outpu t on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are six operations which can
cause the device to be in a busy s ta te: Main Memory Pag e
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-In Erase,
Buffer to Main Memory Page Program without Built-In
Erase, Main Memory Page Program, and Auto Page
Rewrite.
The result of the mos t recent Ma in Memor y Page to B uffer
Compare opera tion is indic ated using bi t 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
The status register can be used to
pin, the part will first
. During this
EP
remains low an d
least one bit of the data in the main memory page does not
match the data in the buffer.
The device dens it y is ind ic ate d us ing b its 5 , 4, and 3 of th e
status register. For the AT45DB041, the three bits ar e 0, 1,
and 1. The decimal value of these three binary bits does
not equate to th e dev ice d ensi ty; th e thre e bit s repr ese nt a
combinational code r elating to d iffering den sities of Ser ial
DataFlash devices, allowing a total of eight different density
configurations.
Read/Program Mode Summary
The modes lis ted abo ve can b e sepa rated into tw o grou ps
— modes which make use of the flash memory array
(Group A) and modes which do no t make use of the flas h
memory array (Group B).
Group A modes consist of:
1. Main memory page read
2. Main memory page to buffer 1 (or 2) transfer
3. Main memory page to buffer 1 (or 2) compare
4. Buffer 1 (or 2) to main memory page program with
built-in erase
5. Buffer 1 (or 2) to main memory page program with-
out built-in erase
6. Main memory page program
7. Auto page rewrite
Group B modes consist of:
1. Buffer 1 (or 2) read
2. Buffer 1 (or 2) write
3. Status read
If a Group A mode is in pro gress ( not full y com pleted) then
another mode in Group A should not be started. However,
during this time in which a Group A mode is in progress,
modes in Group B can be started.
This gives the S erial DataFlash the ability to virtua lly
accommodate a co ntinuous data stre am. While data is
being programmed into main memory from buffer 1, data
can be loaded into buff er 2 (o r vice v ersa) . See applica tio n
note AN-4 (“Using Atmel’s Serial DataFlash”) for more
details.
HARDWARE PAGE WRITE PROTECT:
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first dri ve the prot ect pin high and then us e the
program commands previously mentioned.
If the WP
pin is
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY
4
COMP011XXX
AT45DB041
AT45DB041
RESET
:
A low state on the reset pin (RESET
) will terminate
the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset
condition as long as a low level is pr esent on the RE SET
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The device also in corporates an internal power -on reset
circuit; therefore, there are no restrictions on the RESET
pin during power-on sequences.
READY/BUSY
:
This open dra in output pin will be dri ven
low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during program-
Absolute Maximum Ratings*
Temperature Under Bias................................-55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
+ 0.6V
CC
ming operations, compare operations, and during page-tobuffer transfers.
The busy status indic at es that the Flas h m emo ry a rray an d
one of the buffers cannot be accessed; read and write
operations to the other buffer can still be performed.
Power On/Reset State
When power is first applied to the device, o r w hen re co ve ring from a reset conditio n, the device will defau lt to SPI
mode 3. In addition, the SO pin will be in a high im peda nc e
state, and a high to low transition on the CS
required to start a valid instruction. The SPI mode will be
automatically select ed on ever y falling ed ge of CS
pling the inactive clock state.
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d
functional oper ation of the de vi ce at t hes e or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .
pin will be
by sam-
DC and AC Operating Range
AT45DB041
Operating Temperature (Case)
V
Power S upply
CC
Note: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.
(1)
Com. 0°C to 70°C
Ind. -40°C to 85°C
2.7V to 3.6V
5
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
, RESET, WP = VIH, all input s at
I
SB
Standby Current
CS
CMOS levels
820µA
I
CC1
I
CC2
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Active Current, Read
Operation
Active Current,
Program/Erase Operation
Input Load Current VIN = CMOS levels 1 µA
Output Leakage Current V
Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V
Output High Voltage IOH = -100 µAV
f = 5 MHz; I
= 3.6V 15 35 mA
V
CC
= CMOS levels 1 µA
I/O
= 0 mA; VCC = 3.6V 4 10 mA
OUT
- 0.2V V
CC
AC Characteristics
Symbol Parameter Min T yp Max Units
f
SCK
t
WH
t
WL
t
CS
t
CSS
t
CSH
t
CSB
t
SU
t
H
t
HO
t
DIS
t
V
t
XFR
t
EP
t
P
t
RST
t
REC
SCK Frequency 5MHz
SCK High Time 80 ns
SCK Low Time 80 ns
Minimum CS High Time 350 ns
CS Setup Time 350 ns
CS Hold Time 350 ns
CS High to RDY/BUSY Low 200 ns
Data In Setup Time 15 ns
Data In Hold Time 35 ns
Output Hold Time 0 ns
Output Disa ble Time 100 ns
Output Valid 120 ns
Page to Buffer Transfer/Compare Time 120 250 µs
Page Erase and Programming Time 10 20 ms
Page Programming Time 7 14 ms
RESET Pulse Width 10 µs
RESET Recovery Time 1 µs
Input Test Wavef orms and Measurement Levels
2.4V
AC
DRIVING
LEVELS
0.45V
tR, tF < 20 ns (10% to 90%)
6
AT45DB041
AC
2.0
MEASUREMENT
0.8
LEVEL
Output Test Load
DEVICE
UNDER
TEST
30 pF
Loading...