ATMEL AT45DB011B User Manual
Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
• 20 MHz Max Clock Frequency
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
• Supports Page and Block Erase Operations
• One 264-byte SRAM Data Buffer
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• Hardware Data Protection Feature
• 100% Compatible with AT45DB011
• Commercial and Industrial Temperature Ranges
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Description
The AT45DB011B is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addition to the main memory, the AT45DB011B also contains one SRAM data buffer of 264
bytes. The buffer allows receiving of data while a page in the main memory is being
reprogrammed. EEPROM emulation (bit or byte alterability) is easily handled with a
self-contained three step Read-Modify-Write operation. Unlike conventional Flash
memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI serial interface to sequentially access its data. SPI
mode 0 and mode 3 are supported. The simple serial interface facilitates hardware
1-megabit
2.7-volt Only
DataFlash
®
AT45DB011B
Pin Configurations
Pin Name Function
SOIC
1
SI
2
3
4
Chip Select
Write Protect Pin
Chip Reset
Ready/Busy
SO
8
GND
7
VCC
6
WP
5
CS
SCK Serial Clock
SI Serial Input
SO Serial Output
WP Hardware Page
RESET
RDY/BUSY
SCK
RESET
CS
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
CBGA Top View
through Package
123
A
B
C
SCK
CS
SO
GND
RDY/BSY
SI
TSSOP Top View
Typ e 1
1
2
3
4
5
6
7
VCC
WP
RESET
AT45DB011B
Preliminary 16Megabit 2.7-volt
Only Serial
DataFlash
14
CS
13
NC
12
NC
11
NC
10
NC
9
NC
8
SI
Rev. 1984I–DFLSH–9/7/05
1
Block Diagram
layout, increases system reliability, minimizes switching noise, and reduces package size and
active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. The device
operates at clock frequencies up to 20 MHz with a typical active read current consumption of
4mA.
To allow for simple in-system reprogrammability, the AT45DB011B does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB011B is enabled through the chip select
pin (CS
) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Out-
put (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array may
not be erased. In other words, the contents of the last page may not be filled with FFH.
Memory Array
WP
PAGE (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
FLASH MEMORY ARRAY
BUFFER (264 BYTES)
I/O INTERFACE
SOSI
To provide optimal flexibility, the memory array of the AT45DB011B is divided into three levels
of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram
illustrates the breakdown of each level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page by page basis; however, the optional
erase operations can be performed at the block or page level.
2
AT45DB011B
1984I–DFLSH–9/7/05
Memory Architecture Diagram
AT45DB011B
SECTOR ARCHITECTURE
SECTOR 0 = 2112 BYTES (2K + 64)
SECTOR 1 = 65,472 BYTES (62K + 1984)
SECTOR 2 = 67,584 BYTES (64K + 2K)
SECTOR 0
BLOCK ARCHITECTURE PAGE ARCHITECTURE
8 Pages
BLOCK 0
BLOCK 1
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 509
PAGE 510
PAGE 511
Page = 264 bytes
SECTOR 1SECTOR 2
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
BLOCK 29
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 34
BLOCK 61
BLOCK 62
BLOCK 63
Block = 2112 bytes
(2K + 64)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
(256 + 8)
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4 (pages 11 and 12). A
valid instruction starts with the falling edge of CS
the desired buffer or main memory address location. While the CS
followed by the appropriate 8-bit opcode and
pin is low, toggling the SCK
pin controls the loading of the opcode and the desired buffer or main memory address location
through the SI (serial input) pin. All instructions, addresses, and data are transferred with the
most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA8-PA0 and BA8-BA0 where PA8-PA0
denotes the 10 address bits required to designate a page address and BA8-BA0 denotes the
nine address bits required to designate a byte address within the page.
Read Commands By specifying the appropriate opcode, data can be read from the main memory or from the
data buffer. The DataFlash supports two categories of read modes in relation to the SCK signal. The differences between the modes are in respect to the inactive state of the SCK signal
as well as which clock cycle data will begin to be output. The two categories, which are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock Polarity
High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 1 on page 11 for a
complete list) is used to select which category will be used for reading. Please refer to the
“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle
sequences for each mode.
1984I–DFLSH–9/7/05
3
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a
continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24
address bits and 32 don’t care bits. The first six bits of the 24-bit address sequence are
reserved for upward and downward compatibility to larger and smaller density devices (see
Notes under “Command Sequence for Read/Write Operations” diagram). The next nine
address bits (PA8-PA0) specify which page of the main memory array to read, and the last
nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte address within
the page. The 32 don’t care bits that follow the 24 address bits are needed to initialize the read
operation. Following the 32 don’t care bits, additional clock pulses on the SCK pin will result in
serial data being output on the SO (serial output) pin.
The CS
bits, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one
page to the beginning of the next page). When the last bit in the main memory array has been
read, the device will continue reading back at the beginning of the first page of memory. As
with crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to-high transition on the CS
The maximum SCK frequency allowable for the Continuous Array Read is defined by the f
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from
any one of the 512 pages in the main memory, bypassing the data buffer and leaving the contents of the buffer unchanged. To start a page read, the 8-bit opcode, 52H or D2H, must be
clocked into the device followed by 24 address bits and 32 don’t care bits. In the
AT45DB011B, the first six address bits are reserved for larger density devices (see Notes on
page 15), the next nine address bits (PA8- PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care
bits which follow the 24 address bits are sent to initialize the read operation. Following the 32
don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial
output) pin. The CS
and the reading of data. When the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the beginning of the same page. A lowto-high transition on the CS
pin must remain low during the loading of the opcode, the address bits, the don’t care
pin will terminate the read operation and tri-state the SO pin.
CAR
pin must remain low during the loading of the opcode, the address bits,
pin will terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from the data buffer using an opcode of 54H or D4H. To
perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine
address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nine address bits
(BFA8- BFA0) are required to specify the first byte of data to be read from the buffer. The CS
pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and
the reading of data. When the end of the buffer is reached, the device will continue reading
back at the beginning of the buffer. A low-to-high transition on the CS
read operation and tri-state the SO pin.
4
AT45DB011B
pin will terminate the
1984I–DFLSH–9/7/05
AT45DB011B
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting
with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The
five most significant bits of the status register will contain device information, while the remaining three least significant bits are reserved for future use and will have undefined values. After
bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS
remains low and SCK is being toggled) starting again with bit 7. The data in the status register
is constantly updated, so each repeating sequence will output new data.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device
is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level
once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and
once the device is no longer busy, the state of SO will change from 0 to 1. There are eight
operations which can cause the device to be in a busy state: Main Memory Page to Buffer
Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with
Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase,
Block Erase, Main Memory Page Program, and Auto Page Rewrite.
COMP0011XX
Program and Erase Commands
The result of the most recent Main Memory Page to Buffer Compare operation is indicated
using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches
the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page
does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB011B, the four bits are 0, 0, 1 and 1. The decimal value of these four binary bits does
not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen different density
configurations.
BUFFER WRITE: Data can be shifted in from the SI pin into the data buffer. To load data into
the buffer, an 8-bit opcode of 84H is followed by 15 don’t care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data
is entered following the address bits. If the end of the data buffer is reached, the device will
wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer
until a low-to-high transition is detected on the CS
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into
the buffer can be programmed into the main memory. An 8-bit opcode of 83H is followed by
the six reserved bits, nine address bits (PA8-PA0) that specify the page in the main memory
to be written, and nine additional don’t care bits. When a low-to-high transition occurs on the
CS
pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self-timed and should take place in a maximum
time of t
. During this time, the status register will indicate that the part is busy.
EP
pin.
1984I–DFLSH–9/7/05
5
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously
erased page within main memory can be programmed with the contents of the buffer. An 8-bit
opcode of 88H is followed by the six reserved bits, nine address bits (PA8-PA0) that specify
the page in the main memory to be written, and nine additional don’t care bits. When a low-tohigh transition occurs on the CS
pin, the part will program the data stored in the buffer into the
specified page in the main memory. It is necessary that the page in main memory that is being
programmed has been previously erased. The programming of the page is internally selftimed and should take place in a maximum time of t
. During this time, the status register will
P
indicate that the part is busy.
Successive page programming operations without doing a page erase are not recommended.
In other words, changing bytes within a page from a “1” to a “0” during multiple page programming operations without erasing that page is not recommended.
PAGE ERASE: The optional Page Erase command can be used to individually erase any
page in the main memory array allowing the Buffer to Main Memory Page Program without
Built-in Erase command to be utilized at a later time. To perform a Page Erase, an opcode of
81H must be loaded into the device, followed by six reserved bits, nine address bits (PA8-
PA0), and nine don’t care bits. The nine address bits are used to specify which page of the
memory array is to be erased. When a low-to-high transition occurs on the CS
pin, the part will
erase the selected page to 1s. The erase operation is internally self-timed and should take
place in a maximum time of t
. During this time, the status register will indicate that the part is
PE
busy.
BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main
Memory Page Program without Built-in Erase command to be utilized to reduce programming
times when writing large amounts of data to the device. To perform a Block Erase, an opcode
of 50H must be loaded into the device, followed by six reserved bits, six address bits (PA8-
PA3), and 12 don’t care bits. The six address bits are used to specify which block of eight
pages is to be erased. When a low-to-high transition occurs on the CS
pin, the part will erase
the selected block of eight pages to 1s. The erase operation is internally self-timed and should
take place in a maximum time of t
. During this time, the status register will indicate that the
BE
part is busy.
Block Erase Addressing
PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Bl oc k
000000XXX0
000001XXX1
000010XXX2
000011XXX3
•
•
•
111100XXX60
111101XXX61
111110XXX62
111111XXX63
6
AT45DB011B
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1984I–DFLSH–9/7/05
•
•
•
AT45DB011B
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of
the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations.
Data is first shifted into the buffer from the SI pin and then programmed into a specified page
in the main memory. An 8-bit opcode of 82H is followed by the six reserved bits and 18
address bits. The nine most significant address bits (PA8-PA0) select the page in the main
memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the
first byte in the buffer to be written. After all address bits are shifted in, the part will take data
from the SI pin and store it in the data buffer. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the
CS
pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and should take place in a maximum of
time t
. During this time, the status register will indicate that the part is busy.
EP
Additional Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the
main memory to buffer. An 8-bit opcode of 53H is followed by the six reserved bits, nine
address bits (PA8-PA0) which specify the page in main memory that is to be transferred, and
nine don’t care bits. The CS
the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from
the main memory to the buffer will begin when the CS
During the transfer of a page of data (t
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in the buffer. An 8-bit opcode of 60H is followed by 24 address bits
consisting of the six reserved bits, nine address bits (PA8-PA0) which specify the page in the
main memory that is to be compared to the buffer, and nine don’t care bits. The loading of the
opcode and the address bits is the same as described previously. The CS
while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from
the SI pin. On the low-to-high transition of the CS
ory page will be compared with the 264 bytes in the buffer. During this time (t
register will indicate that the part is busy. On completion of the compare operation, bit 6 of the
status register is updated with the result of the compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple
pages of data are modified in a random fashion. This mode is a combination of two operations:
Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in
Erase. A page of data is first transferred from the main memory to the data buffer, and then the
same data (from the buffer) is programmed back into its original page of main memory. An 8bit opcode of 58H is followed by the six reserved bits, nine address bits (PA8-PA0) that specify the page in main memory to be rewritten, and nine additional don’t care bits. When a lowto-high transition occurs on the CS
memory to the buffer and then program the data from the buffer back into same page of main
memory. The operation is internally self-timed and should take place in a maximum time of t
During this time, the status register will indicate that the part is busy.
pin must be low while toggling the SCK pin to load the opcode,
pin transitions from a low to a high state.
), the status register can be read to determine
XFR
pin must be low
pin, the 264 bytes in the selected main mem-
), the status
XFR
pin, the part will first transfer data from the page in main
EP
.
1984I–DFLSH–9/7/05
If a sector is programmed or reprogrammed sequentially page by page, then the programming
algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 2 on page 27 is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector.
7
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
+ 0.6V
CC
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT45DB011B
Operating Temperature (Case)
V
Power Supply
CC
Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
(1)
tional mode is started.
Com. 0°C to 70°C
Ind. -40°C to 85°C
2.7V to 3.6V
8
AT45DB011B
1984I–DFLSH–9/7/05
AT45DB011B
Operation Mode Summary
The modes described can be separated into two groups – modes which make use of the Flash
memory array (Group A) and modes which do not make use of the Flash memory array
(Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer Transfer
3. Main Memory Page to Buffer Compare
4. Buffer to Main Memory Page Program with Built-in Erase
5. Buffer to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer Read
2. Buffer Write
3. Status Register Read
If a Group A mode is in progress (not fully completed), then another mode in Group A should
not be started. However, during this time in which a Group A mode is in progress (other than
Main Memory Page Read), Status Register Read from Group B can be started. Furthermore,
during Page Erase and Block Erase operation in progress from Group A, any of the modes
from Group B can be started.
Pin Descriptions SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the device.
The SI pin is used for all data input, including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out from the
device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow of
data to and from the DataFlash. Data is always clocked into the device on the rising edge of
SCK and clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS
not selected, data will not be accepted on the SI pin, and the SO pin will remain in a highimpedance state. A high-to-low transition on the CS
low-to-high transition on the CS
WRITE PROTECT: If the WP
be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect
pin high and then use the program commands previously mentioned. If this pin and feature are
not utilized it is recommended that the WP
): The DataFlash is selected when the CS pin is low. When the device is
pin is required to start an operation, and a
pin is required to end an operation.
pin is held low, the first 256 pages of the main memory cannot
pin be driven high externally.
1984I–DFLSH–9/7/05
9
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset condition
as long as a low level is present on the RESET
RESET
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET
mended that the RESET
pin is brought back to a high level.
pin during power-on sequences. If this pin and feature are not utilized it is recom-
pin be driven high externally.
pin. Normal operation can resume once the
Power-on/Reset State
System Considerations
READY/BUSY
internally self-timed operation. This pin, which is normally in a high state (through a 1kΩ external pull-up resistor), will be pulled low during programming operations, compare operations,
and during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
When power is first applied to the device, or when recovering from a reset condition, the
device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and
a high-to-low transition on the CS
will be automatically selected on every falling edge of CS
After power is applied and V
20 ms before an operational mode is started.
DataFlash is controlled by the Serial Clock (SCK) and Chip Select (CS) pins. These signals
must rise and fall monotonically and be free from noise. Excessive noise or ringing on these
pins can be misinterpreted as multiple edges and cause improper operation of the device. The
PC board traces must be kept to a minimum distance or appropriately terminated. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak currents for DataFlash occur during the programming and erase operations. The peak current during programming or erase of a DataFlash is 70 mA to 80 mA. The
regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.
: This open-drain output pin will be driven low when the device is busy in an
pin will be required to start a valid instruction. The SPI mode
by sampling the inactive clock state.
is at the minimum datasheet value, the system should wait
CC
10
AT45DB011B
1984I–DFLSH–9/7/05
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