ATMEL AT45D041-JC, AT45D041-TI, AT45D041-TC, AT45D041-RI, AT45D041-RC Datasheet
...
Features
•
Single 4.5V - 5.5V Supply
•
Serial Interface Architecture
•
Page Program Operation
- Single Cycle Reprogram (Erase and Program)
- 2048 Pages (264 Bytes/Page) Main Memory
•
Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of
Non-Volatile Memory
•
Internal Program and Control Timer
•
Fast Page Program Time - 7 ms Typical
•
80 µs Typical Page to Buffer Transfer Time
•
Low Power Dissipation
- 15 mA Active Read Current Typical
-20 µA CMOS Standby Current Typical
•
10 MHz Max Clock Frequency
•
Hardware Data Protection Feature
•
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
•
CMOS and TTL Compatible Inputs and Outputs
•
Commercial and Industrial Temperature Ranges
AT45D041
4-Megabit
5-volt Only
Serial
DataFlash
™
Description
The AT45D041 is a 5-volt only, serial interface Flash memory suitable for in-system
reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of 264bytes each. In addition to the main memory, the AT45D041 also contains two data
buffers of 264-bytes each. The buffers allow receiving of data while a page in the main
memory is being reprogrammed. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses a serial interface to sequentially access its data. The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and
(continued)
Pin Configurations
Pin Name Function
CS
SCK Serial Clock
SI Serial Input
SO Serial Output
WP
RESET
RDY/BUSY
Chip Select
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
SCK
SO
NC
NC
NC
NC
NC
NC
Note: PLCC package pins 16
and 17 are DON’T CONNECT.
CSNCNC
432
5
6
SI
7
8
9
10
11
12
13
14151617181920
NCNCDCDCNCNCNC
PLCC
GND
1
VCCNCNC
323130
29
28
27
26
25
24
23
22
21
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
AT45D041
RDY/BUSY
RESET
WP
VCC
GND
SCK
TSOP Top View
Type 1
1
2
3
4
NC
5
NC
6
7
8
NC
9
NC
10
NC
11
CS
12
13
SI
14
SO
28
NC
27
NC
26
NC
25
NC
24
NC
23
NC
22
NC
21
NC
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
GND
SCK
SOIC
1
28
2
NC
3
NC
4
CS
5
6
SI
7
SO
8
NC
9
NC
10
NC
11
NC
12
NC
13
NC
14
NC
VCC
27
NC
26
NC
25
WP
24
RESET
23
RDY/BUSY
22
NC
21
NC
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
0803C-D–6/97
1
reduces package size and active pin count. The device is
optimized for use in many commercial and industrial applications where high densi ty, low pi n count, low vol tage, and
low power are essential. Typical appl ications for the
DataFlash are digital voice storage, image storage, and
data storage. The device operates at clock frequencies up
to 10 Mhz with a typical activ e r ea d cur rent c ons um pti on o f
15 mA.
To allow for simple in-system reprogrammability, the
AT45D041 does not require high input voltages for pro-
Block Diagram
gramming. The device operates from a s ingle powe r supply, 4.5V to 5.5V, for both the program and read operations. The AT45D041 is enabled through the chip select pin
) and accessed via a three-wire interface consisting of
(CS
the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
WP
PAGE (264 BYTES)
SCK
CS
RESET
V
CC
GND
RDY/BUSY
Device Operation
The device operation is controlled by instructions from the
host processor. The l is t of i nst ruc tio ns and th eir associated
opcodes are contain ed in Tab les 1 a nd 2. A valid ins truction starts with the falling edge of CS
priate 8-bit opcode and the desi red buf fer or main memory
address location. While the CS
pin controls the loading of the opcode and the desired
buffer or main memory address location throug h the SI
(serial input) pin. All instructions, addresses, and data are
transferred with the most significant bit (MSB) first.
Read
By specifyin g the approp riate opcode , data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ:
the user to read data directly from any one of the 2048
pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
followed by the appro-
pin is low, toggling the SCK
A main memory r ead al l ows
FLASH MEMORY ARRAY
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
SOSI
address bits and 32 don’t care bits . In the AT45D041, the
first four address bits are reserved for larger density
devices (see Notes on page 7), the next 11 address bits
(PA10-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same page . A l ow to hi gh tr an si tio n on the
pin will terminate the read operation and tri-state the
CS
SO pin.
BUFFER READ:
two buffers, using different opcode s to sp ecify which buffe r
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 5 6H is us ed to read data fr om
pin must remain low during the loading of the
Data can be read from e ither one of the
2
AT45D041
AT45D041
buffer 2. To perform a buffer read, the eig ht bits of the
opcode must be followed by 15 don’t care bits, nine
address bits, and eight don't care bits. Since the buffer size
is 264-bytes, nine address bits (BFA8-BFA0) are required
to specify the first byte of data to be read fr om the buff er.
The CS
pin must remain low during the loading of the
opcode, the address bits, the don’t c are bits, and the reading of data. When the end of a buffer is reached, the device
will continue reading back at the begin ning of the buffe r. A
low to high transition on the CS
pin will terminate the read
operation and tri-state the SO pin.
MAIN MEMORY PAGE TO BUFFER TRANSFER:
A page
of data can be transferred from the main memory to either
buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and
55H for buffer 2, is followed by the four reserved bits, 11
address bits (PA10-PA0) which specify the page in main
memory that is to be transferred, and nine don’t care bits.
The CS
pin must be low while t oggli ng the S CK pin to load
the opcode, the address bi ts, and the d on’t care bits from
the SI pin. The transfer of the page of da ta from the main
memory to the buffer will begin when the CS
pin transitions
from a low to a high state. During the transfer of a page of
data (t
), the status reg ister can be read to deter mine
XFR
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE:
A page
of data in main memory can be compared to the dat a in
buffer 1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and
61H for buffer 2, is followed by 24 address bits consisting of
the four reserv ed bits, 11 add ress bits (P A10-PA0 ) which
specify the page in the main memory that is to be compared to the buf fer, and ni ne do n't care bits. The lo adi ng of
the opcode and the address bits is the same as described
previously. The CS
pin must be low while togg li ng t he S CK
pin to load the opcode , the address bits, and the don't care
bits from the SI pin. On the low to hig h transitio n of the CS
pin, the 264 bytes in the se lected main mem ory page will
be compared with the 264 bytes in buffer 1 or buffer 2. During this time (t
), the status register will indicate that the
XFR
part is busy. On completion of the compare ope ration, bi t 6
of the status register is updated with the result of the compare.
Program
BUFFER WRITE:
into either buffer 1 or bu ffer 2. To load data int o either
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
is followed by 15 don't care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in
the buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the
device will wrap around back to the beginning of the buffer.
Data will continue to be loaded into the buf fer until a low to
high transition is detected on the CS
Data can be shifted in from the SI pin
pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE:
Data written into either buffer 1 or buffer
2 can be programmed into the main memory. An 8-bit
opcode, 83H for buffer 1 or 86H for buffer 2, is fol lowed by
the four reserved bits, 11 address bits (PA10-PA0) that
specify the page in the main memory to be written, and
nine additional don't care bits. When a low to high transition
occurs on the CS
pin, the part will first erase the sele cted
page in main memory to all 1s and then program the data
stored in the buffer in to the specified page in the main
memory. Both the erase an d the pr ogram ming of t he page
are internally self timed and should take place in a maximum time of t
. During this time, the status register will
EP
indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE:
A previously erased page within
main memory can be p rogrammed with the conte nts of
either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1
or 89H for buffer 2, is follow ed by th e fou r res erv ed bi ts, 11
address bits (PA10-PA0) that specify the page in the main
memory to be writt en, and nine ad ditional don’t care bi ts.
When a low to high transition occurs on the CS
pin, the part
will program the data stored in the buffer into the specified
page in the main memory. It is necessary that the page in
main memory that is being programmed has been previously programmed to all 1s (erased state). The programming of the page is internally s elf timed and should take
place in a maximum time of t
. During this time, the status
P
register will indicate that the part is busy.
MAIN MEMORY PAGE PROGRAM:
This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Bu ilt-In Eras e operation s. Data is first
shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. An 8bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed
by the four reserved bits and 20 address bits. Th e 11 most
significant address bits (PA10-PA0) select the page in the
main memory where data is to be written, and the next nine
address bits (BFA8-BFA0) sele ct the first byte in the buffe r
to be written. After all addr ess bits are sh ifted in, the part
will take data from the SI pin and st ore i t in one of the d ata
buffers. If the end of th e buffer i s reache d, the d evice wil l
wrap around back to the beginning of the buffer. W hen
there is a low to high transition on the CS
pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the programming of the page are internally self timed and should take
place in a maximum of tim e t
. During this time, the status
EP
register will indicate that the part is busy.
AUTO PA GE REWRITE:
This mode is only needed if multi ple bytes within a page or multipl e pages of data ar e modi fied in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
3
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first trans ferred from the main memor y to
buffer 1 or bu ffer 2 , and th en the s ame da ta (fr om buff er 1
or buffer 2) is pr ogrammed ba ck into it s origina l page of
main memory. An 8-bi t opco de, 58H for b uffer 1 or 59H f or
buffer 2, is foll owed by the four reserve d bits, 11 addres s
bits (PA10-PA0) that specify the page in main memory to
be rewritten, and nine additional don't care bits . When a
low to high transition occurs on the CS
transfer data from the page in main memory to a buffer and
then program the data from the buffer back into same page
of main memory. The operation is internally self-timed and
should take place in a maximum time of t
time, the status register will indicate that the part is busy.
If the main memory is programmed or reprogrammed
sequentially page by page, then the programming algorithm shown in Figure 1 is recommended. Otherwise, if
multiple bytes in a page or sever al pages are programmed
randomly in the ma in mem ory, then the programming algorithm shown in Figure 2 is recommended.
STAT US REGISTER:
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Comp are operation, or the
device density. To read the status register, an opcode of
57H must be loaded in to the device. After the last bit of the
opcode is shifte d in, the e ight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eigh t cl ock c yc le s. The fiv e mos t-s ign ifi cant bits of the status register will contain device information, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will re peat itse lf (a s long as C S
SCK is being toggled ) startin g again wi th bit 7. The dat a in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is n ot bu sy an d i s rea dy
to accept the next comman d. If bit 7 is a 0, then th e devi ce
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be out put on the SO pin,
and once the devic e is no lo nger busy, the state of SO will
change from 0 to 1. There are six operations which can
cause the device to be in a busy state: Main Me mory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-In Erase,
Buffer to Main Memory Page Program without Built-In
The status register can be used to
pin, the part will first
. During this
EP
remains low and
Erase, Main Memory Page Program, and Auto Page
Rewrite.
The result of the mos t recent Ma in Memo ry Page to Buffer
Compare operation is indicated using bit 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memor y pag e does not
match the data in the buffer.
The device density is indic ated us ing bits 5, 4, an d 3 of the
status register. For the AT45D041, the three bits are 0, 1,
and 1. The decimal value of thes e three bi nary bit s does
not equate to th e dev ice d ensi ty; t he th ree bi ts rep res ent a
combinational code relating to differing densities of Serial
DataFlash devices, allowing a total of eight different density
configurations.
Read/Program Mode Summary
The modes listed above can be separated into two groups
— modes which make use of the flash memory array
(Group A) and modes which do no t make use of the fl ash
memory array (Group B).
Group A modes consist of:
1. Main memory page read
2. Main memory page to buffer 1 (or 2) transfer
3. Main memory page to buffer 1 (or 2) compare
4. Buffer 1 (or 2) to main memory page program with
built-in erase
5. Buffer 1 (or 2) to main memory page program with-
out built-in erase
6. Main memory page program
7. Auto page rewrite
Group B modes consist of:
1. Buffer 1 (or 2) read
2. Buffer 1 (or 2) write
3. Status read
If a Group A mode is in progr ess (not fully co mpleted ) then
another mode in Group A should not be started. However,
during this time in which a Group A mode is in progress,
modes in Group B can be started.
This gives the Serial DataFlash the ability to virtually
accommodate a conti nuous data stream. W hile data is
being programmed into main memory from buffer 1, data
can be loaded into buffer 2 (or vice versa). See application
note AN-4 (“Using Atmel’s Serial DataFlash”) for more
details.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY
4
COMP 0 1 1 X X X
AT45D041
AT45D041
HARDWARE PAGE WRITE PROTECT:
If the WP
pin is
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first dri ve the pro tect pin hig h and then use the
program commands previously mentioned.
RESET
:
A low state on the reset pin (RESET
) will terminate
the operation in progress an d reset the inter nal state
machine to an idle state. The device will remain in the reset
condition as lo ng as a low lev el is prese nt on the RES ET
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
Absolute Maximum Ratings*
Temperature Under Bias ......................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground.........................-0.6V to +6.25V
All Output Voltages
with Respect to Ground...................-0.6V to V
+ 0.6V
CC
The device also incorporates an internal power-on reset circuit; therefore, there are no restrictions on the RESET
pin
during power-on sequences.
READY/BUSY
:
This open drain output pin will be driv en
low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during programming operatio ns, co mpare op eratio ns, an d duri ng page -tobuffer transfers.
The busy status in dic at es that the Flash memory ar ra y and
one of the buffers cannot be accessed; read and write
operations to the other buffer can still be performed.
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This is a stress rating only an d
functional operati on of the de vi ce at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or exten ded periods ma y affect d evice
reliability .
DC and AC Operating Range
AT45D041
Operating Temperature (Case)
V
Power Supply
CC
Note: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.
(1)
Com. 0°C to 70°C
Ind. -40°C to 85°C
4.5V to 5.5V
5
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