ATMEL AT43311 Datasheet

Features

• Self-Powered Hub with Bus Power Controller

• Full Compliance with USB Spec Rev 1.0

• Full Speed USB Host Interface

• Four Downstream Ports

• Downstream Support for Full Speed and Low Speed Transfer Rates

• Continual Monitoring of Port by System Host

• Individual Port Power Control

• USB Connection Status Indicators

• 6 MHz Oscillator with On-Chip PLL

Description

The AT43311 is a fully compliant USB hub chip with 5 ports, one upstream port and four full/low-speed downstream ports. The AT43311 can be used as a stand alone or can provide a simple and quick method of adding USB ports to an existing device.

As a repeater, the AT43311 provides upstream connectivity between the selected function and the host. Connectivity involves setting up and tearing do wn connecti ons, handling bus faults, recovering from bus faults and detecting downstream device connections and disconnections.

The AT43311 may also act a s a hub cont roller mana ging the hu b operatio ns and recording the status of the hub, bus transactions, and downstream ports. In this mode, the AT43311 tracks and generates the bus enumeration , provides configuration information to the host, prov ides indi vidual port stat us to the host, an d controls the port operation based on host commands.

AT43311

USB Hub

AT43311 Preliminary

Pin Configurations

SOIC/DIP/Cerdip

PWR2 PWR3 PWR4

VCC5

VSS OSC1 OSC2

LFT

VCCA

OVL4 OVL3 OVL2 OVL1

VREF

GND

STAT4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

PWR1 DP4 DM4 DP3 DM3 GND DP2 DM2 VCC3 DP1 XDM1 DP0 DM0 STAT1 STAT2 STAT3

0738A-A

Block Diagram

STAT3

DP0

PWR3

OVL3

DM3

DP3

OSC2

OSC1

TIMING

AND

CONTROL

PORT 4

STAT4

PWR4

LFT

OVL4

DM4

VCC5

VCC3

VCCA

VREF

GND

DP4

DM0

HUB CONTROLLER

Serial Interface

Engine

Endpoint 0

PORT 1

Endpoint 1

Note: 1. This document assumes that the reader is familiar with the Universal Serial Bus and therefore only describes the unique

features of the AT43311 chip. For detailed information about the USB and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.0, January 19, 1996.

STAT1

Overcurrent Protection/ Reporting

OVL1

PWR1

DM1

DP1

PORT 2 PORT 3

STAT2

PWR2

PORT 0

REPEATER

DM2

OVL2

HUB

DP2

AT43311

Pin Description

Pin Description Pin Type Description

OSC1 I Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. OSC2 O Oscillator Output. Output of the inverting oscillator amplifier.

LFT I

VREF I Reference Voltage. This is an input pin that should be connected to an external

DP0 B Upstream Plus USB I/O. This pin should be connected to VCC3 through an external

DM0 B Upstream Minus USB I/O DP[1:4] B Port Plus USB I/O. These pins should be connected to VSS through external 1.5K Ω

DM[1:4] B

OVL[1:4]

PWR[1:4]

I Port Overload. These are the input signals used to indicate to the AT43311 that there

OD Power Switch. These are the output signals used to enable or disable the external

PLL Filter. For proper operation of the PLL, this pin should be connected through a 100 Ω resistor and 10 nF capacitor to ground (V (see Figure 1–Power Supply Connection).

voltage source. VREF is used internally as the reference voltage by the overload protection circuit to decide whether there is a problem with a port’s power supply.

1.5K Ω pullup resistor. DP0 and DM0 form the full speed differential signal pin pairs connected to the Host Controller or an upstream Hub.

resistors. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices.

Port Minus USB I/O. These pins should be connected to VSS through external 15K Ω resistors. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices.

is a power supply problem with the port. If OVL the corresponding PWR[1:4]

voltage regulator supplying power to the port. PWR[1:4] supply problem is detected at OVL[1:4]

For proper operation of PWR[1:4] required.

pin and report the status to the USB Host.

, an external pull-up resistor of 10K Ω to VCC5 is

) in parallel with a 2.2 nF capacitor

is asserted, the AT433 11 will assert

is de-asserted when a power

STAT[1:4]

CC3

CC5

CCA

GND V Ground

O Connect Status. These are output pins indicating that a port is properly connected.

STAT[1:4] V 3.3V Power Supply, used for the USB interface V 5V Power Supply, main power supply for the AT43311 V 5V Analog Power Supply

is asserted when the port is enabled.

USB Hub Description

Hub Repeater

The hub repeater i s responsibl e for port conn ectivity set up and tear-down. The rep eater a lso support s exception handling such as bus fault detection and r ecovery, and connect/disconnect detection.

When a SOP to ken is detecte d on the upst ream port, Port0, the AT43311 determines the speed of the transfer. A USB hub must not propagate a full speed transfer to a low speed port due to the possible misinterpretation of the data. The AT43311 will propagate the packet to all enabled downstream ports.

Note: See USB Specification for further detail on bus states

The AT43311 supports do wnstream dat a signaling at bo th

1.5 Mbps and 12 Mbps. Devices attached to the downstream ports are either full speed or low speed depending on which data line (DP or DM) is pulled hi gh. If a por t is enumerated as low speed, the output buffers operate at a slew rate between 75 ns and 300 ns. The AT43311 will not propagate any traffic to that port unless it is prefaced with a preamble PID. Low speed data fo llowing the preambl e PID is propagated to both low and full speed devices. The AT43311 will enable low speed drivers within four fullspeed bit times of the last bit of a preamble PID, and will disable the drivers at the end of an EOP. The upstream traffic from any port to the host is prop agated by Port0 using the full speed 4-20 ns slew rate drivers.

All ports are independently driven and monitored on the DP and DM pins. The AT43311 detects or generates the ‘J’, ‘K’, and SE0 bus s ignal ing st ates. E ach hu b port has s ingle-ended and differential receivers on its DP and DM lines. The ports’ I/O buffers comply to the voltage levels and drive requirements as specified in the USB Specifications Revision 1.0.

The Hub Repeater implements a frame timer that is timed by the 12 MHz USB clock and is reset every time an SOF token is received from the Host.

Hub Controller

The hub controller ma nages an d records the op eratio ns of the AT43311. During enumeration, the controller sends the host the configuration information. The controller also allows the host to retrieve the status of the downstream ports, and power the downs tream ports. The control ler applies power to the downstream ports on a per port basi s. After configuration , the co ntrol le r wil l e nab le the p owe r t o a downstream port upon a SetPortPower command by the host. The controller supports two endpoints and a Control Status register.

Serial Interface Engine

The Serial Interface Engine (SIE) converts data between the serialized USB format and usable data for the controller and repeater. To carry out these tasks, the SIE is able to detect or generate USB signaling. Once a valid operation is detected, the SIE translates the data depending on the operation.

During a reception, the SIE will use the high speed clock supplied by the PLL to help synchronize and separate the synchronization informa tion from th e data. The data mu st be decoded before the SIE may supply the packet ID to the controller and repeater.

The USB protocol uses Cyclical Redundancy Check (CRC), Non Return to Zero Invert (NRZI) data encoding and bit stuffi ng to i mprov e the re liabil ity of data trans fers. The SIE must decode the NR ZI and strip o ff the stuffe d bit to determine the actual data. The CRC information will be used by the SIE to determine if a transmission error has occurred. If an error has occurred, the SIE will correct the data using CRC algorithms.

Control Status Register

Bit Function Value Description

0 Hub configuration status

1 Hub remote wakeup status

2 Endpoint0 STALL status 0

3 Endpoint1 STALL status 0

AT43311

0 1

Set to 0 or 1 by a Set_Configuration Request

Set to 0 or 1 by ClearFeature or SetFeature request Default value is 0

Endpoint0 is stalled Endpoint0 is stalled

Endpoint1 is not stalled Endpoint1 is stalled

Hub is not currently configured Hub is currently configured

Hub is currently not enabled to request remote wakeup Hub is currently enables to request remote wakeup

AT43311

Endpoint0

Endpoint0 i s th e A T4331 1’s defa ult en dpoi nt u sed f or en umeration of the Hub and exchange of configuration information and requests between the Host and th e AT43311. Endpoint0 supports control transfers.

Standard USB Device Requests and class-specific Hub Requests are supported through Endpoint0.

The Hub Controller supports the fol lowing descriptors through Endpoint0 (Descriptors are described in detail in the Descriptors Section of this document):

• Device Descriptor

• Configuration Descriptor

• Interface Descriptor

• Endpoint Descriptor

• Hub Descriptor

Endpoint1

Endpoint1 is used by the Hub Controller to send status change information to the Hos t. Endpoint1 supp orts interrupt transfers.

The Hub Controller samples the c hanges at th e end of every frame at time marker EO F2 in preparation for a potential data transfer in the subsequent frame. The sampled information is stored as a byte in Statu s Chang e Register using a bitmap scheme.

Each bit in the Status Change Register corresponds to one port as shown below.

An IN Token packet from the Host to Endpoi nt1 ind icate s a request for port change status. If the Hub has not detected any change on the port s or a ny change s in the hub itself, then all bits in this register will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If a change in the port status exists, the Hub Controller will transfer the

whole byte. The Hub Controller will continue to report a status change when polled until that particular change has been removed by a ClearP ortFeature reques t from the Host. No status chang e will be reporte d by Endpoi nt1 unti l the AT43311 has been enumerated and configured by the Host through Endpoint0.

Power Management

The AT43311 is designed to be powered from the USB bus. As such, the power co nsumption for the AT43311 itself is less th an 100 m A. Howev er, down stream devices require separate power supplies. The AT43311 monitors and controls each power supply to the individual downstream devices.

Careful design and selection of the power switch is required to meet the USB specification. The USB specifications requires that the volta ge drop at th e power switch be no more than 100 mV. USB requirements specify that a downstream device may use a maximum of 500 mA. These conditions are best met by using a MOSFET switch with an on resistance of 200 m

As a sample power circuit, consid er a P-chan nel enhan cement mode MOSFET. The condition of the port’s power is monitored at the output side of the P MOS switch whi ch is connected to the port’s OVL[1:4] condition, the MOSFE T swit ch’s i nte rnal resista nce ca uses the MOSFET’s output voltage to drop at the OVL[1:4] the MOSFET’s out put voltage dr ops to less than the voltage at the VREF voltage reference pin, the AT4331 1 interprets this drop as a n overcurrent c ondition. The AT43311 does internal filtering to m ake su re that spurious o r switch ing transients are ignore d. If an overcurrent condit ion exists, the AT43 311 rem oves the power from t hat port b y de-activating the port’s PWR[1:4] tion to the Host.

Ω or less.

pin. During an overcurrent

pin. If

pin and reports the condi-

Status Change Register

Bit Function Value Meaning

0 Hub status change 0

1 Port1 status change 0

2 Port2 status change

3 Port3 status change

4 Port4 status change

5-7 Reserved 0 Default values

0 1

No change in status Change in status detected

Figure 1. Power Supply Connection

From upstream power regulator

VCC5 GND VCC3

VREF

3V REG.

AT43311

5.5V

PWR

5V POWER

SUPPLY

OVL

Figure 1 illustrates an example of the power supply connection for a AT43311 port.

Careful conside ration mu st be taken to avoid lar ge grou nd current surges. There is the possibility that the upstream device and the self powered device will be sourced from different electri cal powe r outle ts which share no comm on ground.

When designing the local power supply for the AT4 3311 or a self powered device , local 5 V power must be isolated. This isolation can be achieved th rough a transform er or by proper design of the switching power suppl y. The GND of the Hub or device can then be safely connected to the upstream ports ground line for proper operation of the USB signals.

Even though the devices in a USB network share a common ground (VSS), the t wo 5V supply volta ges of the AT43311 based hub (the upstream’s bus power and the local power) must not be connected under any condition.

Port [1:4] Power Control

Each port has signals for port power management and for port status feedback (PWR[1:4 ]

, OVL[1:4], and STAT[1:4]). The AT43311 monitors and switches the power to each port individually.

PWR[1:4]

are open drain outputs that control the power to the downstream ports. The AT43311 asserts a low value to ports PWR[1:4]

to turn on the power to the port. During

DP DM

power up, reset, and initialization of the Hu b, PWR[1:4] in-active. PWR[1:4]

STAT

To downstream device

VCC5

VSS

is asserted when the Host instructs the Hub to power the p ort through the S etPortPower = O N command. Additionally PWR[1:4]

is de-asserted by the Hub

when an overcurrent condition is detected at the port. For proper operation of PWR[1:4]

tor to VCC5 is required f or PWR[1:4]

, an external pull-up resis-

pins. To control the power to the port, any switch with a low voltage d rop with full power applied is acceptable . The AT43311 is desi gned for a simple, low cost P-c hannel MOS FET to us e as the switch.

To detect a port overload, the AT43311 compares OVL[1:4] to a common VREF defined by the designer.

OVL[1:4] respective downstre am port. If OVL[1:4]

should be attached to the power supply of the

drops below the reference voltage VREF for more than 1 ms, the AT43311 treats the drop in voltage as a fault condition on the port’s power supply. Upon this fault condition, the AT43311 sets the port’s PORT_OVER_CURRENT status bit and the port’s C_PORT_OVER_CURRENT bit. The AT43311 will additionally shut off the power to the port by de-activating the port’s PWR[1:4]

The STAT[1:4] tion. STAT[1:4]

signal.

pins are not required by the USB specifica-

provide feedback to the user whenever a device is properly connected to the port. An LED and series resistor connected to STAT[1:4]

can be used to provide

AT43311

visual feedback. The default state of STAT[1:4] After a port is enabled AT43311 will assert the port’s STAT[1 :4]

is inactive.

Oscillator and Phase-Locked-Loop

To reduce EMI and power dissip ation in the system, the AT43311 on-chip oscillator is designe d to ope rate wit h a 6 MHz external crystal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended stat e, the oscillator circuitry is turned off.

A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately 10 pF is recommended. If the crystal load capacitor is larger, external capacitors added to pins OSC1 and OSC2 are recommended. The values for these capacitors depends on the crystal and the layout of the board, but typically are 33 pF at OSC1 an d 47 pF at OSC2. If the crystal used cannot tolerate the drive level s of the oscillator, a series resistor between OSC2 and the crystal pin may be used.

Figure 2. Oscillator and PLL Connection

Figure 2 shows how to properly connect the oscillator for the AT43311. Ceramic resonators are not recommended due to the frequency stability required by the USB specification (0.25%).

If desired, the clock c an be external ly sourced. To clock externally, connect the clock source to the OSC1 pin, while leaving the OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0 .47V ( see electrical specifi cations). A CMOS device is required to drive this pin to maintain good noise margins at the low switching level.

For proper operation of the PLL, see Figure 1–Power Supply Connection.

To provide the best operating condition for the AT43311, careful consideration of the power supply connections are recommended. Use short, low impedance connections to all power supply lines: VCC5, VCC3, VCCA , and VSS with

0.1 µF decoupling capacitors of high quality adjacent to the device pins.

Descriptors

The Hub Controller supports the following standard USB descriptors: Device, Configurat ion, Interface, an d Endpoint Descriptors, as well as the class specific Hub Descriptor. All the required Standard Requests and Hub Class-Specific Requests are supported by the AT43311’s Hub Controller.

Device Descriptor

The Device Descriptor provides general information about the AT43311 Hub.

Offset Field Description Size (bytes) Value

0 bLength Define size of descriptor = 18 bytes 1 12H 1 bDescriptorType Device descriptor type 1 01H 2 bcdUSB USB Spec. Release Number = Rev 1.0 2 00H

4 bDeviceClass Class code = HUB_CLASSCODE = 09 1 09 H 5 bDeviceSubClass Subclass code 1 00H 6 bDeviceProtocol Protocol code 1 00H 7 wMaxPacketSize0 Max. packet size for Endpoint0 = 8-bytes 1 08H 9 idVendor Vendor ID = Atmel Corporation 2 EBH

10 idProduct Product ID = AT43311 2 11H

01H

03H

33H

12 bcdDevice

14 iManufacturer Index of string descriptor describing

15 iProduct Index of string descriptor describing product =

16 iSerialNumber Index of string descriptor describing device’s

17 bNumConfigurations Number of possible configurations = 1 1 01H

Device release number Example: Rev A0 YY = 01 ZZ = 00

Rev B1 YY = 02 ZZ = 01

manufacturer = not supported

not supported

serial no. = not supported

2 ZZH

YYH

100H

AT43311

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