ATMEL AT40K05, AT40K05LV, AT40K10, AT40K10LV, AT40K20 User Manual

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Features

• Ultra High Performance

– System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10nsFlexibleSRAM – Internal Tri-state Capability in Each Cell

• FreeRAM

– Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM – 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells

• 128 - 384 PCI Compliant I/Os

– 3V/5V Capability – Programmable Output Drive – Fast, Flexible Array Access Facilitates Pin Locking – Pin-compatible with XC4000, XC5200 FPGAs

• 8 Global Clocks

– Fast, Low Skew Clock Distribution – Programmable Rising/Falling Edge Transitions – Distributed Clock Shutdown Capability for Low Power Management – Global Reset/Asynchronous Reset Options – 4 Additional Dedicated PCI Clocks

• Cache Logic

– Unlimited Re-programmability via Serial or Parallel Modes – Enables Adaptive Designs – Enables Fast Vector Multiplier Updates – QuickChange

• Pin-compatible Package Options

– Plastic Leaded Chip Carriers (PLCC) – Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP) – Ball Grid Arrays (BGAs)

• Industry-standard Design Tools

– Seamless Integration (Libraries, Interface, Full Back-annotation) with

– Timing Driven Placement & Routing – Automatic/Interactive Multi-chip Partitioning – Fast, Efficient Synthesis – Over 75 Automatic Component Generators Create 1000s

• Intellectual Property Cores

– Fir Filters, UARTs, PCI, FFT and Other System Level Functions

• Easy Migration to Atmel Gate Arrays for High Volume Production

• Supply Voltage 5V for AT40K, and 3.3V for AT40KLV

™

Dynamic Full/Partial Re-configurability In-System

™

Tools for Fast, Easy Design Changes

Concept Verilog

of Reusable, Fully Deterministic Logic and RAM Functions

, Everest, Exemplar™,Mentor®, OrCAD®,Synario™, Synopsys®,

, Veribest®, Viewlogic®, Synplicity

5K - 50K Gates Coprocessor FPGA with FreeRAM

™

AT40K05 AT40K05LV AT40K10 AT40K10LV AT40K20 AT40K20LV AT40K40 AT40K40LV

Rev. 0896C–FPGA–04/0 2

Table 1. AT40K/AT40KLV Family

(1)

AT40K 05

Device

Usable Gates 5K - 10K 10K - 20K 20K - 30K 40K - 50K

Rows x Columns 16 x 16 24 x 24 32 x 32 48 x 48

Cells 256 576 1,024 2,304

Registers 256

RAM Bits 2,048 4,608 8,192 18,432

I/O (Maximum) 128 192 256 384

Note: 1. Packages with FCK will have 8 less registers.

AT40K05LV

(1)

AT40 K10

AT40K10LV

(1)

576

AT40K20

AT40K20LV

(1)

1,024

AT40K40

AT40K40LV

(1)

2,304

Description The AT40K/AT40KLV is a family of fully PCI-compliant, SRAM-based FPGAs with dis-

tributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 352-ball Square BGA, and support 5V designs for AT40K and 3.3V designs for AT40KLV.

The AT40K/AT40KLV is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform. Atmel’s design tools provide seamless integration with industry standard tools such as Synplicity, ModelSim, Exemplar and Viewlogic.

Fast, Flexible and Efficient SRAM

Fast, Efficient Array and Vector Multipliers

The AT40K/AT40KLV can be used as a coprocessor for high-speed (DSP/processorbased) designs by implementing a variety of computation intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications.

The AT40K/AT40KLV FPGA offers a patented distributed 10 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s macro generator tool.

The AT40K/AT40KLV’s patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40K/AT40KLV’s Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs.

AT40K/AT40KLV Series FPGA

0896C–FPGA–04/02

AT40K/AT40KLV Series FPGA

Cache Logic Design The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementing

Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40K/AT40KLV can act as a reconfigurable coprocessor.

Automatic Component Generators

The AT40K/AT40KLV FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions. The Automatic Component Generators work seamlessly with industry standard schematic and synthesis tools to create the fastest, most efficient designs available.

The patented AT40K/AT40KLV series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O.

Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to 2,304 registers. Pin locations are consistent throughout the AT40K/AT40KLV series for easy design migration in the same package footprint. The AT40K/AT40KLV series FPGAs utilize a reliable 0.6µ single-poly, CMOS process and are 100% factory-tested. Atmel’s PC- and workstation-based integrated development system (IDS) is used to create AT40K/AT40KLV series designs. Multiple design entry methods are supported.

The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances.

0896C–FPGA–04/02

The Symmetrical Array

At the heart of the Atmel architecture is a symmetrical array of identical cells, see Figure 1. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells, see Figure 2 on page 5. At the intersection of each repeater row and column there is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM nous or asynchronous operation.

Note: 1. The right-most column can only be used as single-port RAM.

Figure 1. Symmetrical Array Surrounded by I/O (AT40K20)

(1)

, with either synchro-

= I/O Pad

= AT40K Cell

= Repeater Row

= Repeater Column

= FreeRAM

AT40K/AT40KLV Series FPGA

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AT40K/AT40KLV Series FPGA

Figure 2. Floor Plan (Representative Portion)

= Vertical Repeater

= Horizontal Repeater

= Core Cell

RAM RAM

RV RV RV RV RV RV RV RV RV RV RV RV

RAM RAM RAM

RV RV RV RV RV RV RV RV RV RV RV RV

(1)

RAM RAM

RAM

RV RV RV RV RV RV RV RV RV RV RV RV

RAM RAM

RV RV RV RV RV RV RV RV RV RV RV RV

RAM

Note: 1. Repeaters regenerate signals and can connect any bus to any other bus (all path-

ways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool.

0896C–FPGA–04/02

The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus

resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are connected via repeaters. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. Each local-bus segment spans four cells and connects to consecutive repeaters. Each express-bus segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Although not shown, a local bus can bypass a repeater via a programmable pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are implemented through pass gates in the cell-bus interface. Express/Express turns are implemented through separate pass gates distributed throughout the array.

Some of the bus resources on the AT40K/AT40KLV are used as a dual-function resources. Table 2 shows which buses are used in a dual-function mode and which bus plane is used. The AT40K/AT40KLV software tools are designed to accommodate dualfunction buses in an efficient manner.

Table 2. Dual-function Buses

Function Type Plane(s) Direction Comments

Cell Output Enable Local 5 Horizontal

and Vertical

RAM Output Enable Express 2 Vertical Bus full length at array edge

Bus in first column to left of RAM block

RAM Write Enable Express 1 Vertical Bus full length at array edge

Bus in first column to left of RAM block

RAM Address Express 1 - 5 Vertical Buses full length at array edge

Buses in second column to left of RAM block

RAM Data In Local 1 Horizontal Data In connects to local

bus plane 1

RAM Data Out Local 2 Horizontal Data out connects to local

bus plane 2

Clocking Express 4 Vertical Bus half length at array edge

Set/Reset Express 5 Vertical Bus half length at array edge

AT40K/AT40KLV Series FPGA

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AT40K/AT40KLV Series FPGA

Figure 3. Busing Plane (One of Five)

= AT40K/AT40KLV Core Cell

= Local/Local or Express/Express Turn Point

= Row Repeater

= Column Repeater

0896C–FPGA–04/02

Express

Bus

Local

Bus

Express

Bus

Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.

Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane).

Figure 4. Cell Connections

CELL CELL

CELL CELL CELL

CELL

Direct Connect

Orthogonal

CELL

Diagonal

Direct Connect

CELL

Plane 5 Plane 4 Plane 3 Plane 2 Plane 1

Plane 5

Plane 4

  





Vertical

Busing Plane

Plane 3







Plane 2

Plane 1

W X Y Z L



WXYZL

CELL

 

Horizontal



Busing Plane

 

(a) Cell-to-cell Connections (b) Cell-to-bus Connections

The Cell Figure 5 depicts the AT40K/AT40KLV cell. Configuration bits for separate muxes and

pass gates are independent. All permutations of programmable muxes and pass gates are legal. V

n(V1-V5

connected to the horizontal local bus in plane by turning on the two pass gates connected to V signals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming into the logic cell on one local bus plane can be switched onto another plane by opening two of the pass gates. This allows bus signals to switch planes to achieve greater route ability. Up to five simultaneous local/local turns are possible.

) is connected to the vertical local bus in plane n. Hn(H1-H5)is

. A local/local turn in plane n is achieved

and Hn. Pass gates are opened to let

The AT40K/AT40KLV FPGA core cell is a highly configurable logic block based around two 3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tristated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an important feature in the implementation of efficient array multipliers.

With this functionality in each core cell, the core cell can be configured in several “modes”. The core cell flexibility makes the AT40K/AT40KLV architecture well suited to most digital design application areas, see Figure 6.

AT40K/AT40KLV Series FPGA

0896C–FPGA –04/02

Figure 5. The Cell

"1" NW NE SE SW

XWY

AT40K/AT40KLV Series FPGA

"1"

"1" N E S W

8X1 LUT 8X1 LUT

OUT OUT

"1""0"

CLOCK RESET/SET

NW NE SE SW N E S W

"1"

XZWY

Pass gates

"1" OE

HOEV

X = Diagonal Direct Connect or Bus Y = Orthogonal Direct Connect or Bus W = Bus Connection Z = Bus Connection FB = Internal Feedback

0896C–FPGA–04/02

Figure 6. Some Single Cell Modes

A B

Q (Registered)

and/or

SUM

LUTLUTLUTLUT LUT2:1 MUX LUTLUT

A B

SUM (Registered)

and/or

Synthesis Mode. This mode is particularly important for the use of VHDL/Verilog design. VHDL/Verilog Synthesis tools generally will produce as their output large amounts of random logic functions. Having a 4-input LUT structure gives efficient random logic optimization without the delays associated with larger LUT structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell.

Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40K/AT40KLV core cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the sum output in this diagram is registered. This output could then be tri-stated and/or fed back into the cell.

CARRY

DSP/Multiplier Mode. This mode is used to efficiently

PRODUCT (Registered) or

PRODUCT

C D

and/or

CARRY

implement array multipliers. An array multiplier is an array of bitwise multipliers, each implemented as a full adder with an upstream AND gate. Using this AND gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the AT40K/AT40KLV architecture.

CARRY IN

Counter Mode. Counters are fundamental to almost all digital designs. They are the basis of state machines,

and/or

timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit counter can be implemented in one core cell. Again, the output can be registered, tri-stated and/or fed back.

CARRY

A B

Tri-state/Mux Mode. This mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. The output of the core cell is very often tri-statable for many inputs to many outputs data switching.

AT40K/AT40KLV Series FPGA

0896C–FPGA –04/02

AT40K/AT40KLV Series FPGA

RAM 32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit

Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sectors in the same column. A 5-bit Output Address Bus connects to five vertical express buses in the same column. Ain (input address) and Aout (output address) alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks, Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the left and Aout is tied off, thus it can only be configured as a single port. For single-ported RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. Right-most RAM blocks can be used only for single-ported memories. WEN and OEN connect to the vertical express buses in the same column.

Figure 7. RAM Connections (One Ram Block)

CLK

Ain

32 x 4 RAM

WEN OEN

Din

Dout

Aout

CLK

0896C–FPGA–04/02

Reading and writing of the 10 ns 32 x 4 dual-port FreeRAM are independent of each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1, data flows through; when Load is logic 0, data is latched. These latches are used to synchronize Write Address, Write Enable Not

,and Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the memory latch together form an edge-triggered flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE logic 0, data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or WE

is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous RAM) or they both select “1” (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the “

Series”

application note at www.atmel.com).

AT40K Configuration

Figure 8. RAM Logic

CLOCK

“1”“1”

01 01

Load

32 x 4

Dual-port

RAM

Clear

RAM-Clear Byte

Dout

“1”

Dout

Ain

Aout

WEN

Din

Load

Latch

Load

Latch

Load

Latch

Read Address

Write Address

Write Enable NOT

Din

Figure 9 on page 13 shows an example of a RAM macro constructed using the AT40K/AT40KLV’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will be unused: they can be used for other logic in the design. This logic can be automatically generated using the macro generators.

AT40K/AT40KLV Series FPGA

0896C–FPGA –04/02

AT40K/AT40KLV Series FPGA

Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous)

Read

2-to-4

Address

Decoder

Dout(1)

Dout(0)

Dout(3)

Dout(2)

Dout(4)

Dout(5)

Dout(6)

Dout(7)

Local Buses

Express Buses

Din Dout

Aout Ain

WEN

OEN

Din Dout

WEN

OEN

Ain Aout

Din Dout

Aout Ain

WEN

OEN

Din Dout

Aout Ain

Din Dout

Ain Aout

Din Dout

Aout Ain

Dedicated Connections

WEN

OEN

WEN

OEN

WEN

OEN

0896C–FPGA–04/02

2-to-4

Decoder

Write

Address

Din(0)

Din(1)

Din(2)

Din Dout

Din(3)

WEN

OEN

Ain Aout

Din(4)

Din(5)

Din(6)

Din Dout

Din(7)

WEN

OEN

Ain Aout

Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA.

Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per edge column of the array for PCI specification.

Each column of an array has a “Column Clock mux” and a “Sector Clock mux”.TheColumn Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted, non-inverted or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a sector that has no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus, see Figure 10 on page 15. The extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to provide fast clocking to right-side I/Os.

The register in each cell is triggered on a rising clock edge by default. Before configuration on power-up, constant “0” is provided to each register’s clock pins. After configuration on power-up, the registers either set or reset, depending on the user’s choice.

The clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array.

AT40K/AT40KLV Series FPGA

0896C–FPGA –04/02

AT40K/AT40KLV Series FPGA

Figure 10. Clocking (for One Column of Cells)

“1”

Express Bus

(Plane 4; Half Length at Edge)

“1”

Repeater

}

FCK (2 per Edge Column of the Array)

 

GCK1 - GCK8



Column Clock Mux

Sector Clock Mux

Global Clock Line (Buried)

Sector Clock Mux

“1”

0896C–FPGA–04/02

Set/Reset Scheme The AT40K/AT40KLV family reset scheme is essentially the same as the clock scheme

except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to indicate the global reset. Additional resets will use the express bus network.

The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux, see Figure 11 on page 17. The set/reset provided to each sector column of four cells is either inverted or non-inverted using the Sector Reset mux.

The function of the Set/Reset input of a register is determined by a configuration bit in each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up).

AT40K/AT40KLV Series FPGA

0896C–FPGA –04/02

AT40K/AT40KLV Series FPGA

Figure 11. Set/Reset (for One Column of Cells)

Repeater

“1”

Each Cell has a Programmable Set or Rese

Sector Set/Reset Mux

Global Set/Reset Line (Buried)

Express Bus

(Plane 5; Half Length at Edge)

“1”

0896C–FPGA–04/02

Any User I/O can Drive Global Set/Reset Lone

I/O Structure

PA D The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os

have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the device size and package. These unbonded I/Os are used to perform a variety of bus turns at the edge of the array.

PULL-UP/PULL-DOWN Each pad has a programmable pull-up and pull-down attached to it. This supplies a

weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate the signal level of the pad pin.

The input stage of each I/O cell has a number of parameters that can be programmed either as properties in schematic entry or in the I/O Pad Attributes editor in IDS.

TTL/CMOS The threshold level can be set to either TTL/CMOS-compatible levels.

SCHMITT A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenera-

tive comparator circuit that adds 1V hysteresis to the input. This effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise.

DELAYS The input buffer can be programmed to include four different intrinsic delays as specified

in the AC timing characteristics. This feature is useful for meeting data hold requirements for the input signal.

DRIVE The output drive capabilities of each I/O are programmable. They can be set to FAST,

MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability (20 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive (14 mA at 5V) buffer, while SLOW yields a standard (6 mA at 5V) buffer.

TRI-STATE TheoutputofeachI/Ocanbemadetri-state(0,1orZ),opensource(1orZ)oropen

drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can be normal (0 or 1), as well.

SOURCE SELECTION MUX The Source Selection mux selects the source for the output signal of an I/O, see

Figure 12 on page 20.

AT40K/AT40KLV Series FPGA

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AT40K/AT40KLV Series FPGA

Primary, Secondary and Corner I/Os

Primary I/O Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and

Secondary I/O Every logic cell at the edge of the FPGA array has two direct diagonal connections to a

Corner I/O Logic cells at the corner of the FPGA array have direct-connect access to five separate

The AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40K/AT40KLV has access to one Primary I/O and two Secondary I/Os.

from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It also connects into the repeaters on the row immediately above and below the adjacent core cell. In addition, each Primary I/O also connects into the busing network of the three nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Primary I/O can be accessed from any logic cell on three separate rows or columns of the FPGA. See Figures 12a on page 20 and 13a on page 21.

Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O connects on the diagonal inputs to the cell above and the cell below. It also connects to the repeater of the cell above and below. In addition, each Secondary I/O also connects into the busing network of the two nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Secondary I/O can be accessed from any logic cell on two rows or columns of the FPGA. See Figure 12b on page 20 and Figure 13b.

I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40K/AT40KLV FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing networks running along the edges of the array. This means that many different edge logic cells can access the Corner I/Os. See Figure 14 on page 22.

0896C–FPGA–04/02

Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV

“0”

TRI-STATE

VCC

DRIVE

PULL-UP

“1”

“0”

CELL

PAD

PULL-DOWN

PULL-UP

PAD

GND

VCC

DELAY

SCHMITT

TTL/CMOS

(a) Primary I/O

TRI-STATE

DRIVE

“1”

SOURCE

SELECT MUX

“0” “1”

“0”

“1”

CELL

PULL-DOWN

GND

SCHMITT

TTL/CMOS

AT40K/AT40KLV Series FPGA

DELAY

SOURCE

SELECT MUX

DELAY

(b) Secondary I/O

CELL

0896C–FPGA –04/02

AT40K/AT40KLV Series FPGA

Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV

“0”

TRI-STATE

VCC

DRIVE

PULL-UP

“1”

“0”

CELL

PAD

PULL-DOWN

PULL-UP

PAD

GND

SCHMITT

TTL/CMOS

VCC

“1”

DELAY

SOURCE SELECT MUX

TRI-STATE

DRIVE

(a) Primary I/O

“0” “1”

“0”

“1”

CELL

0896C–FPGA–04/02

PULL-DOWN

GND

DELAY

SCHMITT

TTL/CMOS

CELL

SOURCE SELECT MUX

(a) Secondary I/O

+ 46 hidden pages