ATMEL AT34C02C User Manual

1
2
3
4

8
7
6
5

A0
A1
A2

GND

VCC
WP
SCL
SDA

1
2
3
4

8
7
6
5

A0
A1
A2

GND

VCC
WP
SCL
SDA

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Features

• Permanent and Reversible Software Write Protection for the First-half of the Array

– Software Procedure to Verify Write Protect Status

• Hardware Write Protection for the Entire Array

• Standard-voltage Operation

– 2.5 (VCC = 2.5V to 5.5V)

• Internally Organized 256 x 8

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 400 kHz (2.5V and 5.5V) Compatibility

• 16-byte Page Write Modes

• Partial Page Writes Are Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years

• 8-lead JEDEC SOIC and 8-lead TSSOP Packages

Two-wire
Automotive
Temperature
Serial EEPROM

Description

The AT34C02C provides 2048 bits of serial electrically-erasable and programmable
read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of
the device incorporates a permanent and a reversible software write protection feature
while hardware write protection for the entire array is available via an external pin.
Once the permanent software write protection is enabled, by sending a special com­mand to the device, it cannot be reversed. However, the reversible software write
protection is enabled and can be reversed by sending a special command. The hard­ware write protection is controlled with the WP pin and can be used to protect the
entire array, whether or not the software write protection has been enabled. This
allows the user to protect none, first-half, or all of the array depending on the applica­tion. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operations are essential. The AT34C02C is avail­able in space saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is
accessed via a Two-wire serial interface. It is available in 2.5V (2.5V to 5.5V).

Table 1. Pin Configurations

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

8-lead SOIC

with Permanent
and Reversible
Software Write
Protect

2K (256 x 8)

AT34C02C

WP Write Protect

8-lead TSSOP

Rev. 5242B–SEEPR–01/09

Absolute Maximum Ratings*

D

OUT

/ACK

LOGIC

D

OUT

D

IN

A

0

SDA

GND

A

1

SCL

V

CC

A

2

Y DEC

DATA WORD

ADDR/COUNTER

SERIAL

CONTROL

LOGIC

START

STOP

LOGIC

DEVICE

ADDRESS

COMPARATOR

SERIAL MUX

EEPROM

EN

COMP

INCLOAD

LOAD

R/W

H.V. PUMP/TIMING

DATA RECOVERY

X DEC

WP

WRITE PROTECT

CIRCUITRY

SOFTWARE WRITE
PROTECTED AREA

(00H - 7FH)

Operating Temperature..................................–55°C to +125 °C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground .................................... –1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM

device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open­drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs
that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as eight 2K devices may be addressed on a single bus
system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device
is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci-

2

AT34C02C

5242B–SEEPR–01/09

tive coupling that may appear during customer applications, Atmel recommends always
connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends
using 10kΩ or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected directly to Vcc, all write operations to the memory are inhib­ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to
capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends
using 10kΩ or less.

Table 2. AT34C02C Write Protection Modes

AT34C02C

WP Pin Status

V

CC

Permanent Write Protect

Register

– – Full Array (2K)

Reversible Write Protect

Register

Part of the Array Write

Protected

GND or Floating Not Programmed Not Programmed Normal Read/Write

GND or Floating Programmed –

GND or Floating – Programmed

Table 3. Pin Capacitance

(1)

First-Half of Array

(1K: 00H - 7FH)

First-Half of Array

(1K: 00H - 7FH)

Applicable over recommended operating range from TA = 25⋅C, f = 400 kHz, VCC = +2.5V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

I/O

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 4. DC Characteristics

Applicable over recommended operating range from: T

Symbol Parameter Test Condition Min Typ Max Units

V

CC

I

CC

I

CC

I

SB2

I

SB3

I

LI

I

LO

V

IL

V

IH

V

OL

Note: 1. V

Supply Voltage 2.5 5.5 V

Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA

Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

Standby Current VCC = 2.5V VIN = VCC or V

Standby Current VCC = 5.0V VIN = VCC or V

Input Leakage Current VIN = VCC or V

Output Leakage Current V

Input Low Level

Input High Level

(1)

(1)

Output Low Level VCC = 2.5V IOL = 3.0 mA 0.4 V

min and VIH max are reference only and are not tested.

IL

= –40⋅C to +125⋅C, V

A

SS

SS

SS

= V

CC

or V

SS

OUT

= +2.5V to +5.5V, (unless otherwise noted)

CC

1.6 4.0 µA

8.0 18.0 µA

0.10 3.0 µA

0.05 3.0 µA

–0.6 V

x 0.3 V

CC

VCC x 0.7 VCC + 0.5 V

5242B–SEEPR–01/09

3

Table 5. AC Characteristics

Applicable over recommended operating range from T

= –40⋅C to +125⋅C, VCC = +2.5V to +5.5V, CL = 1 TTL Gate and

A

100 pF (unless otherwise noted)

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

I

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Note: 1. This parameter is ensured by characterization only.

Clock Frequency, SCL 400 kHz

Clock Pulse Width Low 1.2 µs

Clock Pulse Width High 0.6 µs

Noise Suppression Time

(1)

Clock Low to Data Out Valid 0.1 0.9 µs

Time the bus must be free before a new
transmission can start

(1)

Start Hold Time 0.6 µs

Start Set-up Time 0.6 µs

Data In Hold Time 0 µs

Data In Set-up Time 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

Stop Set-up Time 0.6 µs

Data Out Hold Time 50 ns

Write Cycle Time 5ms

(1)

25⋅C, Page Mode

AT34C02C

UnitsMin Max

50 ns

1.2 µs

300 ns

300 ns

1M

Write

Cycles

Memory
Organization

Device
Operation

4

AT34C02C

AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each.

Random word addressing requires a 8-bit data word address.

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on

page 6). Data changes during SCL high periods will indicate a start or stop condition as defined

below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 6).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-

ure 5 on page 6).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.

5242B–SEEPR–01/09

STANDBY MODE: The AT34C02C features a low-power standby mode which is enabled: (a)

SCL

SDA

12389

Start Bit Start Bit Stop Bit

Dummy Clock Cycles

t

wr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

upon power-up or (b) after the receipt of the STOP bit and the completion of any internal
operations.

2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be protocol reset by following these steps (a) Create a start bit condition, (b)
Clock 9 cycles, (c) Create another start bit followed by a stop bit condition as shown below. The
device is ready for next communication after above steps have been completed.

Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O

AT34C02C

Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

5242B–SEEPR–01/09

5

Figure 4. Data Validity

Figure 5. Start and Stop Condition

Figure 6. Output Acknowledge

Device
Addressing

The 2K EEPROM device requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 10 on page 11).

6

AT34C02C

5242B–SEEPR–01/09