ATMEL AT34C02B User Manual

L A

查询AT34C02B-10TU-1.7供应商

Features

• Permanent and Reversible Software Write Protection for the First-half of the Array

– Software Procedure to Verify Write Protect Status

• Hardware Write Protection for the Entire Array

• Low-voltage and Standard-voltage Operation

– 1.7 (VCC = 1.7V to 3.6V)

• Internally Organized 256 x 8

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 100 kHz (1.7V) and 400 kHz (2.7V and 3.6V) Compatibility

• 16-byte Page Write Modes

• Partial Page Writes Are Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles – Data Retention: 100 Years

• 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball

dBGA2 Packages

Two-wire Serial EEPROM with Permanent and Reversible Software Write

Description

The AT34C02B provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a permanent and a reversible software write protection feature while hardware write protection for the entire array is available via an external pin. Once the permanent software write protection is enabled, by sending a special command to the device, it cannot be reversed. However, the reversible software write protection is enabled and can be reversed by sending a special command. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the application. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT34C02B is available in space saving 8-lead JEDEC SOIC, TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. It is available in 1.7V (1.7V to 3.6V).

Table 1. Pin Configurations

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

VCC

SCL SDA

8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead

8-ball dBGA2

Bottom View

GND

8-lead Ultra Thin Mini-MAP

SCL

(MLP 2x3)

Bottom View

Protect

2K (256 x 8)

AT34C02B

Note: Not recommended for new

design; please refer to AT34C02C datasheet.

8-lead TSSOP

8-lead SOIC

Rev. 3417E–SEEPR–1/07

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground .................................... –1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

CL DA

2 1 0

START

STOP

LOGIC

LOAD

DEVICE

ADDRESS

COMPARATOR

R/W

*NOTICE: Stresses beyond those listed under “Absolute

CONTROL

WRITE PROTECT

CIRCUITRY

COMP

DATA WORD

ADDR/COUNTER

SERIAL

LOGIC

INCLOAD

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

H.V. PUMP/TIMING

DATA RECOVERY

SOFTWARE WRITE PROTECTED AREA

(00H - 7FH)

X DEC

EEPROM

Y DEC

AT34C02B

OUT

SERIAL MUX

/ACK

OUT

LOGIC

3417E–SEEPR–1/07

AT34C02B

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.

Table 2. AT34C02B Write Protection Modes

WP Pin Status

GND or Floating Not Programmed Not Programmed Normal Read/Write

GND or Floating Programmed –

GND or Floating – Programmed

Table 3. Pin Capacitance

Permanent Write Protect

– – Full Array (2K)

(1)

Reversible Write Protect

Part of the Array Write

Protected

First-Half of Array

(1K: 00H - 7FH)

First-Half of Array

(1K: 00H - 7FH)

Applicable over recommended operating range from TA = 25°C, f = 100 kHz, VCC = +1.7V

Symbol Test Condition Max Units Conditions

I/O

Note: 1. This parameter is characterized and is not 100% tested.

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

I/O

= 0V

3417E–SEEPR–1/07

Table 4. DC Characteristics

Applicable over recommended operating range from: T

= –40°C to +85°C, V

= +1.7V to +3.6V, (unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

CC1

SB1

SB2

OL2

OL1

Supply Voltage 1.7 3.6 V

Supply Current VCC = 3.6V READ at 100 kHz 0.4 1.0 mA

Supply Current VCC = 3.6V WRITE at 100 kHz 2.0 3.0 mA

Standby Current VCC = 1.7V VIN = VCC or V

Standby Current VCC = 3.6V VIN = VCC or V

Input Leakage Current VIN = VCC or V

Output Leakage Current V

Input Low Level

Input High Level

(1)

OUT

= V

or V

–0.6 V

VCC x 0.7 VCC + 0.5 V

0.6 3.0 µA

1.6 4.0 µA

0.10 3.0 µA

0.05 3.0 µA

x 0.3 V

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

Output Low Level VCC = 1.7V IOL = 0.15 mA 0.2 V

Note: 1. VIL min and VIH max are reference only and are not tested.

AT34C02B

3417E–SEEPR–1/07

Table 5. AC Characteristics

AT34C02B

Applicable over recommended operating range from T

= –40°C to +85°C, VCC = +1.7V to +3.6V, CL = 1 TTL Gate and

100 pF (unless otherwise noted)

Symbol Parameter

SCL

LOW

HIGH

BUF

HD.STA

SU.STA

HD.DAT

SU.DAT

SU.STO

Endurance

Note: 1. This parameter is characterized and is not 100% tested.

Clock Frequency, SCL 100 400 kHz

Clock Pulse Width Low 4.7 1.2 µs

Clock Pulse Width High 4.0 0.6 µs

Noise Suppression Time

(1)

Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs

Time the bus must be free before a new transmission can start

(1)

Start Hold Time 4.0 0.6 µs

Start Set-up Time 4.7 0.6 µs

Data In Hold Time 0 0 µs

Data In Set-up Time 200 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

Stop Set-up Time 4.7 0.6 µs

Data Out Hold Time 100 50 ns

Write Cycle Time 5 5 ms

(1)

25°C, Page Mode

1.7V 2.7V, 3.6V

UnitsMin Max Min Max

100 50 ns

4.7 1.2 µs

1.0 0.3 µs

300 300 ns

1M 1M

Write

Cycles

3417E–SEEPR–1/07

Memory Organization AT34C02B, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16

bytes each. Random word addressing requires a 8-bit data word address.

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT34C02B features a low-power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any Two-wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition.

AT34C02B

3417E–SEEPR–1/07

Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O

Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O

AT34C02B

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

8th BIT

WORDn

ACK

STOP

CONDITION

(1)

START

CONDITION

Figure 4. Data Validity

3417E–SEEPR–1/07

+ 14 hidden pages