Atmel AT32UC3A0512, AT32UC3A0256, AT32UC3A0128, AT32UC3A1512, AT32UC3A1256 Datasheet

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Features

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AVR32-01/12

• High Performance, Low Power 32-Bit Atmel

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing 1.49 DMIPS / MHz

Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State) Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)

– Memory Protection Unit

• Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance – 15 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes Versions – Single Cycle Access up to 33 MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)

• External Memory Interface on AT32UC3A0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

• Universal Serial Bus (USB)

– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-chip Transceivers Including Pull-Ups

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller – Supports Media Independent Interface (MII) and Reduced MII (RMII)

• One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces – Support for Hardware Handshaking, RS485 Interfaces and Modem Line

• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

• One Synchronous Serial Protocol Controller

– Supports I2S and Generic Frame-Based Protocols

• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible

• One 8-channel 10-bit Analog-To-Digital Converter

• 16-bit Stereo Audio Bitstream

– Sample Rate Up to 50 KHz

AVR® Microcontroller

32-Bit Atmel AVR Microcontroller

AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128

• On-Chip Debug System (JTAG interface)

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– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace

• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins)

• 5V Input Tolerant I/Os

• Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply

AT32UC3A

1. Description

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AT32UC3A

The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions.

The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access. For applications requiring additional memory, an external memory interface is provided on AT32UC3A0 derivatives.

The Peripheral Direct Memory Access controller (PDCA) enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU.

The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.

The PWM modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. One PWM channel can trigger ADC conversions for more accurate close loop control implementations.

The AT32UC3A also features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like flexible Synchronous Serial Controller, USB and Ethernet MAC are available.

The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I2S.

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor.

The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module provides on-chip solutions for network-connected devices.

AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control.

2. Configuration Summary

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The table below lists all AT32UC3A memory and package configurations:

Device Flash SRAM Ext. Bus Interface AT32UC3A0512 512 Kbytes 64 Kbytes yes yes 144 pin LQFP

AT32UC3A0256 256 Kbytes 64 Kbytes yes yes 144 pin LQFP

AT32UC3A0128 128 Kbytes 32 Kbytes yes yes 144 pin LQFP

AT32UC3A1512 512 Kbytes 64 Kbytes no yes 100 pin TQFP AT32UC3A1256 256 Kbytes 64 Kbytes no yes 100 pin TQFP AT32UC3A1128 128 Kbytes 32 Kbytes no yes 100 pin TQFP

AT32UC3A

Ethernet MAC Package

144 pin BGA

3. Abbreviations

• GCLK: Power Manager Generic Clock

• GPIO: General Purpose Input/Output

• HSB: High Speed Bus

• MPU: Memory Protection Unit

• OCD: On Chip Debug

• PB: Peripheral Bus

• PDCA: Peripheral Direct Memory Access Controller (PDC) version A

• USBB: USB On-The-GO Controller version B

4. Blockdiagram

UC CPU

NEXUS

CLASS 2+

OCD

INSTR

INTERFACE

DATA

INTERFACE

TIMER/COUNTER

INTERRUPT

CONTROLLER

REAL TIME

COUNTER

PERIPHERAL

DMA

CONTROLLER

512 KB FLASH

HSB-PB

BRIDGE B

HSB-PB

BRIDGE A

MEMORY INTERFACE

M M M

M M

EXTERNAL

INTERRUPT

CONTROLLER

HIGH SPEED BUS MATRIX

FAST GPIO

GENERAL PURPOSE IOs

64 KB SRAM

GENERAL PURPOSE IOs

PA PB PC PX

A[2..0] B[2..0]

CLK[2..0]

EXTINT[7..0]

KPS[7..0]

NMI_N

GCLK[3..0]

XIN32

XOUT32

XIN0

XOUT0

PA PB PC PX

RESET_N

EXTERNAL BUS INTERFACE

(SDRAM & STATIC MEMORY

CONTROLLER)

CAS

RAS

SDA10

SDCK SDCKE SDCS0

SDWE

NCS[3..0]

NRD

NWAIT

NWE0

DATA[15..0]

USB

INTERFACE

DMA

VBOF

VBUS

D-

D+

ETHERNET

MAC

DMA

32 KHz

OSC

115 kHz RCOSC

OSC0

PLL0

PULSE WIDTH MODULATION CONTROLLER

SERIAL

PERIPHERAL

INTERFACE 0/1

TWO-WIRE

INTERFACE

PDCPDC PDC

MISO, MOSI

NPCS[3..1]

PWM[6..0]

SCL

SDA

USART1

PDC

RXD TXD CLK

RTS, CTS

DSR, DTR, DCD, RI

USART0 USART2 USART3

PDC

RXD TXD CLK

RTS, CTS

SYNCHRONOUS

SERIAL

CONTROLLER

PDC

TX_CLOCK, TX_FRAME_SYNC

RX_DATA

TX_DATA

RX_CLOCK, RX_FRAME_SYNC

ANALOG TO

DIGITAL

CONVERTER

PDC

AD[7..0]

ADVREF

WATCHDOG

TIMER

XIN1

XOUT1

OSC1

PLL1

SCK

JTAG

INTERFACE

MCKO

MDO[5..0]

MSEO[1..0]

EVTI_N

EVTO_N

TCK TDO

TDI

TMS

POWER

MANAGER

RESET

CONTROLLER

ADDR[23..0]

SLEEP

CONTROLLER

CLOCK

CONTROLLER

CLOCK

GENERATOR

COL,

CRS, RXD[3..0], RX_CLK,

RX_DV,

RX_ER

MDC,

TXD[3..0],

TX_CLK,

TX_EN, TX_ER,

SPEED

MDIO

FLASH

CONTROLLER

CONFIGURATION REGISTERS BUS

MEMORY PROTECTION UNIT

HSB

NWE1 NWE3

PBA

PBB

NPCS0

LOCAL BUS INTERFACE

AUDIO

BITSTREAM

DAC

PDC

DATA[1..0]

DATAN[1..0]

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Figure 4-1. Blockdiagram

AT32UC3A

4.1 Processor and architecture

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4.1.1 AVR32 UC CPU

• 32-bit load/store AVR32A RISC architecture.

– 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and unprivileged modes enabling efficient and secure Operating Systems. – Innovative instruction set together with variable instruction length ensuring industry leading

code density.

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.

• 3 stage pipeline allows one instruction per clock cycle for most instructions.

– Byte, half-word, word and double word memory access. – Multiple interrupt priority levels.

• MPU allows for operating systems with memory protection.

4.1.2 Debug and Test system

• IEEE1149.1 compliant JTAG and boundary scan

• Direct memory access and programming capabilities through JTAG interface

• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+

– Low-cost NanoTrace supported.

• Auxiliary port for high-speed trace information

• Hardware support for 6 Program and 2 data breakpoints

• Unlimited number of software breakpoints supported

• Advanced Program, Data, Ownership, and Watchpoint trace supported

AT32UC3A

4.1.3 Peripheral DMA Controller

• Transfers from/to peripheral to/from any memory space without intervention of the processor.

• Next Pointer Support, forbids strong real-time constraints on buffer management.

• Fifteen channels

– Two for each USART – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for each ADC – Two for each TWI Interface

4.1.4 Bus system

• High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled

– Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet

Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, EBI.

– Round-Robin Arbitration (three modes supported: no default master, last

master, fixed default master)

– Burst Breaking with Slot Cycle Limit – One Address Decoder Provided per Master

accessed default

AT32UC3A

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• Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus

Figure 4-1 gives an overview of the bus system. All modules connected to the same bus use the

same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the High Speed Bus, and which DMA controller is connected to which peripheral.

5. Signals Description

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The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in ”Peripheral Multiplexing on I/O lines”

on page 45.

Table 5-1. Signal Description List

Signal Name Function Type

Power

AT32UC3A

Active

Level Comments

VDDPLL Power supply for PLL

VDDCORE Core Power Supply

VDDIO I/O Power Supply

VDDANA Analog Power Supply

VDDIN Voltage Regulator Input Supply

VDDOUT Voltage Regulator Output

GNDANA Analog Ground Ground

GND Ground Ground

Clocks, Oscillators, and PLL’s

XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog

XOUT0, XOUT1, XOUT32

Crystal 0, 1, 32 Output Analog

Power

Input

Power

Input

Power

Input

Power

Input

Power

Input

Power

Output

1.65V to 1.95 V

3.0V to 3.6V

1.65V to 1.95 V

JTAG

TCK Test Clock Input

TDI Test Data In Input

TDO Test Data Out Output

TMS Test Mode Select Input

Auxiliary Port - AUX

MCKO Trace Data Output Clock Output

MDO0 - MDO5 Trace Data Output Output

Table 5-1. Signal Description List

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AVR32-01/12

Active

Signal Name Function Type

MSEO0 - MSEO1 Trace Frame Control Output

EVTI_N Event In Output Low

EVTO_N Event Out Output Low

Power Manager - PM

GCLK0 - GCLK3 Generic Clock Pins Output

RESET_N Reset Pin Input Low

Real Time Counter - RTC

RTC_CLOCK RTC clock Output

Watchdog Timer - WDT

WDTEXT External Watchdog Pin Output

Level Comments

AT32UC3A

External Interrupt Controller - EIC

EXTINT0 - EXTINT7 External Interrupt Pins Input

KPS0 - KPS7 Keypad Scan Pins Output

NMI_N Non-Maskable Interrupt Pin Input Low

Ethernet MAC - MACB

COL Collision Detect Input

CRS Carrier Sense and Data Valid Input

MDC Management Data Clock Output

MDIO Management Data Input/Output I/O

RXD0 - RXD3 Receive Data Input

RX_CLK Receive Clock Input

RX_DV Receive Data Valid Input

RX_ER Receive Coding Error Input

SPEED Speed

TXD0 - TXD3 Transmit Data Output

TX_CLK Transmit Clock or Reference Clock Output

TX_EN Transmit Enable Output

TX_ER Transmit Coding Error Output

Table 5-1. Signal Description List

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AVR32-01/12

Active

Signal Name Function Type

External Bus Interface - HEBI

ADDR0 - ADDR23 Address Bus Output

CAS Column Signal Output Low

DATA0 - DATA15 Data Bus I/O

NCS0 - NCS3 Chip Select Output Low

NRD Read Signal Output Low

NWAIT External Wait Signal Input Low

NWE0 Write Enable 0 Output Low

NWE1 Write Enable 1 Output Low

NWE3 Write Enable 3 Output Low

Level Comments

AT32UC3A

RAS Row Signal Output Low

SDA10 SDRAM Address 10 Line Output

SDCK SDRAM Clock Output

SDCKE SDRAM Clock Enable Output

SDCS0 SDRAM Chip Select Output Low

SDWE SDRAM Write Enable Output Low

General Purpose Input/Output 2 - GPIOA, GPIOB, GPIOC

P0 - P31 Parallel I/O Controller GPIOA I/O

P0 - P31 Parallel I/O Controller GPIOB I/O

P0 - P5 Parallel I/O Controller GPIOC I/O

P0 - P31 Parallel I/O Controller GPIOX I/O

Serial Peripheral Interface - SPI0, SPI1

MISO Master In Slave Out I/O

MOSI Master Out Slave In I/O

NPCS0 - NPCS3 SPI Peripheral Chip Select I/O Low

SCK Clock Output

Synchronous Serial Controller - SSC

RX_CLOCK SSC Receive Clock I/O

Table 5-1. Signal Description List

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AVR32-01/12

Signal Name Function Type

RX_DATA SSC Receive Data Input

RX_FRAME_SYNC SSC Receive Frame Sync I/O

TX_CLOCK SSC Transmit Clock I/O

TX_DATA SSC Transmit Data Output

TX_FRAME_SYNC SSC Transmit Frame Sync I/O

Timer/Counter - TIMER

A0 Channel 0 Line A I/O

A1 Channel 1 Line A I/O

A2 Channel 2 Line A I/O

B0 Channel 0 Line B I/O

AT32UC3A

Active

Level Comments

B1 Channel 1 Line B I/O

B2 Channel 2 Line B I/O

CLK0 Channel 0 External Clock Input Input

CLK1 Channel 1 External Clock Input Input

CLK2 Channel 2 External Clock Input Input

Two-wire Interface - TWI

SCL Serial Clock I/O

SDA Serial Data I/O

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3

CLK Clock I/O

CTS Clear To Send Input

DCD Data Carrier Detect Only USART1

DSR Data Set Ready Only USART1

DTR Data Terminal Ready Only USART1

RI Ring Indicator Only USART1

RTS Request To Send Output

RXD Receive Data Input

TXD Transmit Data Output

Table 5-1. Signal Description List

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AVR32-01/12

Signal Name Function Type

Analog to Digital Converter - ADC

AT32UC3A

Active

Level Comments

AD0 - AD7 Analog input pins

ADVREF Analog positive reference voltage input

Pulse Width Modulator - PWM

PWM0 - PWM6 PWM Output Pins Output

Universal Serial Bus Device - USB

DDM USB Device Port Data - Analog

DDP USB Device Port Data + Analog

VBUS USB VBUS Monitor and OTG Negociation

USBID ID Pin of the USB Bus Input

USB_VBOF USB VBUS On/off: bus power control port output

Audio Bitstream DAC (ABDAC)

DATA0-DATA1 D/A Data out Outpu

DATAN0-DATAN1 D/A Data inverted out Outpu

Analog

input

Analog

input

Analog

Input

2.6 to 3.6V

6. Power Considerations

3.3V

VDDANA

VDDIO

VDDIN

VDDCORE

VDDOUT

VDDPLL

ADVREF

3.3V

1.8V

VDDANA

VDDIO

VDDIN

VDDCORE

VDDOUT

VDDPLL

ADVREF

Single Power Supply

Dual Power Supply

1.8V

Regulator

1.8V

Regulator

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AVR32-01/12

6.1 Power Supplies

The AT32UC3A has several types of power supply pins:

• VDDIO: Powers I/O lines. Voltage is 3.3V nominal.

• VDDANA: Powers the ADC Voltage is 3.3V nominal.

• VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal.

• VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.

• VDDPLL: Powers the PLL. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO, VDDPLL. The ground pin for

VDDANA is GNDANA. Refer to ”Power Consumption” on page 767 for power consumption on the various supply pins.

AT32UC3A

6.2 Voltage Regulator

3.3V

1.8V

VDDIN

VDDOUT

1.8V

Regulator

IN1

OUT1

OUT2

IN2

VDDIN

VDDOUT

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6.2.1 Single Power Supply

The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to the 1.8V domains.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and GND as close to the chip as possible

AT32UC3A

Refer to Section 38.3 on page 765 for decoupling capacitors values and regulator characteristics

6.2.2 Dual Power Supply

In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current.

6.3 Analog-to-Digital Converter (A.D.C) reference.

ADVREF

VREF1VREF2

3.3V

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The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling.

Refer to Section 38.4 on page 765 for decoupling capacitors values and electrical characteristics.

In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption.

AT32UC3A

1 25

5175

100

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AVR32-01/12

7. Package and Pinout

The device pins are multiplexed with peripheral functions as described in ”Peripheral Multiplexing on I/O lines” on page 45.

Figure 7-1. TQFP100 Pinout

Table 7-1. TQFP100 Package Pinout

1 PB20 26 PA05 51 PA21 76 PB08 2 PB21 27 PA06 52 PA22 77 PB09 3 PB22 28 PA07 53 PA23 78 PB10 4 VDDIO 29 PA08 54 PA24 79 VDDIO 5 GND 30 PA09 55 PA25 80 GND 6 PB23 31 PA10 56 PA26 81 PB11 7 PB24 32 N/C 57 PA27 82 PB12 8 PB25 33 PA11 58 PA28 83 PA29

9 PB26 34 VDDCORE 59 VDDANA 84 PA30 10 PB27 35 GND 60 ADVREF 85 PC02 11 VDDOUT 36 PA12 61 GNDANA 86 PC03 12 VDDIN 37 PA13 62 VDDPLL 87 PB13 13 GND 38 VDDCORE 63 PC00 88 PB14 14 PB28 39 PA 15 PB29 40 PA15 16 PB30 41 PA16 66 PB01 91 TDO 17 PB31 42 PA17 67 VDDIO 92 TDI 18 RESET_N 43 PA18 68 VDDIO 93 PC04 19 PA00 44 PA19 69 GND 94 PC05 20 PA01 45 PA20 70 PB02 95 PB15 21 GND 46 VBUS 71 PB03 96 PB16 22 VDDCORE 47 VDDIO 72 PB04 97 VDDCORE

64 PC01 89 TMS 65 PB00 90 TCK

AT32UC3A

1 36

73108

109

144

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AVR32-01/12

Table 7-1. TQFP100 Package Pinout

23 PA02 48 DM 73 PB05 98 PB17 24 PA03 49 DP 74 PB06 99 PB18 25 PA04 50 GND 75 PB07 100 PB19

Figure 7-2. LQFP144 Pinout

Table 7-2. VQFP144 Package Pinout

1 PX00 37 GND 73 PA21 109 GND

2 PX01 38 PX10 74 PA22 110 PX30

3 PB20 39 PA05 75 PA23 111 PB08

4 PX02 40 PX11 76 PA24 112 PX31

5 PB21 41 PA06 77 PA25 113 PB09

6 PB22 42 PX12 78 PA26 114 PX32

7 VDDIO 43 PA07 79 PA27 115 PB10

8 GND 44 PX13 80 PA28 116 VDDIO

9 PB23 45 PA08 81 VDDANA 117 GND 10 PX03 46 PX14 82 ADVREF 118 PX33 11 PB24 47 PA09 83 GNDANA 119 PB11 12 PX04 48 PA10 84 VDDPLL 120 PX34 13 PB25 49 N/C 85 PC00 121 PB12 14 PB26 50 PA 15 PB27 51 VDDCORE 87 PX20 123 PA30 16 VDDOUT 52 GND 88 PB00 124 PC02 17 VDDIN 53 PA12 89 PX21 125 PC03 18 GND 54 PA13 90 PB01 126 PB13 19 PB28 55 VDDCORE 91 PX22 127 PB14 20 PB29 56 PA14 92 VDDIO 128 TMS 21 PB30 57 PA15 93 VDDIO 129 TCK

86 PC01 122 PA29

AT32UC3A

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Table 7-2. VQFP144 Package Pinout

22 PB31 58 PA16 94 GND 130 TDO 23 RESET_N 59 PX15 95 PX23 131 TDI 24 PX05 60 PA17 96 PB02 132 PC04 25 PA00 61 PX16 97 PX24 133 PC05 26 PX06 62 PA18 98 PB03 134 PB15 27 PA01 63 PX17 99 PX25 135 PX35 28 GND 64 PA19 100 PB04 136 PB16 29 VDDCORE 65 PX18 101 PX26 137 PX36 30 PA02 66 PA20 102 PB05 138 VDDCORE 31 PX07 67 PX19 103 PX27 139 PB17 32 PA03 68 VBUS 104 PB06 140 PX37 33 PX08 69 VDDIO 105 PX28 141 PB18 34 PA04 70 DM 106 PB07 142 PX38 35 PX09 71 DP 107 PX29 143 PB19 36 VDDIO 72 GND 108 VDDIO 144 PX39

Figure 7-3. BGA144 Pinout

AT32UC3A

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AVR32-01/12

Table 7-3. BGA144 Package Pinout A1..M8

1 2 3 4 5 6 7 8

VDDIO PB07 PB05 PB02 PB03 PB01 PC00 PA28

PB08 GND PB06 PB04 VDDIO PB00 PC01 VDDPLL

PB09 PX33 PA29 PC02 PX28 PX26 PX22 PX21

PB11 PB13 PB12 PX30 PX29 PX25 PX24 PX20

PB10 VDDIO PX32 PX31 VDDIO PX27 PX23 VDDANA

PA30 PB14 PX34 PB16 TCK GND GND PX16

TMS PC03 PX36 PX35 PX37 GND GND PA16

TDO VDDCORE PX38 PX39 VDDIO PA01 PA10 VDDCORE

TDI PB17 PB15 PX00 PX01 PA00 PA03 PA04

PC05 PC04 PB19 PB20 PX02 PB29 PB30 PA02

PB21 GND PB18 PB24 VDDOUT PX04 PB31 VDDIN

PB22 PB23 PB25 PB26 PX03 PB27 PB28 RESET_N

Table 7-4. BGA144 Package Pinout A9..M12

9 10 11 12

PA26 PA25 PA24 PA23

PA27 PA21 GND PA22

ADVREF GNDANA PX19 PA19

PA18 PA20 DP DM

PX18 PX17 VDDIO VBUS

PA17 PX15 PA15 PA14

PA13 PA12 PA11 NC

PX11 PA08 VDDCORE VDDCORE

PX14 PA07 PX13 PA09

PX08 GND PA05 PX12

PX06 PX10 GND PA06

PX05 PX07 PX09 VDDIO

Note: NC is not connected.

8. I/O Line Considerations

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8.1 JTAG pins

TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

8.2 RESET_N pin

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product.

8.3 TWI pins

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as PIO pins.

8.4 GPIO pins

All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset State” of the GPIO Controller multiplexing tables.

AT32UC3A

9. Processor and Architecture

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This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual.

9.1 AVR32 Architecture

AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and half-word data types without penalty in code size and performance.

Memory load and store operations are provided for byte, half-word, word and double word data with automatic sign- or zero extension of half-word and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed.

AT32UC3A

In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution.

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions.

9.2 The AVR32UC CPU

The AVR32 UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented.

AVR32 UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs.

AT32UC3A

AVR32UC CPU pipeline

Instruction memory controller

High

Speed

Bus

master

MPU

High Speed Bus

OCD

system

OCD interface

Interrupt controller interface

High

Speed

Bus slave

High Speed Bus

Data RAM interface

High Speed Bus master

Power/

Reset

control

Reset interface

CPU Local

Bus

master

CPU Local Bus

Data memory controller

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A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the device-specific “Peripherals” chapter of this data sheet.

Figure 9-1 on page 22 displays the contents of AVR32UC.

Figure 9-1. Overview of the AVR32UC CPU

9.2.1 Pipeline Overview

AVR32 UC is a pipelined processor with three pipeline stages. There are three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID) and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section and one load/store (LS) section.

Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline.

Figure 9-2 on page 23 shows an overview of the AVR32 UC pipeline stages.

Figure 9-2. The AVR32UC Pipeline

IF ID ALU

MUL

Regfile

write

Prefetch unit Decode unit

ALU unit

Multiply unit

Load-store

unit

Regfile

Read

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9.2.2 AVR32A Microarchitecture Compliance

AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling.

AT32UC3A

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address.

9.2.3 Java Support

AVR32UC does not provide Java hardware acceleration.

9.2.4 Memory protection

The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.

9.2.5 Unaligned reference handling

AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses.

The following table shows the instructions with support for unaligned addresses. All other

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instructions require aligned addresses.

Table 9-1. Instructions with unaligned reference support

Instruction Supported alignment

ld.d Word st.d Word

9.2.6 Unimplemented instructions

The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed:

• All SIMD instructions

• All coprocessor instructions

• retj, incjosp, popjc, pushjc

• tlbr, tlbs, tlbw

• cache

9.2.7 CPU and Architecture revision

Two major revisions of the AVR32UC CPU currently exist. The device described in this datasheet uses CPU revision 2.

AT32UC3A

The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device.

AVR32UC CPU revision 2 is fully backward-compatible with revision 1, ie. code compiled for revision 1 is binary-compatible with revision 2 CPUs.

9.3 Programming Model

Application

Bit 0

Supe rv isor

Bit 31

INT0PC

FINTPC

INT1PC

SM PC

R4 R3

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

INT0

SP_APP SP_SYS

R12

R11

R10

Exce ption NMIINT1 INT2 INT3

LRLR

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

SP_SYS

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

SP_SYS

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

SP_SYS

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

SP_SYS

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

SP_SYS

Bit 0Bit 31

R12

INT0PC

FINTPC

INT1PC

SM PC

R11

R10

SP_SYS

Bit 31

0 0 0

Bit 16

Interrupt Level 0 Mask Interrupt Level 1 Mask

Interrupt Level 3 Mask

Interrupt Level 2 Mask

10 0 0 0 1 1 0 0 0 00 0

FE I0M GMM1- D M0 EM I2MDM - M2

Initial value

Bit name

I1M

Mode Bit 0 Mode Bit 1

Mode Bit 2 Reserved

Debug State

- I3M

Reserved

Exception Mask

Global Interrupt Mask

Debug State Mask

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9.3.1 Register file configuration

The AVR32UC register file is shown below.

Figure 9-3. The AVR32UC Register File

AT32UC3A

9.3.2 Status register configuration

The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 9-4 on

page 25 and Figure 9-5 on page 26. The lower word contains the C, Z, N, V and Q condition

code flags and the R, T and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.

Figure 9-4. The Status Register High Halfword

Figure 9-5. The Status Register Low Halfword

Bit 15 Bit 0

Reserved

Carry Zero Sign

0 0 0 00000000000

- - --TR Bit name

Initial value

0 0

L Q V N Z C-

Overflow Saturation

- - -

Lock

Scratch

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9.3.3 Processor States

9.3.3.1 Normal RISC State

The AVR32 processor supports several different execution contexts as shown in Table 9-2 on

page 26.

Table 9-2. Overview of execution modes, their priorities and privilege levels.

AT32UC3A

Priority Mode Security Description

1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode 2 Exception Privileged Execute exceptions 3 Interrupt 3 Privileged General purpose interrupt mode 4 Interrupt 2 Privileged General purpose interrupt mode 5 Interrupt 1 Privileged General purpose interrupt mode 6 Interrupt 0 Privileged General purpose interrupt mode N/A Supervisor Privileged Runs supervisor calls N/A Application Unprivileged Normal program execution mode

Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead.

When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode.

9.3.3.2 Debug State

The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available.

All interrupt levels are by default disabled when debug state is entered, but they can individually

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be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction.

9.3.4 System registers

The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual.

Table 9-3. System Registers

AT32UC3A

Reg # Address Name Function 0 0 SR Status Register 1 4 EVBA Exception Vector Base Address 2 8 ACBA Application Call Base Address 3 12 CPUCR CPU Control Register 4 16 ECR Exception Cause Register 5 20 RSR_SUP Unused in AVR32UC 6 24 RSR_INT0 Unused in AVR32UC 7 28 RSR_INT1 Unused in AVR32UC 8 32 RSR_INT2 Unused in AVR32UC 9 36 RSR_INT3 Unused in AVR32UC 10 40 RSR_EX Unused in AVR32UC 11 44 RSR_NMI Unused in AVR32UC 12 48 RSR_DBG Return Status Register for Debug Mode 13 52 RAR_SUP Unused in AVR32UC 14 56 RAR_INT0 Unused in AVR32UC 15 60 RAR_INT1 Unused in AVR32UC 16 64 RAR_INT2 Unused in AVR32UC 17 68 RAR_INT3 Unused in AVR32UC 18 72 RAR_EX Unused in AVR32UC 19 76 RAR_NMI Unused in AVR32UC 20 80 RAR_DBG Return Address Register for Debug Mode 21 84 JECR Unused in AVR32UC 22 88 JOSP Unused in AVR32UC 23 92 JAVA_LV0 Unused in AVR32UC 24 96 JAVA_LV1 Unused in AVR32UC 25 100 JAVA_LV2 Unused in AVR32UC

Table 9-3. System Registers (Continued)

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Reg # Address Name Function 26 104 JAVA_LV3 Unused in AVR32UC 27 108 JAVA_LV4 Unused in AVR32UC 28 112 JAVA_LV5 Unused in AVR32UC 29 116 JAVA_LV6 Unused in AVR32UC 30 120 JAVA_LV7 Unused in AVR32UC 31 124 JTBA Unused in AVR32UC 32 128 JBCR Unused in AVR32UC 33-63 132-252 Reserved Reserved for future use 64 256 CONFIG0 Configuration register 0 65 260 CONFIG1 Configuration register 1 66 264 COUNT Cycle Counter register 67 268 COMPARE Compare register 68 272 TLBEHI Unused in AVR32UC

AT32UC3A

69 276 TLBELO Unused in AVR32UC 70 280 PTBR Unused in AVR32UC 71 284 TLBEAR Unused in AVR32UC 72 288 MMUCR Unused in AVR32UC 73 292 TLBARLO Unused in AVR32UC 74 296 TLBARHI Unused in AVR32UC 75 300 PCCNT Unused in AVR32UC 76 304 PCNT0 Unused in AVR32UC 77 308 PCNT1 Unused in AVR32UC 78 312 PCCR Unused in AVR32UC 79 316 BEAR Bus Error Address Register 80 320 MPUAR0 MPU Address Register region 0 81 324 MPUAR1 MPU Address Register region 1 82 328 MPUAR2 MPU Address Register region 2 83 332 MPUAR3 MPU Address Register region 3 84 336 MPUAR4 MPU Address Register region 4 85 340 MPUAR5 MPU Address Register region 5 86 344 MPUAR6 MPU Address Register region 6 87 348 MPUAR7 MPU Address Register region 7 88 352 MPUPSR0 MPU Privilege Select Register region 0 89 356 MPUPSR1 MPU Privilege Select Register region 1 90 360 MPUPSR2 MPU Privilege Select Register region 2 91 364 MPUPSR3 MPU Privilege Select Register region 3

Table 9-3. System Registers (Continued)

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Reg # Address Name Function 92 368 MPUPSR4 MPU Privilege Select Register region 4 93 372 MPUPSR5 MPU Privilege Select Register region 5 94 376 MPUPSR6 MPU Privilege Select Register region 6 95 380 MPUPSR7 MPU Privilege Select Register region 7 96 384 MPUCRA Unused in this version of AVR32UC 97 388 MPUCRB Unused in this version of AVR32UC 98 392 MPUBRA Unused in this version of AVR32UC 99 396 MPUBRB Unused in this version of AVR32UC 100 400 MPUAPRA MPU Access Permission Register A 101 404 MPUAPRB MPU Access Permission Register B 102 408 MPUCR MPU Control Register 103-191 412-764 Reserved Reserved for future use 192-255 768-1020 IMPL IMPLEMENTATION DEFINED

AT32UC3A

9.4 Exceptions and Interrupts

AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class.

When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 9-4 on page 32. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme.

An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU.

9.4.1 System stack issues

Event handling in AVR32 UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic.

The user must also make sure that the system stack is large enough so that any event is able to

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push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state.

9.4.2 Exceptions and interrupt requests

When an event other than scall or debug request is received by the core, the following actions are performed atomically:

1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU.

2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2 or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source.

3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 9-4, is loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

AT32UC3A

9.4.3 Supervisor calls

9.4.4 Debug requests

The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete instruction returns from INT0, INT1, INT2 or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling.

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register.

The AVR32 architecture defines a dedicated debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the

status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the

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Debug Exception handler. By default, debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges.

Debug mode is exited by executing the retd instruction. This returns to the previous context.

9.4.5 Entry points for events

Several different event handler entry points exists. In AVR32 UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area.

TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly.

AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error.

AT32UC3A

All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes.

Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present.

If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 9-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A.

The addresses and priority of simultaneous events are shown in Table 9-4. Some of the exceptions are unused in AVR32 UC since it has no MMU, coprocessor interface or floating-point unit.

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Table 9-4. Priority and handler addresses for events

Priority Handler Address Name Event source Stored Return Address

1 0x8000_0000 Reset External input Undefined 2 Provided by OCD system OCD Stop CPU OCD system First non-completed instruction 3 EVBA+0x00 Unrecoverable exception Internal PC of offending instruction 4 EVBA+0x04 TLB multiple hit MPU 5 EVBA+0x08 Bus error data fetch Data bus First non-completed instruction 6 EVBA+0x0C Bus error instruction fetch Data bus First non-completed instruction 7 EVBA+0x10 NMI External input First non-completed instruction 8 Autovectored Interrupt 3 request External input First non-completed instruction 9 Autovectored Interrupt 2 request External input First non-completed instruction 10 Autovectored Interrupt 1 request External input First non-completed instruction 11 Autovectored Interrupt 0 request External input First non-completed instruction 12 EVBA+0x14 Instruction Address CPU PC of offending instruction 13 EVBA+0x50 ITLB Miss MPU 14 EVBA+0x18 ITLB Protection MPU PC of offending instruction 15 EVBA+0x1C Breakpoint OCD system First non-completed instruction 16 EVBA+0x20 Illegal Opcode Instruction PC of offending instruction 17 EVBA+0x24 Unimplemented instruction Instruction PC of offending instruction 18 EVBA+0x28 Privilege violation Instruction PC of offending instruction 19 EVBA+0x2C Floating-point UNUSED 20 EVBA+0x30 Coprocessor absent UNUSED 21 EVBA+0x100 Supervisor call Instruction PC(Supervisor Call) +2 22 EVBA+0x34 Data Address (Read) CPU PC of offending instruction 23 EVBA+0x38 Data Address (Write) CPU PC of offending instruction 24 EVBA+0x60 DTLB Miss (Read) MPU 25 EVBA+0x70 DTLB Miss (Write) MPU 26 EVBA+0x3C DTLB Protection (Read) MPU PC of offending instruction 27 EVBA+0x40 DTLB Protection (Write) MPU PC of offending instruction 28 EVBA+0x44 DTLB Modified UNUSED

10. Memories

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10.1 Embedded Memories

• Internal High-Speed Flash

– 512 KBytes (AT32UC3A0512, AT32UC3A1512) – 256 KBytes (AT32UC3A0256, AT32UC3A1256) – 128 KBytes (AT32UC3A1128, AT32UC3A2128)

- 0 Wait State Access at up to 33 MHz in Worst Case Conditions

- 1 Wait State Access at up to 66 MHz in Worst Case Conditions

- Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access

- Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation

- 100 000 Write Cycles, 15-year Data Retention Capability

- 4 ms Page Programming Time, 8 ms Chip Erase Time

- Sector Lock Capabilities, Bootloader Protection, Security Bit

- 32 Fuses, Erased During Chip Erase

- User Page For Data To Be Preserved During Chip Erase

• Internal High-Speed SRAM, Single-cycle access at full speed

– 64 KBytes (AT32UC3A0512, AT32UC3A0256, AT32UC3A1512, AT32UC3A1256) – 32KBytes (AT32UC3A1128)

10.2 Physical Memory Map

AT32UC3A

The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows:

Table 10-1. AT32UC3A Physical Memory Map

Device Start Address

Embedded SRAM 0x0000_0000 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 32 Kbyte 32 Kbyte Embedded Flash 0x8000_0000 512 Kbyte 512 Kbyte 256 Kbyte 256 Kbyte 128 Kbyte 128 Kbyte EBI SRAM CS0 0xC000_0000 16 Mbyte - 16 Mbyte - 16 Mbyte EBI SRAM CS2 0xC800_0000 16 Mbyte - 16 Mbyte - 16 Mbyte EBI SRAM CS3 0xCC00_0000 16 Mbyte - 16 Mbyte - 16 Mbyte EBI SRAM CS1

/SDRAM CS0 USB

Configuration HSB-PB Bridge A 0xFFFE_0000 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte HSB-PB Bridge B 0xFFFF_0000 64 Kbyte 64 Kbyte 64 kByte 64 kByte 64 Kbyte 64 Kbyte

0xD000_0000 128 Mbyte - 128 Mbyte - 128 Mbyte -

0xE000_0000 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte

Size

AT32UC3A0512 AT32UC3A1512 AT32UC3A0256 AT32UC3A1256 AT32UC3A0128 AT32UC3A1128

Table 10-2. Flash Memory Parameters

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General Purpose

Flash Size

Part Number

AT32UC3A0512 512 Kbytes 1024 128 words 32 fuses AT32UC3A1512 512 Kbytes 1024 128 words 32 fuses AT32UC3A0256 256 Kbytes 512 128 words 32 fuses AT32UC3A1256 256 Kbytes 512 128 words 32 fuses AT32UC3A1128 128 Kbytes 256 128 words 32 fuses AT32UC3A0128 128 Kbytes 256 128 words 32 fuses

(FLASH_PW)

Number of pages

(FLASH_P)

Page size

(FLASH_W)

10.3 Bus Matrix Connections

Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own

decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, MCFG0 is associated with the CPU Data master interface.

AT32UC3A

Fuse bits

(FLASH_F)

Table 10-3. High Speed Bus masters

Master 0 CPU Data Master 1 CPU Instruction Master 2 CPU SAB Master 3 PDCA Master 4 MACB DMA Master 5 USBB DMA

Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with the Internal SRAM Slave Interface.

Table 10-4. High Speed Bus slaves

Slave 0 Internal Flash Slave 1 HSB-PB Bridge 0 Slave 2 HSB-PB Bridge 1 Slave 3 Internal SRAM Slave 4 USBB DPRAM Slave 5 EBI

Figure 10-1. HMatrix Master / Slave Connections

CPU Data 0

CPU

Instruction

CPU SAB 2

PDCA 3

MACB 4

Internal Flash

HSB-PB

Bridge 01HSB-PB

Bridge 1

Internal SRAM

Slave

USBB Slave

EBI

USBB DMA 5

HMATRIX MASTERS

HMATRIX SLAVES

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11. Fuses Settings

The flash block contains a number of general purpose fuses. Some of these fuses have defined meanings outside the flash controller and are described in this section.

The general purpose fuses are erase by a JTAG chip erase.

11.1 Flash General Purpose Fuse Register (FGPFRLO)

Table 11-1. FGPFR Register Description

31 30 29 28 27 26 25 24

GPF31 GPF30 GPF29 BODEN BODHYST BODLEVEL[5:4]

23 22 21 20 19 18 17 16

BODLEVEL[3:0] BOOTPROT EPFL

15 14 13 12 11 10 9 8

LOCK[15:8]

7 6 5 4 3 2 1 0

LOCK[7:0]

BODEN: Brown Out Detector Enable Table 11-2. BODEN Field Description

BODEN Description

0x0 BOD disabled 0x1 BOD enabled, BOD reset enabled 0x2 BOD enabled, BOD reset disabled 0x3 BOD disabled

BODHYST: Brown Out Detector Hysteresis Table 11-3. BODEN Field Description

BODHYST

0b 1b he Brown out detector hysteresis is enabled.

Description

The Brown out detector hysteresis is disabled

BODLEVEL: Brown Out Detector Trigger Level

This controls the voltage trigger level for the Brown out detector. Refer to sectionTable 38-6 on

page 765 for values description. If the BODLEVEL is set higher than VDDCORE and enabled by

fuses, the part will be in constant reset. To recover from this situation, apply an external voltage on VDDCORE that is higher than the BOD level and disable the BOD.

LOCK, EPFL, BOOTPROT

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These are Flash controller fuses and are described in the FLASHC section.

11.2 Default Fuse Value

The devices are shipped with the FGPFRLO register value: 0xFC07FFFF:

• GPF31 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader.

• GPF30 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader.

• GPF29 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader.

• BODEN fuses set to 11b. BOD is disabled.

• BODHYST fuse set to 1b. The BOD hysteresis is enabled.

• BODLEVEL fuses set to 000000b. This is the minimum voltage trigger level for BOD.

• BOOTPROT fuses set to 011b. The bootloader protected size is 8 Ko.

• EPFL fuse set to 1b. External privileged fetch is not locked.

• LOCK fuses set to 1111111111111111b. No region locked. See also the AT32UC3A Bootloader user guide document.

AT32UC3A

After the JTAG chip erase command, the FGPFRLO register value is 0xFFFFFFFF.

12. Peripherals

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AVR32-01/12

12.1 Peripheral address map

Table 12-1. Peripheral Address Mapping

Address Peripheral Name Bus

AT32UC3A

0xE0000000

0xFFFE0000

0xFFFE1000

0xFFFE1400

0xFFFE1800

0xFFFE1C00

0xFFFE2000

0xFFFF0000

0xFFFF0800

0xFFFF0C00

USBB USBB Slave Interface - USBB HSB

USBB USBB Configuration Interface - USBB PBB

HMATRIX HMATRIX Configuration Interface - HMATRIX PBB

FLASHC Flash Controller - FLASHC PBB

MACB MACB Configuration Interface - MACB PBB

SMC

SDRAMC

Static Memory Controller Configuration Interface SMC

SDRAM Controller Configuration Interface SDRAMC

PBB

PDCA Peripheral DMA Interface - PDCA PBA

INTC Interrupt Controller Interface - INTC PBA

PM Power Manager - PM PBA

0xFFFF0D00

0xFFFF0D30

0xFFFF0D80

0xFFFF1000

0xFFFF1400

0xFFFF1800

RTC Real Time Clock - RTC PBA

WDT WatchDog Timer - WDT PBA

EIC External Interrupt Controller - EIC PBA

GPIO General Purpose IO Controller - GPIO PBA

USART0

USART1

Universal Synchronous Asynchronous Receiver Transmitter - USART0

Universal Synchronous Asynchronous Receiver Transmitter - USART1

PBA

Table 12-1. Peripheral Address Mapping (Continued)

32058K

AVR32-01/12

Address Peripheral Name Bus

AT32UC3A

0xFFFF1C00

0xFFFF2000

0xFFFF2400

0xFFFF2800

0xFFFF2C00

0xFFFF3000

0xFFFF3400

0xFFFF3800

0xFFFF3C00

USART2

USART3

SPI0 Serial Peripheral Interface - SPI0 PBA

SPI1 Serial Peripheral Interface - SPI1 PBA

TWI Two Wire Interface - TWI PBA

PWM Pulse Width Modulation Controller - PWM PBA

SSC Synchronous Serial Controller - SSC PBA

TC Timer/Counter - TC PBA

ADC Analog To Digital Converter - ADC PBA

Universal Synchronous Asynchronous Receiver Transmitter - USART2

Universal Synchronous Asynchronous Receiver Transmitter - USART3

PBA

12.2 CPU Local Bus Mapping

Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus.

Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers.

AT32UC3A

32058K

AVR32-01/12

The following GPIO registers are mapped on the local bus:

Table 12-2. Local bus mapped GPIO registers

Local Bus

Port Register Mode

0 Output Driver Enable Register (ODER) WRITE 0x4000_0040 Write-only

SET 0x4000_0044 Write-only CLEAR 0x4000_0048 Write-only TOGGLE 0x4000_004C Write-only

Output Value Register (OVR) WRITE 0x4000_0050 Write-only

SET 0x4000_0054 Write-only CLEAR 0x4000_0058 Write-only TOGGLE 0x4000_005C Write-only

Pin Value Register (PVR) - 0x4000_0060 Read-only

1 Output Driver Enable Register (ODER) WRITE 0x4000_0140 Write-only

SET 0x4000_0144 Write-only CLEAR 0x4000_0148 Write-only TOGGLE 0x4000_014C Write-only

Address Access

Output Value Register (OVR) WRITE 0x4000_0150 Write-only

SET 0x4000_0154 Write-only CLEAR 0x4000_0158 Write-only TOGGLE 0x4000_015C Write-only

Pin Value Register (PVR) - 0x4000_0160 Read-only

2 Output Driver Enable Register (ODER) WRITE 0x4000_0240 Write-only

SET 0x4000_0244 Write-only CLEAR 0x4000_0248 Write-only TOGGLE 0x4000_024C Write-only

Output Value Register (OVR) WRITE 0x4000_0250 Write-only

SET 0x4000_0254 Write-only CLEAR 0x4000_0258 Write-only TOGGLE 0x4000_025C Write-only

Pin Value Register (PVR) - 0x4000_0260 Read-only

Table 12-2. Local bus mapped GPIO registers

32058K

AVR32-01/12

Port Register Mode

3 Output Driver Enable Register (ODER) WRITE 0x4000_0340 Write-only

Output Value Register (OVR) WRITE 0x4000_0350 Write-only

Pin Value Register (PVR) - 0x4000_0360 Read-only

12.3 Interrupt Request Signal Map

The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantics of the different interrupt requests.

AT32UC3A

Local Bus Address Access

SET 0x4000_0344 Write-only CLEAR 0x4000_0348 Write-only TOGGLE 0x4000_034C Write-only

SET 0x4000_0354 Write-only CLEAR 0x4000_0358 Write-only TOGGLE 0x4000_035C Write-only

The interrupt request signals are connected to the INTC as follows.

Table 12-3. Interrupt Request Signal Map

Group Line Module Signal

0 0

0 External Interrupt Controller EIC 0 1 External Interrupt Controller EIC 1 2 External Interrupt Controller EIC 2 3 External Interrupt Controller EIC 3 4 External Interrupt Controller EIC 4 5 External Interrupt Controller EIC 5 6 External Interrupt Controller EIC 6 7 External Interrupt Controller EIC 7 8 Real Time Counter RTC 9 Power Manager PM

10 Frequency Meter FREQM

AVR32 UC CPU with optional MPU and optional OCD

SYSBLOCK

COMPARE

Table 12-3. Interrupt Request Signal Map

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AVR32-01/12

0 General Purpose Input/Output GPIO 0 1 General Purpose Input/Output GPIO 1 2 General Purpose Input/Output GPIO 2 3 General Purpose Input/Output GPIO 3 4 General Purpose Input/Output GPIO 4 5 General Purpose Input/Output GPIO 5 6 General Purpose Input/Output GPIO 6

7 General Purpose Input/Output GPIO 7 8 General Purpose Input/Output GPIO 8

9 General Purpose Input/Output GPIO 9 10 General Purpose Input/Output GPIO 10 11 General Purpose Input/Output GPIO 11 12 General Purpose Input/Output GPIO 12 13 General Purpose Input/Output GPIO 13

AT32UC3A

0 Peripheral DMA Controller PDCA 0

1 Peripheral DMA Controller PDCA 1

2 Peripheral DMA Controller PDCA 2

3 Peripheral DMA Controller PDCA 3

4 Peripheral DMA Controller PDCA 4

5 Peripheral DMA Controller PDCA 5

6 Peripheral DMA Controller PDCA 6

4 0 Flash Controller FLASHC

5 0

7 Peripheral DMA Controller PDCA 7

8 Peripheral DMA Controller PDCA 8

9 Peripheral DMA Controller PDCA 9 10 Peripheral DMA Controller PDCA 10 11 Peripheral DMA Controller PDCA 11 12 Peripheral DMA Controller PDCA 12 13 Peripheral DMA Controller PDCA 13 14 Peripheral DMA Controller PDCA 14

Universal Synchronous/Asynchronous Receiver/Transmitter

USART0

6 0

7 0

8 0

Universal Synchronous/Asynchronous Receiver/Transmitter

USART1

USART2

USART3

Table 12-3. Interrupt Request Signal Map

32058K

AVR32-01/12

12.4 Clock Connections

AT32UC3A

9 0 Serial Peripheral Interface SPI0 10 0 Serial Peripheral Interface SPI1 11 0 Two-wire Interface TWI 12 0 Pulse Width Modulation Controller PWM 13 0 Synchronous Serial Controller SSC

0 Timer/Counter TC0

15 0 Analog to Digital Converter ADC 16 0 Ethernet MAC MACB 17 0 USB 2.0 OTG Interface USBB 18 0 SDRAM Controller SDRAMC 19 0 Audio Bitstream DAC DAC

1 Timer/Counter TC1 2 Timer/Counter TC2

12.4.1 Timer/Counters

12.4.2 USARTs

Each Timer/Counter channel can independently select an internal or external clock source for its counter:

Table 12-4. Timer/Counter clock connections

Source Name Connection

Internal TIMER_CLOCK1 32 KHz Oscillator

TIMER_CLOCK2 PBA clock / 2 TIMER_CLOCK3 PBA clock / 8 TIMER_CLOCK4 PBA clock / 32 TIMER_CLOCK5 PBA clock / 128

External XC0 See Section 12.7

XC1 XC2

Each USART can be connected to an internally divided clock:

Table 12-5. USART clock connections

USART Source Name Connection

0 Internal CLK_DIV PBA clock / 8 1 2 3

12.4.3 SPIs

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AVR32-01/12

Each SPI can be connected to an internally divided clock:

Table 12-6. SPI clock connections

SPI Source Name Connection

0 Internal CLK_DIV PBA clock or 1

12.5 Nexus OCD AUX port connections

If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual.

Table 12-7. Nexus OCD AUX port connections

Pin AXS=0 AXS=1

EVTI_N PB19 PA08

AT32UC3A

PBA clock / 32

MDO[5] PB16 PA27 MDO[4] PB14 PA26 MDO[3] PB13 PA25 MDO[2] PB12 PA24 MDO[1] PB11 PA23 MDO[0] PB10 PA22 EVTO_N PB20 PB20 MCKO PB21 PA21 MSEO[1] PB04 PA07 MSEO[0] PB17 PA28

12.6 PDC handshake signals

The PDC and the peripheral modules communicate through a set of handshake signals. The following table defines the valid settings for the Peripheral Identifier (PID) in the PDC Peripheral Select Register (PSR).

Table 12-8. PDC Handshake Signals

PID Value Peripheral module & direction

0 ADC 1 SSC - RX 2 USART0 - RX 3 USART1 - RX

Table 12-8. PDC Handshake Signals

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AVR32-01/12

PID Value Peripheral module & direction

4 USART2 - RX 5 USART3 - RX 6 TWI - RX 7 SPI0 - RX 8 SPI1 - RX 9 SSC - TX 10 USART0 - TX 11 USART1 - TX 12 USART2 - TX 13 USART3 - TX 14 TWI - TX 15 SPI0 - TX 16 SPI1 - TX

AT32UC3A

17 ABDAC

12.7 Peripheral Multiplexing on I/O lines

Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C. The following table define how the I/O lines on the peripherals A, B and C are multiplexed by the GPIO.

Table 12-9. GPIO Controller Function Multiplexing

TQFP100 VQFP144 PIN GPIO Pin Function A Function B Function C

19 25 PA00 GPIO 0 USART0 - RXD TC - CLK0 20 27 PA01 GPIO 1 USART0 - TXD TC - CLK1 23 30 PA02 GPIO 2 USART0 - CLK TC - CLK2 24 32 PA03 GPIO 3 USART0 - RTS EIM - EXTINT[4] DAC - DATA[0] 25 34 PA04 GPIO 4 USART0 - CTS EIM - EXTINT[5] DAC - DATAN[0] 26 39 PA05 GPIO 5 USART1 - RXD PWM - PWM[4] 27 41 PA06 GPIO 6 USART1 - TXD PWM - PWM[5] 28 43 PA07 GPIO 7 USART1 - CLK PM - GCLK[0] SPI0 - NPCS[3] 29 45 PA08 GPIO 8 USART1 - RTS SPI0 - NPCS[1] EIM - EXTINT[7] 30 47 PA09 GPIO 9 USART1 - CTS SPI0 - NPCS[2] MACB - WOL 31 48 PA10 GPIO 10 SPI0 - NPCS[0] EIM - EXTINT[6] 33 50 PA11 GPIO 11 SPI0 - MISO USB - USB_ID 36 53 PA12 GPIO 12 SPI0 - MOSI USB - USB_VBOF 37 54 PA13 GPIO 13 SPI0 - SCK

39 56 PA14 GPIO 14

40 57 PA15 GPIO 15 SSC - TX_CLOCK SPI1 - SCK EBI - ADDR[20]

SSC -

TX_FRAME_SYNC

SPI1 - NPCS[0] EBI - NCS[0]

AT32UC3A

32058K

AVR32-01/12

Table 12-9. GPIO Controller Function Multiplexing

41 58 PA16 GPIO 16 SSC - TX_DATA SPI1 - MOSI EBI - ADDR[21] 42 60 PA17 GPIO 17 SSC - RX_DATA SPI1 - MISO EBI - ADDR[22] 43 62 PA18 GPIO 18 SSC - RX_CLOCK SPI1 - NPCS[1] MACB - WOL

44 64 PA19 GPIO 19

45 66 PA20 GPIO 20 EIM - EXTINT[8] SPI1 - NPCS[3] 51 73 PA21 GPIO 21 ADC - AD[0] EIM - EXTINT[0] USB - USB_ID 52 74 PA22 GPIO 22 ADC - AD[1] EIM - EXTINT[1] USB - USB_VBOF 53 75 PA23 GPIO 23 ADC - AD[2] EIM - EXTINT[2] DAC - DATA[1] 54 76 PA24 GPIO 24 ADC - AD[3] EIM - EXTINT[3] DAC - DATAN[1] 55 77 PA25 GPIO 25 ADC - AD[4] EIM - SCAN[0] EBI - NCS[0] 56 78 PA26 GPIO 26 ADC - AD[5] EIM - SCAN[1] EBI - ADDR[20] 57 79 PA27 GPIO 27 ADC - AD[6] EIM - SCAN[2] EBI - ADDR[21] 58 80 PA28 GPIO 28 ADC - AD[7] EIM - SCAN[3] EBI - ADDR[22] 83 122 PA29 GPIO 29 TWI - SDA USART2 - RTS 84 123 PA30 GPIO 30 TWI - SCL USART2 - CTS 65 88 PB00 GPIO 32 MACB - TX_CLK USART2 - RTS USART3 - RTS 66 90 PB01 GPIO 33 MACB - TX_EN USART2 - CTS USART3 - CTS 70 96 PB02 GPIO 34 MACB - TXD[0] DAC - DATA[0] 71 98 PB03 GPIO 35 MACB - TXD[1] DAC - DATAN[0] 72 100 PB04 GPIO 36 MACB - CRS USART3 - CLK EBI - NCS[3] 73 102 PB05 GPIO 37 MACB - RXD[0] DAC - DATA[1] 74 104 PB06 GPIO 38 MACB - RXD[1] DAC - DATAN[1] 75 106 PB07 GPIO 39 MACB - RX_ER 76 111 PB08 GPIO 40 MACB - MDC 77 113 PB09 GPIO 41 MACB - MDIO 78 115 PB10 GPIO 42 MACB - TXD[2] USART3 - RXD EBI - SDCK 81 119 PB11 GPIO 43 MACB - TXD[3] USART3 - TXD EBI - SDCKE 82 121 PB12 GPIO 44 MACB - TX_ER TC - CLK0 EBI - RAS 87 126 PB13 GPIO 45 MACB - RXD[2] TC - CLK1 EBI - CAS 88 127 PB14 GPIO 46 MACB - RXD[3] TC - CLK2 EBI - SDWE 95 134 PB15 GPIO 47 MACB - RX_DV 96 136 PB16 GPIO 48 MACB - COL USB - USB_ID EBI - SDA10 98 139 PB17 GPIO 49 MACB - RX_CLK USB - USB_VBOF EBI - ADDR[23] 99 141 PB18 GPIO 50 MACB - SPEED ADC - TRIGGER PWM - PWM[6]

100 143 PB19 GPIO 51 PWM - PWM[0] PM - GCLK[0] EIM - SCAN[4]

1 3 PB20 GPIO 52 PWM - PWM[1] PM - GCLK[1] EIM - SCAN[5] 2 5 PB21 GPIO 53 PWM - PWM[2] PM - GCLK[2] EIM - SCAN[6] 3 6 PB22 GPIO 54 PWM - PWM[3] PM - GCLK[3] EIM - SCAN[7] 6 9 PB23 GPIO 55 TC - A0 USART1 - DCD

SSC -

RX_FRAME_SYNC

SPI1 - NPCS[2]

AT32UC3A

32058K

AVR32-01/12

Table 12-9. GPIO Controller Function Multiplexing

7 11 PB24 GPIO 56 TC - B0 USART1 - DSR 8 13 PB25 GPIO 57 TC - A1 USART1 - DTR

9 14 PB26 GPIO 58 TC - B1 USART1 - RI 10 15 PB27 GPIO 59 TC - A2 PWM - PWM[4] 14 19 PB28 GPIO 60 TC - B2 PWM - PWM[5] 15 20 PB29 GPIO 61 USART2 - RXD PM - GCLK[1] EBI - NCS[2] 16 21 PB30 GPIO 62 USART2 - TXD PM - GCLK[2] EBI - SDCS 17 22 PB31 GPIO 63 USART2 - CLK PM - GCLK[3] EBI - NWAIT 63 85 PC00 GPIO 64 64 86 PC01 GPIO 65 85 124 PC02 GPIO 66 86 125 PC03 GPIO 67 93 132 PC04 GPIO 68 94 133 PC05 GPIO 69

1 PX00 GPIO 100 EBI - DATA[10] USART0 - RXD 2 PX01 GPIO 99 EBI - DATA[9] USART0 - TXD

4 PX02 GPIO 98 EBI - DATA[8] USART0 - CTS 10 PX03 GPIO 97 EBI - DATA[7] USART0 - RTS 12 PX04 GPIO 96 EBI - DATA[6] USART1 - RXD 24 PX05 GPIO 95 EBI - DATA[5] USART1 - TXD 26 PX06 GPIO 94 EBI - DATA[4] USART1 - CTS 31 PX07 GPIO 93 EBI - DATA[3] USART1 - RTS 33 PX08 GPIO 92 EBI - DATA[2] USART3 - RXD 35 PX09 GPIO 91 EBI - DATA[1] USART3 - TXD 38 PX10 GPIO 90 EBI - DATA[0] USART2 - RXD 40 PX11 GPIO 109 EBI - NWE1 USART2 - TXD 42 PX12 GPIO 108 EBI - NWE0 USART2 - CTS 44 PX13 GPIO 107 EBI - NRD USART2 - RTS 46 PX14 GPIO 106 EBI - NCS[1] TC - A0 59 PX15 GPIO 89 EBI - ADDR[19] USART3 - RTS TC - B0 61 PX16 GPIO 88 EBI - ADDR[18] USART3 - CTS TC - A1 63 PX17 GPIO 87 EBI - ADDR[17] TC - B1 65 PX18 GPIO 86 EBI - ADDR[16] TC - A2 67 PX19 GPIO 85 EBI - ADDR[15] EIM - SCAN[0] TC - B2 87 PX20 GPIO 84 EBI - ADDR[14] EIM - SCAN[1] TC - CLK0 89 PX21 GPIO 83 EBI - ADDR[13] EIM - SCAN[2] TC - CLK1 91 PX22 GPIO 82 EBI - ADDR[12] EIM - SCAN[3] TC - CLK2 95 PX23 GPIO 81 EBI - ADDR[11] EIM - SCAN[4] 97 PX24 GPIO 80 EBI - ADDR[10] EIM - SCAN[5]

Table 12-9. GPIO Controller Function Multiplexing

32058K

AVR32-01/12

99 PX25 GPIO 79 EBI - ADDR[9] EIM - SCAN[6]

101 PX26 GPIO 78 EBI - ADDR[8] EIM - SCAN[7] 103 PX27 GPIO 77 EBI - ADDR[7] SPI0 - MISO 105 PX28 GPIO 76 EBI - ADDR[6] SPI0 - MOSI 107 PX29 GPIO 75 EBI - ADDR[5] SPI0 - SCK 110 PX30 GPIO 74 EBI - ADDR[4] SPI0 - NPCS[0] 112 PX31 GPIO 73 EBI - ADDR[3] SPI0 - NPCS[1] 114 PX32 GPIO 72 EBI - ADDR[2] SPI0 - NPCS[2] 118 PX33 GPIO 71 EBI - ADDR[1] SPI0 - NPCS[3] 120 PX34 GPIO 70 EBI - ADDR[0] SPI1 - MISO 135 PX35 GPIO 105 EBI - DATA[15] SPI1 - MOSI 137 PX36 GPIO 104 EBI - DATA[14] SPI1 - SCK 140 PX37 GPIO 103 EBI - DATA[13] SPI1 - NPCS[0] 142 PX38 GPIO 102 EBI - DATA[12] SPI1 - NPCS[1] 144 PX39 GPIO 101 EBI - DATA[11] SPI1 - NPCS[2]

AT32UC3A

12.8 Oscillator Pinout

The oscillators are not mapped to the normal A,B or C functions and their muxings are controlled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this.

Table 12-10. Oscillator pinout

TQFP100 pin VQFP144 pin Pad Oscillator pin

85 124 PC02 xin0 93 132 PC04 xin1 63 85 PC00 xin32 86 125 PC03 xout0 94 133 PC05 xout1 64 86 PC01 xout32

12.9 USART Configuration

Table 12-11. USART Supported Mode

SPI RS485 ISO7816 IrDA Modem

USART0 Yes No No No No No

Manchester

Encoding

USART1 Yes Yes Yes Yes Yes Yes USART2 Yes No No No No No USART3 Yes No No No No No

12.10 GPIO

32058K

AVR32-01/12

The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device.

12.11 Peripheral overview

12.11.1 External Bus Interface

• Optimized for Application Memory Space support

• Integrates Two External Memory Controllers:

– Static Memory Controller – SDRAM Controller

• Optimized External Bus:

–16-bit Data Bus – 24-bit Address Bus, Up to 16-Mbytes Addressable – Optimized pin multiplexing to reduce latencies on External Memories

• 4 SRAM Chip Selects, 1SDRAM Chip Select:

– Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3

12.11.2 Static Memory Controller

AT32UC3A

• 4 Chip Selects Available

• 64-Mbyte Address Space per Chip Select

• 8-, 16-bit Data Bus

• Word, Halfword, Byte Transfers

• Byte Write or Byte Select Lines

• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

• Programmable Data Float Time per Chip Select

• Compliant with LCD Module

• External Wait Request

• Automatic Switch to Slow Clock Mode

• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

12.11.3 SDRAM Controller

• Numerous Configurations Supported

• Programming Facilities

• Energy-saving Capabilities

– 2K, 4K, 8K Row Address Memory Parts – SDRAM with Two or Four Internal Banks – SDRAM with 16-bit Data Path

– Word, Half-word, Byte Access – Automatic Page Break When Memory Boundary Has Been Reached – Multibank Ping-pong Access – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable

– Self-refresh, Power-down and Deep Power Modes Supported

– Supports Mobile SDRAM Devices

32058K

AVR32-01/12

• Error Detection

– Refresh Error Interrupt

• SDRAM Power-up Initialization by Software

• CAS Latency of 1, 2, 3 Supported

• Auto Precharge Command Not Used

12.11.4 USB Controller

• USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s

• 7 Pipes/Endpoints

• 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints

• Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)

• Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels

• On-Chip Transceivers Including Pull-Ups

12.11.5 Serial Peripheral Interface

• Supports communication with serial external devices

– Four chip selects with external decoder support allow communication with up to 15

peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data

per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection

• Very fast transfers supported

– Transfers with baud rates up to Peripheral Bus A (PBA) max frequency – The chip select line may be left active to speed up transfers on the same device

12.11.6 Two-wire Interface

AT32UC3A

• High speed up to 400kbit/s

• Compatibility with standard two-wire serial memory

• One, two or three bytes for slave address

• Sequential read/write operations

12.11.7 USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection

– Optional Manchester Encoding

32058K

AVR32-01/12

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

• SPI Mode

– Master or Slave – Serial Clock Programmable Phase and Polarity – SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency PBA/4

• Supports Connection of Two Peripheral DMA Controller Channels (PDC)

– Offers Buffer Transfer without Processor Intervention

12.11.8 Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications (with

CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of different

event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

12.11.9 Timer Counter

AT32UC3A

• Three 16-bit Timer Counter Channels

• Wide range of functions including:

– Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals

• Two global registers that act on all three TC Channels

12.11.10 Pulse Width Modulation Controller

• 7 channels, one 20-bit counter per channel

• Common clock generator, providing Thirteen Different Clocks

– A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs

• Independent channel programming

– Independent Enable Disable Commands – Independent Clock – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform

12.11.11 Ethernet 10/100 MAC

32058K

AVR32-01/12

• Compatibility with IEEE Standard 802.3

• 10 and 100 Mbits per second data throughput capability

• Full- and half-duplex operations

• MII or RMII interface to the physical layer

• Register Interface to address, data, status and control registers

• DMA Interface, operating as a master on the Memory Controller

• Interrupt generation to signal receive and transmit completion

• 28-byte transmit and 28-byte receive FIFOs

• Automatic pad and CRC generation on transmitted frames

• Address checking logic to recognize four 48-bit addresses

• Support promiscuous mode where all valid frames are copied to memory

• Support physical layer management through MDIO interface control of alarm and update

time/calendar data

12.11.12 Audio Bitstream DAC

• Digital Stereo DAC

• Oversampled D/A conversion architecture

– Oversampling ratio fixed 128x – FIR equalization filter – Digital interpolation filter: Comb4 – 3rd Order Sigma-Delta D/A converters

• Digital bitstream outputs

• Parallel interface

• Connected to Peripheral DMA Controller for background transfer without CPU intervention

AT32UC3A

13. Power Manager (PM)

32058K

AVR32-01/12

Rev: 2.0.0.1

13.1 Features

• Controls integrated oscillators and PLLs

• Generates clocks and resets for digital logic

• Supports 2 crystal oscillators 450 kHz-16 MHz

• Supports 2 PLLs 80-240 MHz

• Supports 32 KHz ultra-low power oscillator

• Integrated low-power RC oscillator

• On-the fly frequency change of CPU, HSB, PBA, and PBB clocks

• Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators

• Module-level clock gating through maskable peripheral clocks

• Wake-up from internal or external interrupts

• Generic clocks with wide frequency range provided

• Automatic identification of reset sources

• Controls brownout detector (BOD), RC oscillator, and bandgap voltage reference through control

and calibration registers

13.2 Description

AT32UC3A

The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power 32 KHz oscillator is used to generate the real-time counter clock for high accuracy real-time measurements. The PM also contains a low-power RC oscillator with fast start-up time, which can be used to clock the digital logic.

The provided clocks are divided into synchronous and generic clocks. The synchronous clocks are used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous clocks, which can be tuned precisely within a wide frequency range, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules.

The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into three clock domains, one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB bus.The three clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-the-fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals.

Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically switched off during idle periods by using the sleep instruction on the CPU. The system will return to normal on occurrence of interrupts.

The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software.

13.3 Block Diagram

Sleep Controller

Oscillator and

PLL Control

PLL0

PLL1

Synchronous

Clock Generator

Generic Clock

Generator

Reset Controller

Oscillator 0

Oscillator 1

Oscillator

Startup

Counter

Slow clock

Sleep

instruction

Power-On

Detector

Other reset

sources

resets

Generic clocks

Synchronous

clocks

CPU, HSB,

PBA, PBB

OSC/PLL

Control signals

RCOSC

32 KHz

Oscillator

32 KHz clock

for RTC

Interrupts

External Reset Pad

Calibration

Registers

Brown-Out

Detector

Voltage Regulator

fuses

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AT32UC3A

Figure 13-1. Power Manager block diagram

13.4 Product Dependencies

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13.4.1 I/O Lines

The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the GPIO controller.

13.4.2 Interrupt

The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first.

13.4.3 Clock implementation

In AT32UC3A, the HSB shares the source clock with the CPU. This means that writing to the HSBDIV and HSBSEL bits in CKSEL has no effect. These bits will always read the same as CPUDIV and CPUSEL.

13.5 Functional Description

13.5.1 Slow clock

AT32UC3A

The slow clock is generated from an internal RC oscillator which is always running, except in Static mode. The slow clock can be used for the main clock in the device, as described in ”Syn-

chronous clocks” on page 58. The slow clock is also used for the Watchdog Timer and

measuring various delays in the Power Manager. The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running.

The RC oscillator operates at approximately 115 kHz, and can be calibrated to a narrow range by the RCOSCCAL fuses. Software can also change RC oscillator calibration through the use of the RCCR register. Please see the Electrical Characteristics section for details.

RC oscillator can also be used as the RTC clock when crystal accuracy is not required.

13.5.2 Oscillator 0 and 1 operation

The two main oscillators are designed to be used with an external 450 kHz to 16 MHz crystal and two biasing capacitors, as shown in Figure 13-2. Oscillator 0 can be used for the main clock in the device, as described in ”Synchronous clocks” on page 58. Both oscillators can be used as source for the generic clocks, as described in ”Generic clocks” on page 61.

The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a general purpose I/O.

The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode (external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are automatically switched off in certain sleep modes to reduce power consumption, as described in

Section 13.5.7 on page 60.

After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscillators may need a certain amount of time to stabilize on the correct frequency. This start-up time can be set in the OSCCTRLn register.

AT32UC3A

XIN

XOUT

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The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in ”Interrupt Enable/Disable/Mask/Status/Clear” on

page 76.

Figure 13-2. Oscillator connections

13.5.3 32 KHz oscillator operation

The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter.

The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode.

While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin can be used as a general purpose I/O.

The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY.

As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz oscillator will keep running across resets, except Power-On-Reset.

13.5.4 PLL operation

The device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its output frequency until the two compared clocks are equal, thus locking the output frequency to a multiple of the reference clock frequency.

The Voltage Controlled Oscillator inside the PLL can generate frequencies from 80 to 240 MHz. To make the PLL output frequencies under 80 MHz the OTP[1] bitfield could be set. This will

AT32UC3A

Phase

Detector

Output

Divider

Osc0 clock

Osc1 clock

PLLOSC

PLLOPT

PLLMU L

Lock bit

Mask

PLL clock

In p ut

D ivider

PLLDIV

1/2

PLLOPT[1]

VC O

vco

PLL

Lock

Detector

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divide the output of the PLL by two and bring the clock in range of the max frequency of the CPU.

When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable.

Figure 13-3. PLL with control logic and filters

13.5.4.1 Enabling the PLL

PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and division factors, respectively, creating the voltage controlled ocillator frequency f frequency f

If PLLOPT[1] field is set to 0:

If PLLOPT[1] field is set to 1:

The PLLn:PLLOPT field should be set to proper values according to the PLL operating frequency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.

The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be generated on a 0 to 1 transition of these bits.

PLL

= (PLLMUL+1)/(PLLDIV) • f

VCO

= 2*(PLLMUL+1) • f

VCO

= f

PLL

= f

PLL

VCO.

VCO

/ 2

OSC

if PLLDIV = 0.

OSC

if PLLDIV > 0.

and the PLL

VCO

13.5.5 Synchronous clocks

Mask

Prescaler

Osc0 clock PLL0 clock

MCSEL

CPUSEL

CPUDIV

Main clock

Sleep

Controller

CPUMASK

CPU clocks HSB clocks

PBAclocks

PBB clocks

Sleep

instruction

Slow clock

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The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as f nous clock source can be changed on-the fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in ”Sleep modes” on page 60. Additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules.

AT32UC3A

CPU

f

. The synchro-

PBA,B,

Figure 13-4. Synchronous clock generation

13.5.5.1 Selecting PLL or oscillator for the main clock

The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default, the main clock will be connected to the slow clock. The user can connect the main clock to Oscillator 0 or PLL0 by writing the MCSEL bitfield in the Main Clock Control Register (MCCTRL). This must only be done after that unit has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.

13.5.5.2 Selecting synchronous clock division ratio

The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a pres-

caler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling

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value, resulting in a CPU clock frequency:

CPU

Similarly, the clock for the PBA, and PBB can be divided by writing their respective bitfields. To ensure correct operation, frequencies must be selected so that f must never exceed the specified maximum frequency for each clock domain.

CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL bitfields. This way, it is possible to e.g. scale CPU and HSB speed according to the required performance, while keeping the PBA and PBB frequency constant.

13.5.5.3 Clock Ready flag

There is a slight delay from CKSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER:CKRDY is written to 1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang.

13.5.6 Peripheral clock masking

= f

main

(CPUSEL+1)

/ 2

CPU

AT32UC3A

f

. Also, frequencies

PBA,B

By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0. When a module is not clocked, it will cease operation, and its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to 1.

A module may be connected to several clock domains, in which case it will have several mask bits.

Table 13-5 contains a list of implemented maskable clocks.

13.5.6.1 Cautionary note

Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the internal RAM will cause a problem if the stack is mapped there. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

13.5.6.2 Mask Ready flag

Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information. When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the MSKRDY bit in IER.

13.5.7 Sleep modes

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In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument.

13.5.7.1 Entering and exiting sleep modes

The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings of the mask registers.

Oscillators and PLLs can also be switched off to save power. Some of these modules have a relatively long start-up time, and are only switched off when very low power consumption is required.

The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked.

13.5.7.2 Supported sleep modes

The following sleep modes are supported. These are detailed in Table 13-1.

AT32UC3A

•Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt.

•Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupt from PB modules.

•Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing quick wake-up to normal mode. Wake-up sources are RTC or external interrupt (EIC).

•Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and RC oscillators and RTC/WDT still operate. Wake-up sources are RTC, external interrupt (EIC), or external reset pin.

•DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference and BOD is turned off. Wake-up sources are RTC, external interrupt (EIC) or external reset pin.

•Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage reference BOD detector is turned off. Wake-up sources are external interrupt (EIC) in asynchronous mode only or external reset pin.

Table 13-1. Sleep modes

PBA,B

Index Sleep Mode CPU HSB

0 Idle Stop Run Run Run Run Run On Full power 1 Frozen Stop Stop Run Run Run Run On Full power

GCLK

Osc0,1 PLL0,1 Osc32 RCOsc

BOD & Bandgap

Voltage Regulator

2 Standby Stop Stop Stop Run Run Run On Full power 3 Stop Stop Stop Stop Stop Run Run On Low power 4 DeepStop Stop Stop Stop Stop Run Run Off Low power 5 Static Stop Stop Stop Stop Stop Stop Off Low power

The power level of the internal voltage regulator is also adjusted according to the sleep mode to

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reduce the internal regulator power consumption.

13.5.7.3 Precautions when entering sleep mode

Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions.

Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction.

The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary.

When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete.

AT32UC3A

13.5.7.4 Wake up

13.5.8 Generic clocks

The USB can be used to wake up the part from sleep modes through register PM_AWEN of the Power Manager.

Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The Power Manager contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies.

Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller.

Figure 13-5. Generic clock generation

Divider

Osc0 clock

PLL0 clock

PLLSEL

OSCSEL

Osc1 clock

PLL1 clock

Generic Clock

DIV

DIVEN

Mask

CEN

Sleep

Controller

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AT32UC3A

13.5.8.1 Enabling a generic clock

A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits. The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency:

GCLK

13.5.8.2 Disabling a generic clock

The generic clock can be disabled by writing CEN to 0 or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as 1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0, the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the generic clock.

When the clock is disabled, both the prescaler and output are reset.

13.5.8.3 Changing clock frequency

When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition.

= f

SRC

/ (2*(DIV+1))

13.5.8.4 Generic clock implementation

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In AT32UC3A, there are 6 generic clocks. These are allocated to different functions as shown in

Table 13-2.

Table 13-2. Generic clock allocation

Clock number Function

0 GCLK0 pin 1 GCLK1 pin 2 GCLK2 pin 3 GCLK3 pin 4 USBB 5 ABDAC

13.5.9 Divided PB clocks

The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules.

AT32UC3A

The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx clocks are stopped.

13.5.10 Debug operation

During a debug session, the user may need to halt the system to inspect memory and CPU registers. The clocks normally keep running during this debug operation, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx clocks. This is described in the documentation for the relevant modules. The divided PBx clocks are always debug qualified clocks.

Debug qualified PB clocks are stopped during debug operation. The debug system can optionally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system.

13.5.11 Reset Controller

The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic.

The device contains a Power-On Detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device.

AT32UC3A

JTAG

Reset

Controller

RESET_N

Power-O n

Detector

OCD

W atchdog Reset

RC_RCAUSE

CPU, HSB,

PBA, PBB

OCD, RTC/W DT

Clock Generato

Brownout

Detector

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It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated. Table 13-4 lists these and other reset sources supported by the Reset Controller.

Figure 13-6. Reset Controller block diagram

In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details.

Table 13-3. Reset description

Reset source Description

Power-on Reset Supply voltage below the power-on reset detector threshold

voltage External Reset RESET_N pin asserted Brownout Reset Supply voltage below the brownout reset detector threshold

voltage CPU Error Caused by an illegal CPU access to external memory while

in Supervisor mode Watchdog Timer See watchdog timer documentation. OCD See On-Chip Debug documentation

When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. Only the Power On Reset (POR) will force a reset of the whole chip.

Table 13-4 lists parts of the device that are reset, depending on the reset source.

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Table 13-4. Effect of the different reset events

AT32UC3A

Power-On Reset

CPU/HSB/PBA/PBB (excluding Power Manager)

32 KHz oscillator Y N N N N N RTC control register Y N N N N N GPLP registers Y N N N N N Watchdog control register Y Y N Y Y Y

Y Y Y Y Y Y

External Reset

Watchdog Reset

BOD Reset

CPU Error Reset

OCD Reset

Voltage Calibration register Y N N N N N

RC Oscillator Calibration register Y N N N N N BOD control register Y Y N N N N Bandgap control register Y Y N N N N Clock control registers Y Y Y Y Y Y Osc0/Osc1 and control registers Y Y Y Y Y Y PLL0/PLL1 and control registers Y Y Y Y Y Y OCD system and OCD registers Y Y N Y Y N

The cause of the last reset can be read from the RCAUSE register. This register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken.

13.5.11.1 Power-On Detector

The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The reset will be re-activated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details.

13.5.11.2 Brown-Out Detector

The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD:LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses. The Brown-Out Detector can either generate an interrupt or a reset when the supply voltage is below the brown-out detection level. In any case, the BOD output is available in bit POSCR:BODET bit.

Note that any change to the BOD:LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt.

See Electrical Characteristics for parametric details.

13.5.11.3 External Reset

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The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset.

13.5.12 Calibration registers

The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap voltage reference through several calibrations registers.

Those calibration registers are loaded after a Power On Reset with default values stored in factory-programmed flash fuses.

Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to these registers is protected by a “key”. First, a write to the register must be made with the field “KEY” equal to 0x55 then a second write must be issued with the “KEY” field equal to 0xAA

13.6 User Interface

AT32UC3A

Offset Register Name Access Reset State

0x0000 Main Clock Control MCCTRL Read/Write 0x00000000 0x0004 Clock Select CKSEL Read/Write 0x00000000 0x0008 CPU Mask CPUMASK Read/Write 0x00000003 0x000C HSB Mask HSBMASK Read/Write 0x0000007F 0x0010 PBA Mask PBAMASK Read/Write 0x0000FFFF 0x0014 PBB Mask PBBMASK Read/Write 0x0000003F 0x0018 - 0x001C Reserved 0x0020 PLL0 Control PLL0 Read/Write 0x00000000 0x0024 PLL1 Control PLL1 Read/Write 0x00000000 0x0028 Oscillator 0 Control Register OSCCTRL0 Read/Write 0x00000000 0x002C Oscillator 1 Control Register OSCCTRL1 Read/Write 0x00000000 0x0030 Oscillator 32 Control Register OSCCTRL32 Read/Write 0x00000000 0x0034 Reserved 0x0038 Reserved 0x003C Reserved 0x0040 PM Interrupt Enable Register IER Write Only 0x00000000 0x0044 PM Interrupt Disable Register IDR Write Only 0x00000000 0x0048 PM Interrupt Mask Register IMR Read Only 0x00000000 0x004C PM Interrupt Status Register ISR Read Only 0x00000000 0x0050 PM Interrupt Clear Register ICR Write Only 0x00000000 0x0054 Power and Oscillators Status Register POSCSR Read/Write 0x00000000 0x0058 - 0x005C Reserved

AT32UC3A

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0x0060 Generic Clock Control GCCTRL Read/Write 0x00000000 0x0064 - 0x00BC Reserved 0x00C0 RC Oscillator Calibration Register RCCR Read/Write Factory settings 0x00C4 Bandgap Calibration Register BGCR Read/Write Factory settings 0x00C8 Linear Regulator Calibration Register VREGCR Read/Write Factory settings 0x00CC Reserved 0x00D0 BOD Level Register BOD Read/Write BOD fuses in Flash 0x00D4 - 0x013C Reserved 0x0140 Reset Cause Register RCAUSE Read Only Latest Reset Source 0x0144 - 0x01FC Reserved 0x0200 General Purpose Low-Power register 0 GPLP0 Read/Write 0x00000000 0x0204 General Purpose Low-Power register 1 GPLP1 Read/Write 0x00000000

13.6.1 Main Clock Control

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Name: MCCTRL Access Type: Read/Write

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - -

15 14 13 12 11 10 9 8

- - - - - - - -

7 6 5 4 3 2 1 0

AT32UC3A

- - OSC1EN OSC0EN MCSEL

• MCSEL: Main Clock Select

0: The slow clock is the source for the main clock 1: Oscillator 0 is source for the main clock 2: PLL0 is source for the main clock 3: Reserved

• OSC0EN: Oscillator 0 Enable

0: Oscillator 0 is disabled 1: Oscillator 0 is enabled

• OSC1EN: Oscillator 1 Enable

0: Oscillator 1is disabled 1: Oscillator 1is enabled

13.6.2 Clock Select

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Name: CKSEL Access Type: Read/Write

31 30 29 28 27 26 25 24

PBBDIV - - - - PBBSEL

23 22 21 20 19 18 17 16

PBADIV - - - - PBASEL

15 14 13 12 11 10 9 8

HSBDIV - - - - HSBSEL

7 6 5 4 3 2 1 0

AT32UC3A

CPUDIV - - - - CPUSEL

• PBBDIV, PBBSEL: PBB Division and Clock Select

PBBDIV = 0: PBB clock equals main clock. PBBDIV = 1: PBB clock equals main clock divided by 2

(PBBSEL+1)

• PBADIV, PBASEL: PBA Division and Clock Select

PBADIV = 0: PBA clock equals main clock. PBADIV = 1: PBA clock equals main clock divided by 2

(PBASEL+1)

• HSBDIV, HSBSEL: HSB Division and Clock Select

For the AT32UC3A, HSBDIV always equals CPUDIV, and HSBSEL always equals CPUSEL, as the HSB clock is always equal to the CPU clock.

• CPUDIV, CPUSEL: CPU Division and Clock Select

CPUDIV = 0: CPU clock equals main clock. CPUDIV = 1: CPU clock equals main clock divided by 2

(CPUSEL+1)

Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation. Also note that writing this register clears POSCSR:CKRDY. The register must not be re-written until CKRDY goes high.

13.6.3 Clock Mask

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Name: CPU/HSB/PBA/PBBMASK Access Type: Read/Write

31 30 29 28 27 26 25 24

MASK[31:24]

23 22 21 20 19 18 17 16

MASK[23:16]

15 14 13 12 11 10 9 8

MASK[15:8]

7 6 5 4 3 2 1 0

AT32UC3A

MASK[7:0]

• MASK: Clock Mask

If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in Table 13-5.

Table 13-5. Maskable module clocks in AT32UC3A.

Bit CPUMASK HSBMASK PBAMASK PBBMASK

0 - FLASHC INTC HMATRIX 1 OCD PBA bridge GPIO USBB 2 - PBB bridge PDCA FLASHC 3 - USBB PM/RTC/EIC MACB 4 - MACB ADC SMC 5 - PDCA SPI0 SDRAMC 6 - EBI SPI1 7 - - TWI 8 - - USART0 -

9 - - USART1 10 - - USART2 11 - - USART3 12 - - PWM 13 - - SSC -

Table 13-5. Maskable module clocks in AT32UC3A.

32058K

AVR32-01/12

Bit CPUMASK HSBMASK PBAMASK PBBMASK

14 - - TC 15 - - ABDAC -

AT32UC3A

16 SYSTIMER

(COMPARE/COUNT

REGISTERS CLK)

31:

- - - -

- - -

13.6.4 PLL Control

32058K

AVR32-01/12

Name: PLL0,1 Access Type: Read/Write

31 30 29 28 27 26 25 24

RESERVED PLLCOUNT

23 22 21 20 19 18 17 16

RESERVED PLLMUL

15 14 13 12 11 10 9 8

RESERVED PLLDIV

7 6 5 4 3 2 1 0

AT32UC3A

- - - PLLOPT PLLOSC PLLEN

• RESERVED: Reserved bitfields

Reserved for internal use. Always write to 0.

• PLLCOUNT: PLL Count

Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode.

• PLLMUL: PLL Multiply Factor

• PLLDIV: PLL Division Factor

These bitfields determine the ratio of the PLL output frequency (voltage controlled oscillator frequency f oscillator frequency:

= (PLLMUL+1)/(PLLDIV) • f

VCO

= 2*(PLLMUL+1) • f

VCO

OSC

If PLLOPT[1] field is set to 0:

= f

VCO.

PLL

If PLLOPT[1] field is set to 1: f

= f

VCO

/ 2

PLL

Note that the MUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.

• PLLOPT: PLL Option

Select the operating range for the PLL. PLLOPT[0]: Select the VCO frequency range. PLLOPT[1]: Enable the extra output divider. PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).

if PLLDIV > 0.

OSC

if PLLDIV = 0.

) to the source

VCO

Table 13-6. PLLOPT Fields Description in AT32UC3A

32058K

AVR32-01/12

Description

PLLOPT[0]: VCO frequency

AT32UC3A

0 160MHz<f 1 80MHz<f

PLLOPT[1]: Output divider

0 f 1 f

PLLOPT[2]

0 Wide Bandwidth Mode enabled 1 Wide Bandwidth Mode disabled

• PLLOSC: PLL Oscillator Select

0: Oscillator 0 is the source for the PLL. 1: Oscillator 1 is the source for the PLL.

• PLLEN: PLL Enable

0: PLL is disabled. 1: PLL is enabled.

PLL

= f

vco

<240MHz

vco

<180MHz

13.6.5 PM Oscillator 0/1 Control

32058K

AVR32-01/12

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - -

15 14 13 12 11 10 9 8

- - - - - STARTUP

7 6 5 4 3 2 1 0

- - - - - MODE

AT32UC3A

• MODE: Oscillator Mode Choose between crystal, or external clock

0: External clock connected on XIN, XOUT can be used as an I/O (no crystal) 1 to 3: reserved 4: Crystal is connected to XIN/XOUT - Oscillator is used with gain G0 ( XIN from 5: Crystal is connected to XIN/XOUT - Oscillator is used with gain G1 ( XIN from 0.9 MHz to 3.0 MHz ). 6: Crystal is connected to XIN/XOUT - Oscillator is used with gain G2 ( XIN from 3.0 MHz to 8.0 MHz ). 7: Crystal is connected to XIN/XOUT - Oscillator is used with gain G3 ( XIN from 8.0 Mhz).

• STARTUP: Oscillator Startup Time Select startup time for the oscillator.

Table 13-7. Startup time for oscillators 0 and 1

Number of RC oscillator

STARTUP

0 0 0 1 64 560 us 2 128 1.1 ms 3 2048 18 ms 4 4096 36 ms 5 8192 71 ms

clock cycle

0.4 MHz to 0.9 MHz ).

Approximative Equivalent time (RCOsc = 115 kHz)

6 16384 142 ms 7 Reserved Reserved

13.6.6 PM 32 KHz Oscillator Control Register

32058K

AVR32-01/12

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - STARTUP

15 14 13 12 11 10 9 8

- - - - - MODE

7 6 5 4 3 2 1 0

- - - - - - - OSC32EN

AT32UC3A

Note: This register is only reset by Power-On Reset

• OSC32EN: Enable the 32 KHz oscillator

0: 32 KHz Oscillator is disabled 1: 32 KHz Oscillator is enabled

• MODE: Oscillator Mode Choose between crystal, or external clock

0: External clock connected on XIN32, XOUT32 can be used as a I/O (no crystal) 1: Crystal is connected to XIN32/XOUT32 2 to 7: reserved

• STARTUP: Oscillator Startup Time Select startup time for 32 KHz oscillator

Table 13-8. Startup time for 32 KHz oscillator

Number of RC oscillator

STARTUP

0 0 0 1 128 1.1 ms 2 8192 72.3 ms 3 16384 143 ms

clock cycle

Approximative Equivalent time (RCOsc = 115 kHz)

4 65536 570 ms 5 131072 1.1 s 6 262144 2.3 s 7 524288 4.6 s

AT32UC3A

32058K

AVR32-01/12

13.6.7 Interrupt Enable/Disable/Mask/Status/Clear Name: IER/IDR/IMR/ISR/ICR

Access Type: IER/IDR/ICR: Write-only

IMR/ISR: Read-only

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - BODDET

15 14 13 12 11 10 9 8

- - - - - - OSC32RDY OSC1RDY

7 6 5 4 3 2 1 0

OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0

BODDET: Brown out detection

•

Set to 1 when 0 to 1 transition on POSCSR:BODDET bit is detected: BOD has detected that power supply is going below

BOD reference value.

• OSC32RDY: 32 KHz oscillator Ready

Set to 1 when 0 to 1 transition on the POSCSR:OSC32RDY bit is detected: The 32 KHz oscillator is stable and ready to be

used as clock source.

• OSC1RDY: Oscillator 1 Ready

Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used as

clock source.

• OSC0RDY: Oscillator 0 Ready

Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used as

clock source.

• MSKRDY: Mask Ready

Set to 1 when 0 to 1 transition on the POSCSR:MSKRDY bit is detected: Clocks are now masked according to the

(CPU/HSB/PBA/PBB)_MASK registers.

• CKRDY: Clock Ready

0: The CKSEL register has been written, and the new clock setting is not yet effective. 1: The synchronous clocks have frequencies as indicated in the CKSEL register. Note: Writing ICR:CKRDY to 1 has no effect.

• LOCK1: PLL1 locked

Set to 1 when 0 to 1 transition on the POSCSR:LOCK1 bit is detected: PLL 1 is locked and ready to be selected as clock

source.

• LOCK0: PLL0 locked

Set to 1 when 0 to 1 transition on the POSCSR:LOCK0 bit is detected: PLL 0 is locked and ready to be selected as clock

source.

The effect of writing or reading the bits listed above depends on which register is being accessed:

32058K

AVR32-01/12

• IER (Write-only)

0: No effect 1: Enable Interrupt

• IDR (Write-only)

0: No effect 1: Disable Interrupt

• IMR (Read-only)

0: Interrupt is disabled 1: Interrupt is enabled

• ISR (Read-only)

0: An interrupt event has not occurred or has been previously cleared 1: An interrupt event has not occurred

• ICR (Write-only)

0: No effect 1: Clear corresponding event

AT32UC3A

32058K

AVR32-01/12

13.6.8 Power and Oscillators Status Name: POSCSR

Access Type: Read-only

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - BODDET

15 14 13 12 11 10 9 8

- - - - - - OSC32RDY OSC1RDY

7 6 5 4 3 2 1 0

OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0

BODDET: Brown out detection

•

0: No BOD event 1: BOD has detected that power supply is going below BOD reference value.

• OSC32RDY: 32 KHz oscillator Ready

0: The 32 KHz oscillator is not enabled or not ready. 1: The 32 KHz oscillator is stable and ready to be used as clock source.

•

OSC1RDY: OSC1 ready

0: Oscillator 1 not enabled or not ready. 1: Oscillator 1 is stable and ready to be used as clock source.

• OSC0RDY: OSC0 ready

0: Oscillator 0 not enabled or not ready. 1: Oscillator 0 is stable and ready to be used as clock source.

• MSKRDY: Mask ready

0: Mask register has been changed, masking in progress. 1: Clock are masked according to xxx_MASK

• CKRDY:

0: The CKSEL register has been written, and the new clock setting is not yet effective. 1: The synchronous clocks have frequencies as indicated in the CKSEL register.

• LOCK1: PLL 1 locked

0:PLL 1 is unlocked 1:PLL 1 is locked, and ready to be selected as clock source.

• LOCK0: PLL 0 locked

0: PLL 0 is unlocked 1: PLL 0 is locked, and ready to be selected as clock source.

13.6.9 Generic Clock Control

32058K

AVR32-01/12

Name: GCCTRL Access Type: Read/Write

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - -

15 14 13 12 11 10 9 8

DIV[7:0]

7 6 5 4 3 2 1 0

AT32UC3A

- - - DIVEN - CEN PLLSEL OSCSEL

There is one GCCTRL register per generic clock in the design.

DIV: Division Factor

•

• DIVEN: Divide Enable

0: The generic clock equals the undivided source clock. 1: The generic clock equals the source clock divided by 2*(DIV+1).

• CEN: Clock Enable

0: Clock is stopped. 1: Clock is running.

• PLLSEL: PLL Select

0: Oscillator is source for the generic clock. 1: PLL is source for the generic clock.

• OSCSEL: Oscillator Select

0: Oscillator (or PLL) 0 is source for the generic clock. 1: Oscillator (or PLL) 1 is source for the generic clock.

AT32UC3A

32058K

AVR32-01/12

13.6.10 Reset Cause Name: RCAUSE

Access Type: Read-only

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - -

15 14 13 12 11 10 9 8

- - - - - - JTAGHARD OCDRST

7 6 5 4 3 2 1 0

CPUERR - - JTAG WDT EXT BOD POR

• POR Power-on Reset

The CPU was reset due to the supply voltage being lower than the power-on threshold level.

• BOD: Brown-out Reset

The CPU was reset due to the supply voltage being lower than the brown-out threshold level.

• EXT: External Reset Pin

The CPU was reset due to the RESET pin being asserted.

• WDT: Watchdog Reset

The CPU was reset because of a watchdog timeout.

• JTAG: JTAG reset

The CPU was reset by setting the bit RC_CPU in the JTAG reset register.

• CPUERR: CPU Error

The CPU was reset because it had detected an illegal access.

• OCDRST: OCD Reset

The CPU was reset because the RES strobe in the OCD Development Control register has been written to one.

• JTAGHARD: JTAG Hard Reset

The chip was reset by setting the bit RC_OCD in the JTAG reset register or by using the JTAG HALT instruction.

13.6.11 BOD Control

32058K

AVR32-01/12

BOD Level register

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

- - - - - - - FCD

15 14 13 12 11 10 9 8

- - - - - - CTRL

7 6 5 4 3 2 1 0

- HYST LEVEL

AT32UC3A

KEY

• KEY: Register Write protection

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• FCD: BOD Fuse calibration done

Set to 1 when CTRL, HYST and LEVEL fields has been updated by the Flash fuses after power-on reset or Flash fuses update If one, the CTRL, HYST and LEVEL values will not be updated again by Flash fuses Can be cleared to allow subsequent overwriting of the value by Flash fuses

• CTRL: BOD Control

0: BOD is off 1: BOD is enabled and can reset the chip 2: BOD is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR register. 3: BOD is off

• HYST: BOD Hysteresis

0: No hysteresis 1: Hysteresis On

• LEVEL: BOD Level

This field sets the triggering threshold of the BOD. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt.

13.6.12 RC Oscillator Calibration

32058K

AVR32-01/12

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

- - - - - - - FCD

15 14 13 12 11 10 9 8

- - - - - - CALIB

7 6 5 4 3 2 1 0

AT32UC3A

KEY

CALIB

• CALIB: Calibration Value

Calibration Value for the RC oscillator.

• FCD: Flash Calibration Done

Set to 1 when CTRL, HYST, and LEVEL fields have been updated by the Flash fuses after power-on reset, or after Flash fuses are reprogrammed. The CTRL, HYST and LEVEL values will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero.

• KEY: Register Write protection

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

13.6.13 Bandgap Calibration

32058K

AVR32-01/12

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

- - - - - - - FCD

15 14 13 12 11 10 9 8

- - - - - - - -

7 6 5 4 3 2 1 0

- - - - - CALIB

AT32UC3A

KEY

• KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• CALIB: Calibration value Calibration value for Bandgap. See Electrical Characteristics for voltage values.

• FCD: Flash Calibration Done

Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero.

13.6.14 PM Voltage Regulator Calibration Register

32058K

AVR32-01/12

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

- - - - - - - FCD

15 14 13 12 11 10 9 8

- - - - - - - -

7 6 5 4 3 2 1 0

- - - - - CALIB

AT32UC3A

KEY

• KEY: Register Write protection

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• CALIB: Calibration value

Calibration value for Voltage Regulator. See Electrical Characteristics for voltage values.

• FCD: Flash Calibration Done

13.6.15 General Purpose Low-power register 0/1

32058K

AVR32-01/12

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

AT32UC3A

GPLP

These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these registers untouched.

14. Real Time Counter (RTC)

32058K

AVR32-01/12

Rev: 2.3.0.1

14.1 Features

• 32-bit real-time counter with 16-bit prescaler

• Clocked from RC oscillator or 32 KHz oscillator

• High resolution: Max count frequency 16 KHz

• Long delays

– Max timeout 272 years

• Extremely low power consumption

• Available in all sleep modes except Static

• Interrupt on wrap

14.2 Description

The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from the RC oscillator or the 32 KHz oscillator. Any tapping of the prescaler can be selected as clock source for the RTC, enabling both high resolution and long timeouts. The prescaler cannot be written directly, but can be cleared by the user.

AT32UC3A

The RTC can generate an interrupt when the counter wraps around the value stored in the top register, producing accurate periodic interrupts.

14.3 Block Diagram

16-bit Prescaler

RC OSC

32-bit counter

RTC_VAL

RTC_TOP

TOPI

IRQ

32 kHz

RTC_CTRL

CLK32

PCLR

32058K

AVR32-01/12

Figure 14-1. Real Time Counter module block diagram

AT32UC3A

14.4 Product Dependencies

14.4.1 Power Management

The RTC is continuously clocked, and remains operating in all sleep modes except Static. Interrupts are not available in DeepStop mode.

14.4.2 Interrupt

The RTC interrupt line is connected to one of the internal sources of the interrupt controller. Using the RTC interrupt requires the interrupt controller to be programmed first.

14.4.3 Debug Operation

The RTC prescaler is frozen during debug operation, unless the OCD system keeps peripherals running in debug operation.

14.4.4 Clocks

The RTC can use the internal RC oscillator as clock source. This oscillator is always enabled whenever these modules are active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (f

The RTC can also use the 32 KHz crystal oscillator as clock source. This oscillator must be enabled before use. Please refer to the Power Manager chapter for details.

14.5 Functional Description

14.5.1 RTC operation

14.5.1.1 Source clock

The RTC is enabled by writing the EN bit in the CTRL register to 1. The 16-bit prescaler will then increment on the selected clock. The prescaler cannot be read or written, but it can be reset by writing the PCLR strobe.

The CLK32 bit selects either the RC oscillator or the 32 KHz oscillator as clock source for the

32058K

AVR32-01/12

prescaler. The PSEL bitfield selects the prescaler tapping, selecting the source clock for the RTC:

14.5.1.2 Counter operation

When enabled, the RTC will increment until it reaches TOP, and then wrap to 0x0. The status bit TOPI in ISR is set when this occurs. From 0x0 the counter will count TOP+1 cycles of the source clock before it wraps back to 0x0.

The RTC count value can be read from or written to the register VAL. Due to synchronization, continuous reading of the VAL with the lowest prescaler setting will skip every other value.

14.5.1.3 RTC Interrupt

Writing the TOPI bit in IER enables the RTC interrupt, while writing the corresponding bit in IDR disables the RTC interrupt. IMR can be read to see whether or not the interrupt is enabled. If enabled, an interrupt will be generated if the TOPI flag in ISR is set. The flag can be cleared by writing TOPI in ICR to one.

The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static mode.

RTC

= 2

-(PSEL+1)

AT32UC3A

* (fRC or 32 KHz)

14.5.1.4 RTC wakeup

14.5.1.5 Busy bit

The RTC can also wake up the CPU directly without triggering an interrupt when the TOPI flag in ISR is set. In this case, the CPU will continue executing from the instruction following the sleep instruction.

This direct RTC wakeup is enabled by writing the WAKE_EN bit in the CTRL register to one. When the CPU wakes from sleep, the WAKE_EN bit must be written to zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction will have no effect.

The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be configured independently of the RTC interrupt.

Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values stored in CTRL, TOP, and VAL to the RTC. The BUSY bit in CTRL indicates that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until BUSY goes low again.

14.6 User Interface

32058K

AVR32-01/12

Offset Register Register Name Access Reset

0x00 RTC Control CTRL Read/Write 0x0 0x04 RTC Value VAL Read/Write 0x0 0x08 RTC Top TOP Read/Write 0x0 0x10 RTC Interrupt Enable IER Write-only 0x0 0x14 RTC Interrupt Disable IDR Write-only 0x0 0x18 RTC Interrupt Mask IMR Read-only 0x0

0x1C RTC Interrupt Status ISR Read-only 0x0

0x20 RTC Interrupt Clear ICR Write-only 0x0

14.6.1 RTC Control Name: CTRL

Access Type: Read/Write

AT32UC3A

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - CLKEN

15 14 13 12 11 10 9 8

- - - - PSEL

7 6 5 4 3 2 1 0

- - - BUSY CLK32 WAKE_EN PCLR EN

• CLKEN: Clock enable

0: The clock is disabled 1: The clockis enabled

• PSEL: Prescale Select

Selects prescaler bit PSEL as source clock for the RTC.

• BUSY: RTC busy

0: The RTC accepts writes to TOP, VAL, and CTRL. 1: The RTC is busy and will discard writes to TOP, VAL, and CTRL.

• CLK32: 32 KHz oscillator select

0: The RTC uses the RC oscillator as clock source 1: The RTC uses the 32 KHz oscillator as clock source

• WAKE_EN: Wakeup enable

32058K

AVR32-01/12

0: The RTC does not wake up the CPU from sleep modes 1: The RTC wakes up the CPU from sleep modes.

• PCLR: Prescaler Clear

Writing 1 to this strobe clears the prescaler.

• EN: Enable

0: The RTC is disabled 1: The RTC is enabled

AT32UC3A

14.6.2 RTC Value

32058K

AVR32-01/12

Name: VAL Access Type: Read/Write

31 30 29 28 27 26 25 24

VAL[31:24]

23 22 21 20 19 18 17 16

VAL[23:16]

15 14 13 12 11 10 9 8

VAL[15:8]

7 6 5 4 3 2 1 0

AT32UC3A

• VAL: RTC Value

This value is incremented on every rising edge of the source clock.

VAL[7:0]

14.6.3 RTC Top

32058K

AVR32-01/12

Name: TOP Access Type: Read/Write

31 30 29 28 27 26 25 24

TOP[31:24]

23 22 21 20 19 18 17 16

TOP[23:16]

15 14 13 12 11 10 9 8

TOP[15:8]

7 6 5 4 3 2 1 0

AT32UC3A

• TOP: RTC Top Value

VAL wraps at this value.

TOP[7:0]

14.6.4 RTC Interrupt Enable/Disable/Mask/Status/Clear

32058K

AVR32-01/12

Name: IER/IDR/IMR/ISR/ICR Access Type: IER/IDR/ICR: Write-only

IMR/ISR: Read-only

31 30 29 28 27 26 25 24

- - - - - - - -

23 22 21 20 19 18 17 16

- - - - - - - -

15 14 13 12 11 10 9 8

- - - - - - - -

AT32UC3A

7 6 5 4 3 2 1 0

- - - - - - - TOPI

TOPI: Top Interrupt

•

VAL has wrapped at its top value.

The effect of writing or reading this bit depends on which register is being accessed:

• IER (Write-only)

0: No effect 1: Enable Interrupt

• IDR (Write-only)

0: No effect 1: Disable Interrupt

• IMR (Read-only)

0: Interrupt is disabled 1: Interrupt is enabled

• ISR (Read-only)

0: An interrupt event has occurred 1: An interrupt even has not occurred

• ICR (Write-only)

0: No effect 1: Clear interrupt even

15. Watchdog Timer (WDT)

RCOSC

WDT_CLR

Watchdog

Detector

WDT_CTRL

32-bit

Prescaler

Watchdog Reset

32058K

AVR32-01/12

Rev: 2.3.0.1

15.1 Features

• Watchdog Timer counter with 16-bit prescaler

• Clocked from RC oscillator

15.2 Description

The Watchdog Timer (WDT) has a prescaler generating a timeout period. This prescaler is clocked from the RC oscillator. The watchdog timer must be periodically reset by software within the timeout period, otherwise, the device is reset and starts executing from the boot vector. This allows the device to recover from a condition that has caused the system to be unstable.

15.3 Block Diagram

Figure 15-1. Watchdog Timer module block diagram

AT32UC3A

15.4 Product Dependencies

15.4.1 Power Management

When the WDT is enabled, the WDT remains clocked in all sleep modes, and it is not possible to enter Static mode.

15.4.2 Debug Operation

The WDT prescaler is frozen during debug operation, unless the OCD system keeps peripherals running in debug operation.

15.4.3 Clocks

The WDT can use the internal RC oscillator as clock source. This oscillator is always enabled whenever these modules are active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (fRC).

15.5 Functional Description

32058K

AVR32-01/12

The WDT is enabled by writing the EN bit in the CTRL register to one. This also enables the RC clock for the prescaler. The PSEL bitfield in the same register selects the watchdog timeout period:

WDT

The next timeout period will begin as soon as the watchdog reset has occured and count down during the reset sequence. Care must be taken when selecting the PSEL value so that the timeout period is greater than the startup time of the chip, otherwise a watchdog reset can reset the chip before any code has been run.

To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with the KEY field set to 0x55, then 0xAA without changing the other bitfields. Failure to do so will cause the write operation to be ignored, and CTRL does not change value.

The CLR register must be written with any value with regular intervals shorter than the watchdog timeout period. Otherwise, the device will receive a soft reset, and the code will start executing from the boot vector.

When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result in entering Shutdown mode, leaving the WDT operational.

= 2

(PSEL+1)

/ f

AT32UC3A

15.6 User Interface

32058K

AVR32-01/12

Offset Register Register Name Access Reset

0x00 WDT Control CTRL Read/Write 0x0 0x04 WDT Clear CLR Write-only 0x0

AT32UC3A

15.6.1 WDT Control

32058K

AVR32-01/12

Name: CTRL Access Type: Read/Write

31 30 29 28 27 26 25 24

KEY[7:0]

23 22 21 20 19 18 17 16

- - - - - - - -

15 14 13 12 11 10 9 8

- - - PSEL

7 6 5 4 3 2 1 0

AT32UC3A

- - - - - - - EN

• KEY

This bitfield must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This bitfield always reads as zero.

• PSEL: Prescale Select

Prescaler bit PSEL is used as watchdog timeout period.

• EN: WDT Enable

0: WDT is disabled. 1: WDT is enabled.

AT32UC3A

32058K

AVR32-01/12

15.6.2 WDT Clear Name: CLR

Access Type: Write-only

When the watchdog timer is enabled, this register must be periodically written, with any value, within the watchdog timeout period, to prevent a watchdog reset.

16. Interrupt Controller (INTC)

Request masking

IREQ0

IREQ1

IREQ2

IREQ31

GrpReq0

Masks

SREG masks

I[3-0]M

INTLEVEL

AUTOVECTOR

Prioritizer

CPUInterrupt Controller

GrpReqN

NMIREQ

IREQ32

IREQ33

IREQ34

IREQ63

GrpReq1

IRR registers

IPR registers ICR registers

INT_level, offset

IPR0

IPR1

IPRn

IRR0

IRR1

IRRn

ValReq0

ValReq1

ValReqN

32058K

AVR32-01/12

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16.1 Description

The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).

The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register (IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and an autovector to each group, and the IRRs are used to identify the active interrupt request within each group. If a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the group that has a pending interrupt of the corresponding priority level. If several groups have an pending interrupt of the same level, the group with the lowest number takes priority.

16.2 Block Diagram

AT32UC3A

16.3 Operation

Figure 16-1 on page 99 gives an overview of the INTC. The grey boxes represent registers that

can be accessed via the Peripheral Bus (PB). The interrupt requests from the peripherals (IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure.

Figure 16-1. Overview of the Interrupt Controller

All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that is active. If several IREQs within the same group is active, the interrupt service routine must pri-

AT32UC3A

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oritize between them. All of the input lines in each group are logically-ORed together to form the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.

The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to INT3 by associating each group with the INTLEVEL field in the corresponding IPR register. The GrpReq inputs are then masked by the I0M, I1M, I2M, I3M and GM mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted.

The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the pending interrupt of the highest priority. If a NMI interrupt is pending, it automatically gets highest priority of any pending interrupt. If several interrupt groups of the highest pending interrupt level have pending interrupts, the interrupt group with the highest number is selected.

Interrupt level (INTLEVEL) and handler autovector offset (AUTOVECTOR) of the selected interrupt are transmitted to the CPU for interrupt handling and context switching. The CPU doesn't need to know which interrupt is requesting handling, but only the level and the offset of the handler address. The IRR registers contain the interrupt request lines of the groups and can be read via PB for checking which interrupts of the group are actually active.

Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely interrupt level 3 mask (I3M) to interrupt level 0 mask (I0M), and Global interrupt mask (GM). An interrupt request is masked if either the Global interrupt mask or the corresponding interrupt level mask bit is set.

16.3.1 Non maskable interrupts

A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vector address defined by the AVR32 architecture, so AUTOVECTOR is undefined when INTLEVEL indicates that an NMI is pending.

16.3.2 CPU response

When the CPU receives an interrupt request it checks if any other exceptions are pending. If no exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt handling, the corresponding interrupt mask bit is set automatically for this and lower levels in status register. E.g, if interrupt on level 3 is approved for handling the interrupt mask bits I3M, I2M, I1M, and I0M are set in status register. If interrupt on level 1 is approved the masking bits I1M, and I0M are set in status register. The handler offset is calculated from AUTOVECTOR and EVBA and a change-of-flow to this address is performed.

Setting of the interrupt mask bits prevents the interrupts from the same and lower levels to be passed trough the interrupt controller. Setting of the same level mask bit prevents also multiple request of the same interrupt to happen.

It is the responsibility of the handler software to clear the interrupt request that caused the interrupt before returning from the interrupt handler. If the conditions that caused the interrupt are not cleared, the interrupt request remains active.

16.3.3 Clearing an interrupt request

Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal.

The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a

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Atmel AT32UC3A0512, AT32UC3A0256, AT32UC3A0128, AT32UC3A1512, AT32UC3A1256 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

2. Configuration Summary

3. Abbreviations

4. Blockdiagram

4.1 Processor and architecture

4.1.1 AVR32 UC CPU

4.1.2 Debug and Test system

4.1.3 Peripheral DMA Controller

4.1.4 Bus system

5. Signals Description

6. Power Considerations

6.1 Power Supplies

6.2 Voltage Regulator

6.2.1 Single Power Supply

6.2.2 Dual Power Supply

6.3 Analog-to-Digital Converter (A.D.C) reference.

7. Package and Pinout

8. I/O Line Considerations

8.1 JTAG pins

8.2 RESET_N pin

8.3 TWI pins

8.4 GPIO pins

9. Processor and Architecture

9.1 AVR32 Architecture

9.2 The AVR32UC CPU

9.2.1 Pipeline Overview

9.2.2 AVR32A Microarchitecture Compliance

9.2.3 Java Support

9.2.4 Memory protection

9.2.5 Unaligned reference handling

9.2.6 Unimplemented instructions

9.2.7 CPU and Architecture revision

9.3 Programming Model

9.3.1 Register file configuration

9.3.2 Status register configuration

9.3.3 Processor States

9.3.3.1 Normal RISC State

9.3.3.2 Debug State

9.3.4 System registers

9.4 Exceptions and Interrupts

9.4.1 System stack issues

9.4.2 Exceptions and interrupt requests

9.4.3 Supervisor calls

9.4.4 Debug requests

9.4.5 Entry points for events

10. Memories

10.1 Embedded Memories

10.2 Physical Memory Map

10.3 Bus Matrix Connections

11. Fuses Settings

11.1 Flash General Purpose Fuse Register (FGPFRLO)

11.2 Default Fuse Value

12. Peripherals

12.1 Peripheral address map

12.2 CPU Local Bus Mapping

12.3 Interrupt Request Signal Map

12.4 Clock Connections

12.4.1 Timer/Counters

12.4.2 USARTs

12.4.3 SPIs

12.5 Nexus OCD AUX port connections

12.6 PDC handshake signals

12.7 Peripheral Multiplexing on I/O lines

12.8 Oscillator Pinout

12.9 USART Configuration

12.10 GPIO

12.11 Peripheral overview

12.11.1 External Bus Interface

12.11.2 Static Memory Controller

12.11.3 SDRAM Controller

12.11.4 USB Controller

12.11.5 Serial Peripheral Interface

12.11.6 Two-wire Interface

12.11.7 USART

12.11.8 Serial Synchronous Controller