Atmel AT32UC3A0512, AT32UC3A0256, AT32UC3A0128, AT32UC3A1512, AT32UC3A1256 Datasheet

Features

32058K-

AVR32-01/12

• High Performance, Low Power 32-Bit Atmel

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing 1.49 DMIPS / MHz

Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)
Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)

– Memory Protection Unit

• Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance
– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes Versions
– Single Cycle Access up to 33 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)

• External Memory Interface on AT32UC3A0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

• Universal Serial Bus (USB)

– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)

• One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line

• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

• One Synchronous Serial Protocol Controller

– Supports I2S and Generic Frame-Based Protocols

• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible

• One 8-channel 10-bit Analog-To-Digital Converter

• 16-bit Stereo Audio Bitstream

– Sample Rate Up to 50 KHz

®

AVR® Microcontroller

32-Bit Atmel AVR
Microcontroller

AT32UC3A0512
AT32UC3A0256
AT32UC3A0128
AT32UC3A1512
AT32UC3A1256
AT32UC3A1128

• On-Chip Debug System (JTAG interface)

32058K

AVR32-01/12

– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace

• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins)

• 5V Input Tolerant I/Os

• Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply

AT32UC3A

2

1. Description

32058K

AVR32-01/12

AT32UC3A

The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC
processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha­sis on low power consumption, high code density and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con­troller for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.

The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3A0 derivatives.

The Peripheral Direct Memory Access controller (PDCA) enables data transfers between periph­erals and memories without processor involvement. PDCA drastically reduces processing
overhead when transferring continuous and large data streams between modules within the
MCU.

The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform frequency measurement, event counting, interval mea­surement, pulse generation, delay timing and pulse width modulation.

The PWM modules provides seven independent channels with many configuration options
including polarity, edge alignment and waveform non overlap control. One PWM channel can
trigger ADC conversions for more accurate close loop control implementations.

The AT32UC3A also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible Synchronous Serial Controller, USB and Ethernet MAC are available.

The Synchronous Serial Controller provides easy access to serial communication protocols and
audio standards like I2S.

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time
thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device
like a USB Flash disk or a USB printer to be directly connected to the processor.

The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module
provides on-chip solutions for network-connected devices.

AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.

3

2. Configuration Summary

32058K

AVR32-01/12

The table below lists all AT32UC3A memory and package configurations:

Device Flash SRAM Ext. Bus Interface
AT32UC3A0512 512 Kbytes 64 Kbytes yes yes 144 pin LQFP

AT32UC3A0256 256 Kbytes 64 Kbytes yes yes 144 pin LQFP

AT32UC3A0128 128 Kbytes 32 Kbytes yes yes 144 pin LQFP

AT32UC3A1512 512 Kbytes 64 Kbytes no yes 100 pin TQFP
AT32UC3A1256 256 Kbytes 64 Kbytes no yes 100 pin TQFP
AT32UC3A1128 128 Kbytes 32 Kbytes no yes 100 pin TQFP

AT32UC3A

Ethernet
MAC Package

144 pin BGA

144 pin BGA

144 pin BGA

3. Abbreviations

• GCLK: Power Manager Generic Clock

• GPIO: General Purpose Input/Output

• HSB: High Speed Bus

• MPU: Memory Protection Unit

• OCD: On Chip Debug

• PB: Peripheral Bus

• PDCA: Peripheral Direct Memory Access Controller (PDC) version A

• USBB: USB On-The-GO Controller version B

4

4. Blockdiagram

UC CPU

NEXUS

CLASS 2+

OCD

INSTR

INTERFACE

DATA

INTERFACE

TIMER/COUNTER

INTERRUPT

CONTROLLER

REAL TIME

COUNTER

PERIPHERAL

DMA

CONTROLLER

512 KB
FLASH

HSB-PB

BRIDGE B

HSB-PB

BRIDGE A

MEMORY INTERFACE

S

M M M

M
M

S

S

S

S

S

M

EXTERNAL

INTERRUPT

CONTROLLER

HIGH SPEED
BUS MATRIX

FAST GPIO

GENERAL PURPOSE IOs

64 KB
SRAM

GENERAL PURPOSE IOs

PA
PB
PC
PX

A[2..0]
B[2..0]

CLK[2..0]

EXTINT[7..0]

KPS[7..0]

NMI_N

GCLK[3..0]

XIN32

XOUT32

XIN0

XOUT0

PA
PB
PC
PX

RESET_N

EXTERNAL BUS INTERFACE

(SDRAM & STATIC MEMORY

CONTROLLER)

CAS

RAS

SDA10

SDCK
SDCKE
SDCS0

SDWE

NCS[3..0]

NRD

NWAIT

NWE0

DATA[15..0]

USB

INTERFACE

DMA

ID

VBOF

VBUS

D-

D+

ETHERNET

MAC

DMA

32 KHz

OSC

115 kHz
RCOSC

OSC0

PLL0

PULSE WIDTH
MODULATION
CONTROLLER

SERIAL

PERIPHERAL

INTERFACE 0/1

TWO-WIRE

INTERFACE

PDCPDC PDC

MISO, MOSI

NPCS[3..1]

PWM[6..0]

SCL

SDA

USART1

PDC

RXD
TXD
CLK

RTS, CTS

DSR, DTR, DCD, RI

USART0
USART2
USART3

PDC

RXD
TXD
CLK

RTS, CTS

SYNCHRONOUS

SERIAL

CONTROLLER

PDC

TX_CLOCK, TX_FRAME_SYNC

RX_DATA

TX_DATA

RX_CLOCK, RX_FRAME_SYNC

ANALOG TO

DIGITAL

CONVERTER

PDC

AD[7..0]

ADVREF

WATCHDOG

TIMER

XIN1

XOUT1

OSC1

PLL1

SCK

JTAG

INTERFACE

MCKO

MDO[5..0]

MSEO[1..0]

EVTI_N

EVTO_N

TCK
TDO

TDI

TMS

POWER

MANAGER

RESET

CONTROLLER

ADDR[23..0]

SLEEP

CONTROLLER

CLOCK

CONTROLLER

CLOCK

GENERATOR

COL,

CRS,
RXD[3..0],
RX_CLK,

RX_DV,

RX_ER

MDC,

TXD[3..0],

TX_CLK,

TX_EN,
TX_ER,

SPEED

MDIO

FLASH

CONTROLLER

CONFIGURATION REGISTERS BUS

MEMORY PROTECTION UNIT

PB

PB

HSB

HS

B

NWE1
NWE3

PBA

PBB

NPCS0

LOCAL BUS
INTERFACE

AUDIO

BITSTREAM

DAC

PDC

DATA[1..0]

DATAN[1..0]

32058K

AVR32-01/12

Figure 4-1. Blockdiagram

AT32UC3A

5

4.1 Processor and architecture

32058K

AVR32-01/12

4.1.1 AVR32 UC CPU

• 32-bit load/store AVR32A RISC architecture.

– 15 general-purpose 32-bit registers.
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
– Fully orthogonal instruction set.
– Privileged and unprivileged modes enabling efficient and secure Operating Systems.
– Innovative instruction set together with variable instruction length ensuring industry leading

code density.

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.

• 3 stage pipeline allows one instruction per clock cycle for most instructions.

– Byte, half-word, word and double word memory access.
– Multiple interrupt priority levels.

• MPU allows for operating systems with memory protection.

4.1.2 Debug and Test system

• IEEE1149.1 compliant JTAG and boundary scan

• Direct memory access and programming capabilities through JTAG interface

• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+

– Low-cost NanoTrace supported.

• Auxiliary port for high-speed trace information

• Hardware support for 6 Program and 2 data breakpoints

• Unlimited number of software breakpoints supported

• Advanced Program, Data, Ownership, and Watchpoint trace supported

AT32UC3A

4.1.3 Peripheral DMA Controller

• Transfers from/to peripheral to/from any memory space without intervention of the processor.

• Next Pointer Support, forbids strong real-time constraints on buffer management.

• Fifteen channels

– Two for each USART
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for each ADC
– Two for each TWI Interface

4.1.4 Bus system

• High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled

– Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet

Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus
B, EBI.

– Round-Robin Arbitration (three modes supported: no default master, last

master, fixed default master)

– Burst Breaking with Slot Cycle Limit
– One Address Decoder Provided per Master

accessed default

6

AT32UC3A

32058K

AVR32-01/12

• Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus

Figure 4-1 gives an overview of the bus system. All modules connected to the same bus use the

same clock, but the clock to each module can be individually shut off by the Power Manager.
The figure identifies the number of master and slave interfaces of each module connected to the
High Speed Bus, and which DMA controller is connected to which peripheral.

7

5. Signals Description

32058K

AVR32-01/12

The following table gives details on the signal name classified by peripheral
The signals are multiplexed with GPIO pins as described in ”Peripheral Multiplexing on I/O lines”

on page 45.

Table 5-1. Signal Description List

Signal Name Function Type

Power

AT32UC3A

Active

Level Comments

VDDPLL Power supply for PLL

VDDCORE Core Power Supply

VDDIO I/O Power Supply

VDDANA Analog Power Supply

VDDIN Voltage Regulator Input Supply

VDDOUT Voltage Regulator Output

GNDANA Analog Ground Ground

GND Ground Ground

Clocks, Oscillators, and PLL’s

XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog

XOUT0, XOUT1,
XOUT32

Crystal 0, 1, 32 Output Analog

Power

Input

Power

Input

Power

Input

Power

Input

Power

Input

Power

Output

1.65V to 1.95 V

1.65V to 1.95 V

3.0V to 3.6V

3.0V to 3.6V

3.0V to 3.6V

1.65V to 1.95 V

JTAG

TCK Test Clock Input

TDI Test Data In Input

TDO Test Data Out Output

TMS Test Mode Select Input

Auxiliary Port - AUX

MCKO Trace Data Output Clock Output

MDO0 - MDO5 Trace Data Output Output

8

Table 5-1. Signal Description List

32058K

AVR32-01/12

Active

Signal Name Function Type

MSEO0 - MSEO1 Trace Frame Control Output

EVTI_N Event In Output Low

EVTO_N Event Out Output Low

Power Manager - PM

GCLK0 - GCLK3 Generic Clock Pins Output

RESET_N Reset Pin Input Low

Real Time Counter - RTC

RTC_CLOCK RTC clock Output

Watchdog Timer - WDT

WDTEXT External Watchdog Pin Output

Level Comments

AT32UC3A

External Interrupt Controller - EIC

EXTINT0 - EXTINT7 External Interrupt Pins Input

KPS0 - KPS7 Keypad Scan Pins Output

NMI_N Non-Maskable Interrupt Pin Input Low

Ethernet MAC - MACB

COL Collision Detect Input

CRS Carrier Sense and Data Valid Input

MDC Management Data Clock Output

MDIO Management Data Input/Output I/O

RXD0 - RXD3 Receive Data Input

RX_CLK Receive Clock Input

RX_DV Receive Data Valid Input

RX_ER Receive Coding Error Input

SPEED Speed

TXD0 - TXD3 Transmit Data Output

TX_CLK Transmit Clock or Reference Clock Output

TX_EN Transmit Enable Output

TX_ER Transmit Coding Error Output

9

Table 5-1. Signal Description List

32058K

AVR32-01/12

Active

Signal Name Function Type

External Bus Interface - HEBI

ADDR0 - ADDR23 Address Bus Output

CAS Column Signal Output Low

DATA0 - DATA15 Data Bus I/O

NCS0 - NCS3 Chip Select Output Low

NRD Read Signal Output Low

NWAIT External Wait Signal Input Low

NWE0 Write Enable 0 Output Low

NWE1 Write Enable 1 Output Low

NWE3 Write Enable 3 Output Low

Level Comments

AT32UC3A

RAS Row Signal Output Low

SDA10 SDRAM Address 10 Line Output

SDCK SDRAM Clock Output

SDCKE SDRAM Clock Enable Output

SDCS0 SDRAM Chip Select Output Low

SDWE SDRAM Write Enable Output Low

General Purpose Input/Output 2 - GPIOA, GPIOB, GPIOC

P0 - P31 Parallel I/O Controller GPIOA I/O

P0 - P31 Parallel I/O Controller GPIOB I/O

P0 - P5 Parallel I/O Controller GPIOC I/O

P0 - P31 Parallel I/O Controller GPIOX I/O

Serial Peripheral Interface - SPI0, SPI1

MISO Master In Slave Out I/O

MOSI Master Out Slave In I/O

NPCS0 - NPCS3 SPI Peripheral Chip Select I/O Low

SCK Clock Output

Synchronous Serial Controller - SSC

RX_CLOCK SSC Receive Clock I/O

10

Table 5-1. Signal Description List

32058K

AVR32-01/12

Signal Name Function Type

RX_DATA SSC Receive Data Input

RX_FRAME_SYNC SSC Receive Frame Sync I/O

TX_CLOCK SSC Transmit Clock I/O

TX_DATA SSC Transmit Data Output

TX_FRAME_SYNC SSC Transmit Frame Sync I/O

Timer/Counter - TIMER

A0 Channel 0 Line A I/O

A1 Channel 1 Line A I/O

A2 Channel 2 Line A I/O

B0 Channel 0 Line B I/O

AT32UC3A

Active

Level Comments

B1 Channel 1 Line B I/O

B2 Channel 2 Line B I/O

CLK0 Channel 0 External Clock Input Input

CLK1 Channel 1 External Clock Input Input

CLK2 Channel 2 External Clock Input Input

Two-wire Interface - TWI

SCL Serial Clock I/O

SDA Serial Data I/O

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3

CLK Clock I/O

CTS Clear To Send Input

DCD Data Carrier Detect Only USART1

DSR Data Set Ready Only USART1

DTR Data Terminal Ready Only USART1

RI Ring Indicator Only USART1

RTS Request To Send Output

RXD Receive Data Input

TXD Transmit Data Output

11

Table 5-1. Signal Description List

32058K

AVR32-01/12

Signal Name Function Type

Analog to Digital Converter - ADC

AT32UC3A

Active

Level Comments

AD0 - AD7 Analog input pins

ADVREF Analog positive reference voltage input

Pulse Width Modulator - PWM

PWM0 - PWM6 PWM Output Pins Output

Universal Serial Bus Device - USB

DDM USB Device Port Data - Analog

DDP USB Device Port Data + Analog

VBUS USB VBUS Monitor and OTG Negociation

USBID ID Pin of the USB Bus Input

USB_VBOF USB VBUS On/off: bus power control port output

Audio Bitstream DAC (ABDAC)

DATA0-DATA1 D/A Data out Outpu

DATAN0-DATAN1 D/A Data inverted out Outpu

Analog

input

Analog

input

Analog

Input

2.6 to 3.6V

12

6. Power Considerations

3.3V

VDDANA

VDDIO

VDDIN

VDDCORE

VDDOUT

VDDPLL

ADVREF

3.3V

1.8V

VDDANA

VDDIO

VDDIN

VDDCORE

VDDOUT

VDDPLL

ADVREF

Single Power Supply

Dual Power Supply

1.8V

Regulator

1.8V

Regulator

32058K

AVR32-01/12

6.1 Power Supplies

The AT32UC3A has several types of power supply pins:

• VDDIO: Powers I/O lines. Voltage is 3.3V nominal.

• VDDANA: Powers the ADC Voltage is 3.3V nominal.

• VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal.

• VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.

• VDDPLL: Powers the PLL. Voltage is 1.8V nominal.
The ground pins GND are common to VDDCORE, VDDIO, VDDPLL. The ground pin for

VDDANA is GNDANA.
Refer to ”Power Consumption” on page 767 for power consumption on the various supply pins.

AT32UC3A

13

6.2 Voltage Regulator

3.3V

1.8V

VDDIN

VDDOUT

1.8V

Regulator

C

IN1

C

OUT1

C

OUT2

C

IN2

VDDIN

VDDOUT

32058K

AVR32-01/12

6.2.1 Single Power Supply

The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes
its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be
externally connected to the 1.8V domains.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop. Two input decoupling capacitors must be placed close to the
chip.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscil­lations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and
GND as close to the chip as possible

AT32UC3A

Refer to Section 38.3 on page 765 for decoupling capacitors values and regulator characteristics

6.2.2 Dual Power Supply

In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent
from leakage current.

14

6.3 Analog-to-Digital Converter (A.D.C) reference.

ADVREF

CC

VREF1VREF2

3.3V

32058K

AVR32-01/12

The ADC reference (ADVREF) must be provided from an external source. Two decoupling
capacitors must be used to insure proper decoupling.

Refer to Section 38.4 on page 765 for decoupling capacitors values and electrical
characteristics.

In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra
consumption.

AT32UC3A

15

AT32UC3A

1 25

26

50

5175

76

100

32058K

AVR32-01/12

7. Package and Pinout

The device pins are multiplexed with peripheral functions as described in ”Peripheral Multiplexing on I/O lines” on page 45.

Figure 7-1. TQFP100 Pinout

Table 7-1. TQFP100 Package Pinout

1 PB20 26 PA05 51 PA21 76 PB08
2 PB21 27 PA06 52 PA22 77 PB09
3 PB22 28 PA07 53 PA23 78 PB10
4 VDDIO 29 PA08 54 PA24 79 VDDIO
5 GND 30 PA09 55 PA25 80 GND
6 PB23 31 PA10 56 PA26 81 PB11
7 PB24 32 N/C 57 PA27 82 PB12
8 PB25 33 PA11 58 PA28 83 PA29

9 PB26 34 VDDCORE 59 VDDANA 84 PA30
10 PB27 35 GND 60 ADVREF 85 PC02
11 VDDOUT 36 PA12 61 GNDANA 86 PC03
12 VDDIN 37 PA13 62 VDDPLL 87 PB13
13 GND 38 VDDCORE 63 PC00 88 PB14
14 PB28 39 PA
15 PB29 40 PA15
16 PB30 41 PA16 66 PB01 91 TDO
17 PB31 42 PA17 67 VDDIO 92 TDI
18 RESET_N 43 PA18 68 VDDIO 93 PC04
19 PA00 44 PA19 69 GND 94 PC05
20 PA01 45 PA20 70 PB02 95 PB15
21 GND 46 VBUS 71 PB03 96 PB16
22 VDDCORE 47 VDDIO 72 PB04 97 VDDCORE

14

64 PC01 89 TMS
65 PB00 90 TCK

16

AT32UC3A

1 36

37

72

73108

109

144

32058K

AVR32-01/12

Table 7-1. TQFP100 Package Pinout

23 PA02 48 DM 73 PB05 98 PB17
24 PA03 49 DP 74 PB06 99 PB18
25 PA04 50 GND 75 PB07 100 PB19

Figure 7-2. LQFP144 Pinout

Table 7-2. VQFP144 Package Pinout

1 PX00 37 GND 73 PA21 109 GND

2 PX01 38 PX10 74 PA22 110 PX30

3 PB20 39 PA05 75 PA23 111 PB08

4 PX02 40 PX11 76 PA24 112 PX31

5 PB21 41 PA06 77 PA25 113 PB09

6 PB22 42 PX12 78 PA26 114 PX32

7 VDDIO 43 PA07 79 PA27 115 PB10

8 GND 44 PX13 80 PA28 116 VDDIO

9 PB23 45 PA08 81 VDDANA 117 GND
10 PX03 46 PX14 82 ADVREF 118 PX33
11 PB24 47 PA09 83 GNDANA 119 PB11
12 PX04 48 PA10 84 VDDPLL 120 PX34
13 PB25 49 N/C 85 PC00 121 PB12
14 PB26 50 PA
15 PB27 51 VDDCORE 87 PX20 123 PA30
16 VDDOUT 52 GND 88 PB00 124 PC02
17 VDDIN 53 PA12 89 PX21 125 PC03
18 GND 54 PA13 90 PB01 126 PB13
19 PB28 55 VDDCORE 91 PX22 127 PB14
20 PB29 56 PA14 92 VDDIO 128 TMS
21 PB30 57 PA15 93 VDDIO 129 TCK

11

86 PC01 122 PA29

17

AT32UC3A

32058K

AVR32-01/12

Table 7-2. VQFP144 Package Pinout

22 PB31 58 PA16 94 GND 130 TDO
23 RESET_N 59 PX15 95 PX23 131 TDI
24 PX05 60 PA17 96 PB02 132 PC04
25 PA00 61 PX16 97 PX24 133 PC05
26 PX06 62 PA18 98 PB03 134 PB15
27 PA01 63 PX17 99 PX25 135 PX35
28 GND 64 PA19 100 PB04 136 PB16
29 VDDCORE 65 PX18 101 PX26 137 PX36
30 PA02 66 PA20 102 PB05 138 VDDCORE
31 PX07 67 PX19 103 PX27 139 PB17
32 PA03 68 VBUS 104 PB06 140 PX37
33 PX08 69 VDDIO 105 PX28 141 PB18
34 PA04 70 DM 106 PB07 142 PX38
35 PX09 71 DP 107 PX29 143 PB19
36 VDDIO 72 GND 108 VDDIO 144 PX39

Figure 7-3. BGA144 Pinout

18

AT32UC3A

32058K

AVR32-01/12

Table 7-3. BGA144 Package Pinout A1..M8

1 2 3 4 5 6 7 8

VDDIO PB07 PB05 PB02 PB03 PB01 PC00 PA28

A

PB08 GND PB06 PB04 VDDIO PB00 PC01 VDDPLL

B

PB09 PX33 PA29 PC02 PX28 PX26 PX22 PX21

C

PB11 PB13 PB12 PX30 PX29 PX25 PX24 PX20

D

PB10 VDDIO PX32 PX31 VDDIO PX27 PX23 VDDANA

E

PA30 PB14 PX34 PB16 TCK GND GND PX16

F

TMS PC03 PX36 PX35 PX37 GND GND PA16

G

TDO VDDCORE PX38 PX39 VDDIO PA01 PA10 VDDCORE

H

TDI PB17 PB15 PX00 PX01 PA00 PA03 PA04

J

PC05 PC04 PB19 PB20 PX02 PB29 PB30 PA02

K

PB21 GND PB18 PB24 VDDOUT PX04 PB31 VDDIN

L

PB22 PB23 PB25 PB26 PX03 PB27 PB28 RESET_N

M

Table 7-4. BGA144 Package Pinout A9..M12

9 10 11 12

PA26 PA25 PA24 PA23

A

PA27 PA21 GND PA22

B

ADVREF GNDANA PX19 PA19

C

PA18 PA20 DP DM

D

PX18 PX17 VDDIO VBUS

E

PA17 PX15 PA15 PA14

F

PA13 PA12 PA11 NC

G

PX11 PA08 VDDCORE VDDCORE

H

PX14 PA07 PX13 PA09

J

PX08 GND PA05 PX12

K

PX06 PX10 GND PA06

L

PX05 PX07 PX09 VDDIO

M

Note: NC is not connected.

19

8. I/O Line Considerations

32058K

AVR32-01/12

8.1 JTAG pins

TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no
pull-up resistor.

8.2 RESET_N pin

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As
the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case
no reset from the system needs to be applied to the product.

8.3 TWI pins

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the
pins have the same characteristics as PIO pins.

8.4 GPIO pins

All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is
performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines
default as inputs with pull-up resistors disabled, except when indicated otherwise in the column
“Reset State” of the GPIO Controller multiplexing tables.

AT32UC3A

20

9. Processor and Architecture

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AVR32-01/12

This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set and MPU is pre­sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.

9.1 AVR32 Architecture

AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost­sensitive embedded applications, with particular emphasis on low power consumption and high
code density. In addition, the instruction set architecture has been tuned to allow a variety of
microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been com­piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirements, a compact code size also contributes to the core’s low power characteris­tics. The processor supports byte and half-word data types without penalty in code size and
performance.

Memory load and store operations are provided for byte, half-word, word and double word data
with automatic sign- or zero extension of half-word and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.

AT32UC3A

In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme­diate, and an extended format with a larger immediate. In this way, the compiler is able to use
the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com­pact format with two operands as well as an extended format with three operands. The larger
format increases performance, allowing an addition and a data move in the same instruction in a
single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.

9.2 The AVR32UC CPU

The AVR32 UC CPU targets low- and medium-performance applications, and provides an
advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration
hardware is not implemented.

AVR32 UC provides three memory interfaces, one High Speed Bus master for instruction fetch,
one High Speed Bus master for data access, and one High Speed Bus slave interface allowing
other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the
CPU allows fast access to the RAMs, reduces latency and guarantees deterministic timing. Also,
power consumption is reduced by not needing a full High Speed Bus access for memory
accesses. A dedicated data RAM interface is provided for communicating with the internal data
RAMs.

21

AT32UC3A

AVR32UC CPU pipeline

Instruction memory controller

High

Speed

Bus

master

MPU

High Speed Bus

High Speed Bus

OCD

system

OCD interface

Interrupt controller interface

High

Speed

Bus slave

High Speed Bus

Data RAM interface

High Speed Bus master

Power/

Reset

control

Reset interface

CPU Local

Bus

master

CPU Local Bus

Data memory controller

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AVR32-01/12

A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the
LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the
CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory
range allocated to it, and data transfers are performed using regular load and store instructions.
Details on which devices that are mapped into the local bus space is given in the device-specific
“Peripherals” chapter of this data sheet.

Figure 9-1 on page 22 displays the contents of AVR32UC.

Figure 9-1. Overview of the AVR32UC CPU

9.2.1 Pipeline Overview

AVR32 UC is a pipelined processor with three pipeline stages. There are three pipeline stages,
Instruction Fetch (IF), Instruction Decode (ID) and Instruction Execute (EX). The EX stage is
split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) sec­tion and one load/store (LS) section.

Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num­ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.

Figure 9-2 on page 23 shows an overview of the AVR32 UC pipeline stages.

22

Figure 9-2. The AVR32UC Pipeline

IF ID ALU

MUL

Regfile

write

Prefetch unit Decode unit

ALU unit

Multiply unit

Load-store

unit

LS

Regfile

Read

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9.2.2 AVR32A Microarchitecture Compliance

AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar­geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers and return status registers. Instead, all this information is stored on the system
stack. This saves chip area at the expense of slower interrupt handling.

AT32UC3A

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are
restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register and continue execution at the popped return address.

9.2.3 Java Support

AVR32UC does not provide Java hardware acceleration.

9.2.4 Memory protection

The MPU allows the user to check all memory accesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.

9.2.5 Unaligned reference handling

AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.

23

The following table shows the instructions with support for unaligned addresses. All other

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instructions require aligned addresses.

Table 9-1. Instructions with unaligned reference support

Instruction Supported alignment

ld.d Word
st.d Word

9.2.6 Unimplemented instructions

The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:

• All SIMD instructions

• All coprocessor instructions

• retj, incjosp, popjc, pushjc

• tlbr, tlbs, tlbw

• cache

9.2.7 CPU and Architecture revision

Two major revisions of the AVR32UC CPU currently exist. The device described in this
datasheet uses CPU revision 2.

AT32UC3A

The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.

AVR32UC CPU revision 2 is fully backward-compatible with revision 1, ie. code compiled for
revision 1 is binary-compatible with revision 2 CPUs.

24

9.3 Programming Model

Application

Bit 0

Supe rv isor

Bit 31

PC

SR

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4
R3

R1

R2

R0

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

INT0

SP_APP SP_SYS

R12

R11

R9

R10

R8

Exce ption NMIINT1 INT2 INT3

LRLR

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

SP_SYS

LR

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

SP_SYS

LR

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

SP_SYS

LR

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

SP_SYS

LR

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

SP_SYS

LR

Bit 0Bit 31

PC

SR

R12

INT0PC

FINTPC

INT1PC

SM PC

R7

R5

R6

R4

R11

R9

R10

R8

R3

R1

R2

R0

SP_SYS

LR

Bit 31

0 0 0

Bit 16

Interrupt Level 0 Mask
Interrupt Level 1 Mask

Interrupt Level 3 Mask

Interrupt Level 2 Mask

10 0 0 0 1 1 0 0 0 00 0

FE I0M GMM1- D M0 EM I2MDM - M2

LC

1

-

Initial value

Bit name

I1M

Mode Bit 0
Mode Bit 1

-

Mode Bit 2
Reserved

Debug State

- I3M

Reserved

Exception Mask

Global Interrupt Mask

Debug State Mask

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AVR32-01/12

9.3.1 Register file configuration

The AVR32UC register file is shown below.

Figure 9-3. The AVR32UC Register File

AT32UC3A

9.3.2 Status register configuration

The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 9-4 on

page 25 and Figure 9-5 on page 26. The lower word contains the C, Z, N, V and Q condition

code flags and the R, T and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.

Figure 9-4. The Status Register High Halfword

25

Figure 9-5. The Status Register Low Halfword

Bit 15 Bit 0

Reserved

Carry
Zero
Sign

0 0 0 00000000000

- - --TR Bit name

Initial value

0 0

L Q V N Z C-

Overflow
Saturation

- - -

Lock

Register Remap Enable

Scratch

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AVR32-01/12

9.3.3 Processor States

9.3.3.1 Normal RISC State

The AVR32 processor supports several different execution contexts as shown in Table 9-2 on

page 26.

Table 9-2. Overview of execution modes, their priorities and privilege levels.

AT32UC3A

Priority Mode Security Description

1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode
2 Exception Privileged Execute exceptions
3 Interrupt 3 Privileged General purpose interrupt mode
4 Interrupt 2 Privileged General purpose interrupt mode
5 Interrupt 1 Privileged General purpose interrupt mode
6 Interrupt 0 Privileged General purpose interrupt mode
N/A Supervisor Privileged Runs supervisor calls
N/A Application Unprivileged Normal program execution mode

Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.

When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv­ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.

9.3.3.2 Debug State

The AVR32 can be set in a debug state, which allows implementation of software monitor rou­tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.

26

All interrupt levels are by default disabled when debug state is entered, but they can individually

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AVR32-01/12

be switched on by the monitor routine by clearing the respective mask bit in the status register.
Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.

9.3.4 System registers

The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci­fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.

Table 9-3. System Registers

AT32UC3A

Reg # Address Name Function
0 0 SR Status Register
1 4 EVBA Exception Vector Base Address
2 8 ACBA Application Call Base Address
3 12 CPUCR CPU Control Register
4 16 ECR Exception Cause Register
5 20 RSR_SUP Unused in AVR32UC
6 24 RSR_INT0 Unused in AVR32UC
7 28 RSR_INT1 Unused in AVR32UC
8 32 RSR_INT2 Unused in AVR32UC
9 36 RSR_INT3 Unused in AVR32UC
10 40 RSR_EX Unused in AVR32UC
11 44 RSR_NMI Unused in AVR32UC
12 48 RSR_DBG Return Status Register for Debug Mode
13 52 RAR_SUP Unused in AVR32UC
14 56 RAR_INT0 Unused in AVR32UC
15 60 RAR_INT1 Unused in AVR32UC
16 64 RAR_INT2 Unused in AVR32UC
17 68 RAR_INT3 Unused in AVR32UC
18 72 RAR_EX Unused in AVR32UC
19 76 RAR_NMI Unused in AVR32UC
20 80 RAR_DBG Return Address Register for Debug Mode
21 84 JECR Unused in AVR32UC
22 88 JOSP Unused in AVR32UC
23 92 JAVA_LV0 Unused in AVR32UC
24 96 JAVA_LV1 Unused in AVR32UC
25 100 JAVA_LV2 Unused in AVR32UC

27

Table 9-3. System Registers (Continued)

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AVR32-01/12

Reg # Address Name Function
26 104 JAVA_LV3 Unused in AVR32UC
27 108 JAVA_LV4 Unused in AVR32UC
28 112 JAVA_LV5 Unused in AVR32UC
29 116 JAVA_LV6 Unused in AVR32UC
30 120 JAVA_LV7 Unused in AVR32UC
31 124 JTBA Unused in AVR32UC
32 128 JBCR Unused in AVR32UC
33-63 132-252 Reserved Reserved for future use
64 256 CONFIG0 Configuration register 0
65 260 CONFIG1 Configuration register 1
66 264 COUNT Cycle Counter register
67 268 COMPARE Compare register
68 272 TLBEHI Unused in AVR32UC

AT32UC3A

69 276 TLBELO Unused in AVR32UC
70 280 PTBR Unused in AVR32UC
71 284 TLBEAR Unused in AVR32UC
72 288 MMUCR Unused in AVR32UC
73 292 TLBARLO Unused in AVR32UC
74 296 TLBARHI Unused in AVR32UC
75 300 PCCNT Unused in AVR32UC
76 304 PCNT0 Unused in AVR32UC
77 308 PCNT1 Unused in AVR32UC
78 312 PCCR Unused in AVR32UC
79 316 BEAR Bus Error Address Register
80 320 MPUAR0 MPU Address Register region 0
81 324 MPUAR1 MPU Address Register region 1
82 328 MPUAR2 MPU Address Register region 2
83 332 MPUAR3 MPU Address Register region 3
84 336 MPUAR4 MPU Address Register region 4
85 340 MPUAR5 MPU Address Register region 5
86 344 MPUAR6 MPU Address Register region 6
87 348 MPUAR7 MPU Address Register region 7
88 352 MPUPSR0 MPU Privilege Select Register region 0
89 356 MPUPSR1 MPU Privilege Select Register region 1
90 360 MPUPSR2 MPU Privilege Select Register region 2
91 364 MPUPSR3 MPU Privilege Select Register region 3

28

Table 9-3. System Registers (Continued)

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AVR32-01/12

Reg # Address Name Function
92 368 MPUPSR4 MPU Privilege Select Register region 4
93 372 MPUPSR5 MPU Privilege Select Register region 5
94 376 MPUPSR6 MPU Privilege Select Register region 6
95 380 MPUPSR7 MPU Privilege Select Register region 7
96 384 MPUCRA Unused in this version of AVR32UC
97 388 MPUCRB Unused in this version of AVR32UC
98 392 MPUBRA Unused in this version of AVR32UC
99 396 MPUBRB Unused in this version of AVR32UC
100 400 MPUAPRA MPU Access Permission Register A
101 404 MPUAPRB MPU Access Permission Register B
102 408 MPUCR MPU Control Register
103-191 412-764 Reserved Reserved for future use
192-255 768-1020 IMPL IMPLEMENTATION DEFINED

AT32UC3A

9.4 Exceptions and Interrupts

AVR32UC incorporates a powerful exception handling scheme. The different exception sources,
like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well­defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri­ority class.

When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in Table 9-4 on page 32. Most of the han­dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv­ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif­ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.

An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.

9.4.1 System stack issues

Event handling in AVR32 UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.

29

The user must also make sure that the system stack is large enough so that any event is able to

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AVR32-01/12

push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.

9.4.2 Exceptions and interrupt requests

When an event other than scall or debug request is received by the core, the following actions
are performed atomically:

1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit and Bus
Error) can not be masked. When an event is accepted, hardware automatically sets the
mask bits corresponding to all sources with equal or lower priority. This inhibits accep­tance of other events of the same or lower priority, except for the critical events listed
above. Software may choose to clear some or all of these bits after saving the neces­sary state if other priority schemes are desired. It is the event source’s responsability to
ensure that their events are left pending until accepted by the CPU.

2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2 or INT3, regis­ters R8-R12 and LR are also automatically stored to stack. Storing the Status Register
ensures that the core is returned to the previous execution mode when the current
event handling is completed. When exceptions occur, both the EM and GM bits are set,
and the application may manually enable nested exceptions if desired by clearing the
appropriate bit. Each exception handler has a dedicated handler address, and this
address uniquely identifies the exception source.

3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis­ter file bank is selected. The address of the event handler, as shown in Table 9-4, is
loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

AT32UC3A

9.4.3 Supervisor calls

9.4.4 Debug requests

The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg­ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2 or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time­critical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behav­iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.

The AVR32 architecture defines a dedicated debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the

30